Abstract: Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal.

Abstract: An apparatus for estimating head separation in an array reader magnetic recording system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a head separation estimation circuit connected to the first preamplifier and to the second preamplifier, operable to estimate an integer phase offset and a fractional phase offset between a first signal from the first read head and a second signal from the second read head.

Abstract: Method and circuits for cancelling reflected waves from a load are disclosed. An embodiment of the method includes transmitting a signal to the bad from a current source, wherein a transistor is connected in parallel with the current source at a node. The transistor is biased so that a reflected wave at the node will cause the drain to source voltage of the transistor to increase. The drain current of the first transistor increases by way of channel length modulation when the drain to source voltage increases, the increased drain current cancels the reflected wave.

Abstract: Apparatus and systems create differential drive signals suitable for HAMR data recording. A laser diode differential driver provides heating current pulses at a time ?1. The pulses energize a laser diode to pre-heat the magnetic medium to be written. Some embodiments duplicate portions of the laser diode circuit architecture to create a magnetic write head differential driver. The write head driver provides write current pulses to a magnetic write head in one direction with ?1 timing and in the opposite direction with ?2 timing. Both drivers utilize sets of reference voltages capable of being switched to one terminal or the other of the element to be driven. In the laser diode case, the common mode is split between the anode and cathode sections of the driver. A feedback element is added between the cathode and anode sections to provide current accuracy independent of the electrical characteristics of the selected laser diode.

Abstract: A recording apparatus includes a head unit, which includes a driver, and a recording data transmitter that transfers recording data to the head unit via a signal line. The recording apparatus further includes a switching unit in the head unit that switches a driving signal applied to the driver between conductive and nonconductive states based on the transferred recording data, a partition signal output unit in the recording data transmitter that outputs a partition signal that partitions a data signal of the recording data to the head unit in response to switching by the switching unit, and a data selector in the head unit that selects data to be discarded from the transferred recording data based on the partition signal.

Abstract: A write head for a magnetic storage device includes a writing tip comprising a magnetic material, a write pulse generator configured to generate a write pulse signal comprising a varying voltage bias between the magnetic storage device and the writing tip. The write pulse signal comprising one or more write pulses effective to tunnel electrons from the writing tip to the magnetic storage device. The data stream generator configured to provide a data stream signal to the writing tip where the data stream signal is operative to vary spin polarity in the electrons from a first polarity to a second polarity.

Abstract: Receiver circuits and methods of processing received signals are disclosed herein. An embodiment of a receiver circuit includes a differential input having a first input and a second input and a differential output having a first output and a second output. A first feedback loop is connected to the input and the output, wherein the first feedback loop centers a differential output voltage around a common mode output voltage so that the differential sum is zero centered on the common mode output voltage. The circuit also includes a second feedback loop, wherein the second feedback loop centers the voltage at the first input and the voltage at the second input to a reference voltage.

Abstract: Write enhancement circuitry on the head carrier of a magnetic recording disk drive provides additional write current overshoot beyond that provided by the write driver circuitry. The write enhancement circuitry is formed on the head carrier as ladder network blocks. A first ladder network block is a first capacitor C1 located in parallel with the write coil. The second ladder network block includes a second capacitor C2 having substantially the same inductance L2. The compensation circuitry is referred to as a ladder network because additional ladder blocks, like the second block but with different values of capacitance and inductance, may be located on the head carrier.

Abstract: A method and system for estimating a zero gain start (ZGS) bias in a read channel is disclosed. The method may include: receiving preamble samples within a fixed-length window selected for ZGS calculation; calculating an energy associated with a 2T frequency in the preamble samples; calculating an energy associated with non-2T frequencies in the preamble samples; and calculating the ZGS bias based on the energy associated with the 2T frequency in the preamble samples and the energy associated with non-2T frequencies in the preamble samples.

Abstract: Aspects of the disclosure pertain to a system and method for providing zero gain start (ZGS) and gain acquisition based on an adaptive analog-to-digital converter (ADC) target. The adaptive ADC target is used to collect channel characteristics and based on the adaptive ADC target, an adjusted 2T amplitude target value is generated.

Abstract: An apparatus having a controller and a preamplifier is disclosed. The controller may be configured to generate information on a serial bus coupled to a preamplifier interface. The preamplifier may be configured to (i) generate a count value in response to a clock signal synchronized to a recording medium and (ii) generate a plurality of tag signals based on the information and the count value. The tag signals may gate a read operation and a write operation of the preamplifier.

Abstract: A system including a first circuit, a second circuit, an amplifier, and a summer. The first circuit is configured to (i) select a first portion of a signal, and (ii) generate a first compensation for asymmetry in the first portion of the signal using a first function, where the first function is a modulus function. The second circuit is configured to (i) select a second portion of the signal, and (ii) generate a second compensation for asymmetry in the second portion of the signal using a second function, where the second function is different than the first function. The amplifier amplifies the signal and provides an amplified output. The summer is configured to add (i) the first compensation, (ii) the second compensation, and (iii) the amplified output, where (i) the first circuit, (ii) the second circuit, and (iii) the amplifier are connected in parallel to the summer.

Abstract: Aspects of the disclosure pertain to a system and method for providing controllable steady state current waveshaping in a preamplifier of a data storage system (e.g., hard disk drive). The preamplifier provides an output including a write current waveform having a steady state current level that is controllable via the write block circuitry of the preamplifier. This enhances the ability of the waveform to promote improved on-track and off-track write performance.

Abstract: A hard disk drive or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising a write pulse, and reflection compensation circuitry coupled to or otherwise associated with the write driver and configured to provide one or more reflection compensation pulses in the write pulse.

Abstract: A transducer is configured to interact with a magnetic storage medium, a first channel comprises a first sensor and first circuitry configured to adjust a plurality of first channel parameters, and a second channel comprises a second sensor and second circuitry configured to adjust a plurality of second channel parameters. The first and second channel parameters are independently adjustable by the first and second circuitry, respectively. A detector is coupled to the first and second channels, and configured to detect a head-medium interface event.

Abstract: In at least one embodiment, a data storage system is provided. The system includes a controller that is configured to determine a direction of current flow to a first write element to write first data on a magnetic tape and to determine a direction of current flow to each of a plurality of neighboring write elements to write corresponding data on the magnetic tape. The controller is further configured to compare the direction of current flow to the first write element to the direction of current flow to the plurality of neighboring write elements. The controller is further configured to control the first write element to write the first data in response to comparing the direction of current flow to the first write element to the direction of current flow to each of the neighboring write elements.

Abstract: A write driver circuit for generating a write current pulse for use by a magnetic write head includes an output stage adapted for connection with the magnetic write head and a charge storage circuit connected with the output stage. The charge storage circuit is operative in a first mode to store a prescribed charge and is operative in a second mode to transfer at least a portion of the charge stored therein to the output stage to thereby enable an output voltage level of the output stage to extend beyond a voltage supply rail of the write driver circuit. A control circuit in the write driver circuit is operative to generate at least one control signal for selectively controlling a mode of operation of the charge storage circuit.

Abstract: Calibrating a read channel is disclosed. Previously written user data is read from an auxiliary memory. The previously written user data is processed through a plurality of write channel stages. The output of at least one of the plurality of write channel stages is compared to the output of a corresponding read channel stage to generate an error signal.

Abstract: A system including an analog front end module, an equalizer module, a detector module, and a gain module. The analog front end module is configured to sample a signal read from a storage medium, convert the sampled signal into a digital signal, and output the digital signal. The equalizer module is configured to equalize the digital signal and output a data vector that corresponds to the equalized digital signal. The data vector represents data in the signal read from the storage medium. The detector module is configured to output a decision vector that corresponds to a noise-free ideal output vector of the decoded data vector. The gain module is configured to calculate a gain value based on the decision vector and the data vector, apply the gain value to the data vector, and output a revised data vector based on the data vector and the applied gain value.

Abstract: Embedded contact sensor controls for use in arm electronics (AE) in a disk drive are described that provide for removing undesirable offsets between the measured voltage across the ECS resistor in the slider and the balance resistor in ECS amplifier in the arm electronics (AE), which allows increased amplification of the resulting adjusted signal without saturation. Embodiments include a Zero-Offset Circuit, which can be activated periodically or on demand to sample and hold the present DC offset voltage in the ECS amplifier signal and subtract the DC offset voltage from ECS amplifier signal. The adjusted signal can then be further amplified without saturation.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to penalty based multi-variant encoding of data.

Abstract: Techniques are provided for automatic gain control loop adaptation in circuitry for processing such data signals. In one example, an apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry comprises an amplifier, a detector operatively coupled to the amplifier, and a feedback path operatively coupled between the detector and the amplifier. The amplifier is configured to receive and amplify an input signal received by the read channel circuitry. The detector is configured to detect a data pattern from the amplified input signal. The feedback path is configured to provide a feedback signal to the amplifier to adjust a gain of the amplifier, and to generate the feedback signal in accordance with a value selected to improve detection of the data pattern by increasing an amplitude of the data pattern around a given frequency.

Abstract: A balanced amplifier with a relatively high input impedance with wide bandwidth for use as a fly-height sensor head preamplifier in a magnetic storage read system. The balanced amplifier has two substantially identical halves, each amplifier half having an input transistor, responsive to the input node of the amplifier half disposed in series with a cross-coupling transistor receiving a buffered cross-coupled version of the input signal applied to the other half of the balanced amplifier. Use of cascoded transistors and voltage-followers to limit voltages across various the input and cross-coupling transistors enhance the common mode rejection and power supply rejection ratios of the amplifier while retaining a low high-frequency noise figure similar to low-input impedance balanced amplifier designs.

Abstract: A hard disk drive or other storage device comprises a storage medium, a write head, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising write pulses responsive to write data, and a driver controller configured to adjust overshoot amplitudes of respective ones of the write pulses utilizing a segmented digital-to-analog converter. The overshoot amplitudes are adjusted by detecting patterns in the write data, decoding a first portion of a base overshoot value to identify a corresponding number of base overshoot segments, combining the base overshoot value and a differential overshoot value, decoding a first portion of the combined base overshoot and differential overshoot values to identify a corresponding number of enhanced overshoot segments, and selecting between the number of base overshoot segments and the number of enhanced overshoot segments responsive to detection of a particular pattern.

Abstract: In a method and an apparatus for inspecting a thermally assisted magnetic recording head element, a specimen is mounted on a table movable in a plane of a scanning probe microscope device, evanescent light is generated from a portion of light emission of evanescent light of the specimen, scattered light of the evanescent light is detected by moving the table in the plane while a cantilever of the scanning probe microscope having a probe is vertically vibrated in the vicinity of a surface of the specimen, and an intensity distribution of the evanescent light emitted from the portion of light emission of evanescent light or a surface profile of the portion of light emission of evanescent light of the specimen is inspected using position information of generation of the evanescent light based on the detected scattered light.

Abstract: A method is disclosed for selecting a global digital-to-analog setting for a plurality of heads in a disk drive, the disk drive comprising a plurality of disk surfaces and a plurality of respective heads. The method comprises: adjusting a first digital-to-analog setting for a first head to generate a first signal, adjusting a second digital-to-analog setting for a second head to generate a second signal, selecting a first scalar setting for scaling the first signal, selecting a second scalar setting for scaling the second signal, and selecting the global digital-to-analog setting in response to the adjusted first digital-to-analog setting, the adjusted second digital-to-analog setting, the first scalar setting, and the second scalar setting.

Abstract: According to an aspect of the present disclosure, a system for correcting for DC characteristics of a magnetic recording system includes: circuitry implementing at least a portion of a write channel of the magnetic recording system; and circuitry configured to process output data of the write channel circuitry in accordance with a read channel of the magnetic recording system and repeatedly trigger re-writing through the write channel circuitry using different ones of a plurality of available data scramblings until a measured baseline wander exceeds a target threshold.

Abstract: A system including an analog front end module to receive a first signal generated by reading data from a storage medium storing the data in concentric tracks, sample the first signal, and output a second signal based on the sampling of the first signal. An equalizer module generates a first vector based on the second signal. The first vector represents the data in the first signal. A detector module generates a second vector based on the first vector. The second vector represents a noise-free vector corresponding to the first vector. A re-timing module re-samples a plurality of samples in the first vector based on the second vector and generates a third vector based on the re-sampling of the plurality of samples in the first vector. An inter-track interference cancellation module removes inter-track interference from the third vector.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise predictive filter circuit, a data detector circuit, and a first and a second pattern dependent adaptive target circuits. The noise predictive filter circuit includes at least a first pattern dependent filter circuit operable to perform noise predictive filtering on a data input for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the data input for a second pattern using a second adaptive target to yield a second noise predictive output. The data detector circuit is operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output.

Abstract: A writer assembly having two separately driven write coils allows a combined write field generated by the writer assembly to be fine turned and optimized for a particular application. Two preamplifiers may be incorporated into a printed circuit board in order to separately drive the write coils. In other implementations, there may be more than two write coils and corresponding preamplifiers.

Abstract: Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node. The bipolar transistor amplifies the input current received on the first input node, and generates an amplified input current. The load device converts the amplified input current to an output voltage, wherein the output voltage is used to sense the input current.

Abstract: Systems and methods related to writing data to a storage medium. In some cases, a heat assisted loopback circuit is used that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The loopback circuit is operable to selectively couple a derivative of a heat output to a read output and to selectively couple a derivative of a write output to the read output.

Abstract: In one embodiment, a read channel comprises: a preprocessor for receiving a first signal and producing a second signal from the first signal using current values of a positive coefficient, a zero coefficient, and a negative coefficient; an interpolator for producing a third signal based on the second signal; and a slicer for producing a fourth signal from the third signal by estimating a level for the third signal. The fourth signal is at one of three levels consisting of a positive level, a zero level, and a negative level. For every n first signals received by the preprocessor, the current value of one of the positive coefficient, the zero coefficient, and the negative coefficient is adjusted depending on which of the three levels the fourth signal is at.

Abstract: An apparatus having a controller and a preamplifier is disclosed. The controller may be configured to generate information on a serial bus coupled to a preamplifier interface. The preamplifier may be configured to (i) generate a count value in response to a clock signal synchronized to a recording medium and (ii) generate a plurality of tag signals based on the information and the count value. The tag signals may gate a read operation and a write operation of the preamplifier.

Abstract: A method comprises generating first and second magnetic field components in a magnetic medium, the second magnetic field component substantially opposite the first. A pattern is written onto the magnetic medium, and a signal is generated by reading the pattern. The magnitude of the second magnetic field component is controlled based on an asymmetry of the signal.

Abstract: Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a biasing circuit and an amplifier. The biasing circuit is configured to generate a bias voltage and a bias current based on a first resistor having a first resistance determined based on a second resistor. The amplifier is biased based on the bias voltage and bias current to generate an electrical signal that varies in response to a resistance change of the second resistor.

Abstract: A method, apparatus, and system for implementing channel signal processing assist with an embedded contact sensor (ECS) in hard disk drives. An ECS signal is captured during write and idle operation of the hard disk drive. A read channel monitors changes in the ECS signal providing a clearance monitor function for insuring write integrity.

Abstract: One embodiment includes a preamplifier system. The system includes a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path. The system also includes an output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage.

Abstract: A hard disk drive or other storage device comprises a storage medium, a read head configured to read data from the storage medium, and control circuitry coupled to the read head and configured to process data received from the read head. The control circuitry comprises read channel circuitry that includes a low-density parity check decoder or other type of decoder. Power management circuitry associated with the read channel circuitry is configured to detect a power control condition of the read channel circuitry and to control insertion of idle clock cycles in a clock signal supplied to the decoder responsive to the detected power control condition. For example, the read channel circuitry may comprise a clock generator configured to gate the clock signal responsive to a control signal from the power management circuitry.

Abstract: A system including a first filter module and a second filter module. The first filter module is configured to (i) pass a first DC shift in an input signal and (ii) convert a second DC shift in the input signal to a first component and a second component. The first DC shift is shorter in duration than the second DC shift. The second filter module is configured to detect one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift. In response to detecting one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift, the second filter module is configured to filter one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift.

Abstract: Read channel circuitry comprises a decoder and error correction circuitry. The error correction circuitry is configured to calibrate a first set of filters using a read channel data signal, to determine first hard decision information regarding the read channel data signal using the calibrated first set of filters, to determine an error corrected read channel data signal using the first hard decision information, to calibrate a second set of filters using the error corrected read channel data signal, to determine second hard decision information regarding the error corrected read channel data signal using the calibrated second set of filters, and to decode the second hard decision information. The first set of filters and the second set of filters are calibrated in respective first and second calibrators.

Abstract: Disk drives with preamp rotational parameter control (RPC) using standard digital serial interface lines to the preamp are described. The standard serial interface lines are used to generate a special signal pattern that does not follow the serial communication protocol. The special signal pattern is used to implement RPC when doing so will not interference with other signals, preferably in the read/write recovery gap between the data and the servo field in a standard track format. A value of a selected preamp parameter can be incremented or decremented by one LSB during the read/write gap time in each servo sector as the disk rotates. Embodiments of the invention allow fly-height and write driver parameters to be varied inside of a single disk revolution. Embodiments are described that include two or four parameters in the set, which allows for multiple updates of each parameter per revolution of the disk.

Abstract: A Dynamic Wave-Shaping (DWS) write driver for use in a preamp in a disk drive is described. The DWS write driver includes a Dynamic Current Booster (DCB) that adds a current component (WDCB) to the standard write driver signal (including overshoot) that is a function of the bit spacing in the write data input waveform supplied to the write driver. The invention allows dynamic control of the bit-pattern dependent overshoot amplitude without requiring significant preamp overhead. Embodiments of the Dynamic Current Booster include a programmable analog feed-forward timer at the preamp level. The boost current amplitude is a function of the time between the transitions that represent bits. In embodiments, the polarity of the boost current WDCB can be programmed to be positive or negative.

Abstract: A channel circuit includes a reader, a decoder, a prediction module, and a seek module. The reader reads data written in a medium. The decoder performs iterative decoding of the read data. The prediction module predicts whether an early read is possible or not without waiting for arrival of the read data. The seek module continuously initiates a seek when the prediction module predicts that the read is possible.

Abstract: A voltage booster is disclosed comprising an input for receiving an input voltage Vin, a first charging capacitor C1, a second charging capacitor C2, and an output capacitor Cout. The output capacitor Cout is charged to four times Vin by connecting C1 in parallel with Vin to charge C1 to Vin, after charging C1 to Vin, connecting C2 in parallel with Vin plus C1 to charge C2 to twice Vin, after charging C2 to twice Vin, connecting C1 in parallel with Vin to recharge C1 to Vin, and after recharging C1, connecting Cout in parallel with Vin plus C1 plus C2 to charge Cout to four times Vin.

Abstract: An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a plurality of interconnects and (b) the first bus. The controller may be configured to send/receive the digital control signals over the interconnects. The apparatus may be configured to (i) read/write the analog data signals to the drive and (ii) generate the digital control signals, in response to one or more input/output requests received from a drive interface.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a plurality of interconnects and (b) the first bus. The controller may be configured to send/receive the digital control signals over the interconnects. The apparatus may be configured to (i) read/write the analog data signals to the drive and (ii) generate the digital control signals, in response to one or more input/output requests received from a drive interface.