Abstract: An arrester is disclosed. In an embodiment, the arrester includes a first electrode, a second electrode, a switching contact, a first discharge space between the first and second electrodes and a short-circuiting mechanism suitable for short-circuiting the first and second electrodes and for switching a state of the arrester, wherein, in a first state, at least one electrode of the first and second electrodes is not electrically conductively connected to the switching contact and, in a second state, the at least one electrode is electrically conductively connected to the switching contact.

Abstract: An electrical bypass apparatus is provided, which comprises first and second terminals for connection across an electrical component; an electrically-triggered bypass switch being switchable to form a short circuit across the first and second terminals; and a first control circuit connected between the first and second terminals. The first control circuit includes mutually coupled first and second windings, the first winding being isolated from the second winding. The first control circuit is configured to inhibit a current flowing between the first and second terminals from flowing through the first winding when a normal operating voltage is present across the first and second terminals; and to permit a current to flow between the first and second terminals and through the first winding when an overvoltage is present across the first and second terminals and thereby induce a current pulse in the second winding.

Abstract: An electrical assembly comprises a power converter including first and second DC terminals and an AC terminal. The electrical assembly also includes a grounding circuit to connect the AC terminal to ground. The grounding circuit defines first and second current flow paths between the AC terminal and ground. The first current flow path includes a switching element. The second current flow path includes a first current flow control element that is configured to operate in a first mode in which it reduce the flow of current between the AC terminal and ground when the first current flow path is open. The electrical assembly additionally includes a control unit configured to operate the switching element to maintain open the first current flow path following an occurrence of a DC network fault. The power converter is configured to continue transferring power between the DC and AC networks throughout the DC network fault.

Abstract: Disclosed examples include integrated circuits, output driver circuits and protection circuits to protect an output transistor connected between a driver output node and a first intermediate node, including a resistor connected between the output node and a gate terminal of the output transistor, a diode connected between a second intermediate node and the output transistor gate terminal, and a switching device to electrically couple the second intermediate node with a reference node to turn on the output transistor to allow a second transistor to control a voltage of the output node when a control signal is in a first state, and to disconnect the second intermediate node from the reference node to prevent current flow through the resistor to control a gate voltage of the output transistor when the control signal is in a different second state.

Abstract: A system for testing a transient voltage suppressor (TVS) configured to be coupled between a bus and a first ground or line to discharge a voltage surge on the bus to the first ground or line includes a pulse source configured to generate an electrical pulse. The system further includes a transformer having a first side coupled to the pulse source and a second side configured to be coupled to the TVS and configured to transfer the electrical pulse to the TVS and to transfer an at least partial reflection of the electrical pulse from the TVS to the first side. The system also includes a test point coupled to the first side of the transformer and configured to receive the at least partial reflection of the electrical pulse.

Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.

Abstract: Device forming an electromagnetic lock comprising an electromagnetic suction pad (3) comprising an electromagnet (4), a counter plate (1) and an electric circuit comprising a current source designed to supply at least one coil of the electromagnet of the electromagnetic suction pad with an electric magnetization current to create an electromagnetic field and an associated electromagnetic force pinning the counter plate and the electromagnetic suction pad against one another to close the lock; switching means designed to cut off the supply of current; and anti-remanent means for dealing with the remanent electromagnetic force which remains when the switching means have disconnected the supply of current to the electromagnetic coil.

Abstract: This electrostatic protection circuit enables a high hold voltage to be set, and acts to accurately prevent breakdown of a protected circuit immediately after power on, and to prevent breakdown or deterioration of a protection device during prolonged normal operation, without connecting a resistance element in parallel to a plurality of circuit blocks connected in series. This electrostatic protection circuit is provided with a plurality of circuit blocks connected in series between a first node and a second node, at least one circuit block out of the plurality of circuit blocks including a thyristor having an anode connected to one end of the at least one circuit block and a cathode connected to the other end of the at least one circuit block.

Abstract: To extend an interface function. Provided is an electronic apparatus including: a receptacle configured to connect to a plug of a cable for connecting the electronic apparatus to an external apparatus. The receptacle includes a first power supply terminal, and a second power supply terminal having a greater current capacity than a current capacity of the first power supply terminal. For example, in the receptacle, the first power supply terminal is provided on a surface of a flat plate having a predetermined thickness, extends in a direction in which the plug is inserted, and has a first width, and the second power supply terminal is provided on an end surface of the flat plate, extends in the direction in which the plug is inserted, and has a width greater than the first width.

Abstract: A system for indicating a service need for a surge protector includes a surge protection component. The surge protection component conducts electrical power from the power source to a load when the electrical power has a voltage that is less than a predetermined threshold. The surge protection component also diverts electrical power from the load when the electrical power has a voltage that is greater than the predetermined threshold, the system. The system includes a personal area network chipset. A control circuit is communicatively coupled to the personal area network chipset. The control circuit enters a first alarm state when the surge protection component has reached an expiration date. The control circuit causes the personal area network chipset to generate a wireless alert signal indicating that the surge protection component should be replaced upon the control circuit entering the first alarm state.

Abstract: An electrostatic discharge clamp for groups of terminals having cascaded and different voltage classes, a plurality of discharge paths, and a multiple-input trigger circuit. In response to detecting a positive voltage event at any of the groups of terminals, the trigger circuitry can turn on an electronic switch causing current caused by the voltage event to flow through one or more of the discharge paths instead of through functional circuitry which could potentially be damaged by the current caused by the voltage event.

Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.

Abstract: Aspects disclosed herein include electrostatic discharge (ESD) protection in an electronic switching circuit. An electronic switching circuit includes switching circuitry configured to provide interconnectivity between a common port in at least one common branch and an input/output (I/O) port in at least one I/O branch. The common branch and the I/O branch each include a blocking capacitor element that is inherently incapable for ESD discharging. As such, an ESD clamp is disposed in parallel to the blocking capacitor element to provide a low-impedance ESD discharging path around the blocking capacitor element. By disposing the ESD clamp in parallel to the blocking capacitor element, it is possible to minimize detrimental parasitic effects of the ESD clamp, thus improving performance and reliability of the electronic switching circuit, especially for high power switching circuits such as a radio frequency (RF) switching circuits.

Abstract: The output driving circuit include a pull-down driver, an input/output (IO) control logic, a gate control logic, and an inverter. The pull-down driver includes first, second, and third transistors that are sequentially coupled between a pad and a ground node. The IO control logic is configured to receive a clock signal and an enable signal, and transfer a first control signal to the third transistor. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the first transistor. The inverter is configured to invert the enable signal and transfer an inverted enable signal to the gate control logic. Therefore, the reliability of the output driving circuit can be improved.

Abstract: Electrostatic discharge (ESD) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. A delay circuit is coupled to receive an output signal from the trigger circuit. The delay circuit includes a first inverter coupled to the input of the delay circuit and a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter. A clamp driver circuit is coupled to the output of the delay circuit.

Abstract: A semiconductor device includes an input/output circuit to which a signal is input or from which a signal is output; a first terminal connected to a power line of the input/output circuit; a second terminal connected to the power line; a resistance element connected between the second terminal and the power line; and a first capacitance element connected between the second terminal and a ground terminal. The semiconductor device can suppress a resonance phenomena and Volt age variation caused by impedance of the power line.

Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.

Abstract: Provided is a metal oxide varistor having an overcurrent protection function. The metal oxide varistor includes a metal oxide varistor body, a first electrode layer, a second electrode layer coated, an anistropic conductive paste (ACP) attached to a surface of the first electrode layer on one side of the first direction, a fuse plate bonded to the ACP and electrically conductive to the first electrode layer, a first copper-plated wire having one side of a second direction orthogonal to the first direction connected to the fuse plate, a second copper-plated wire having one side of the second direction bonded to the surface of the second electrode layer on the other side of the first direction, and an insulated coating member configured to surround the first copper-plated wire and the second copper-plated wire on one side of the second direction, the metal oxide varistor body and the fuse plate.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.

Abstract: A multi-channel transient voltage suppressor includes a plurality of diode strings, a Zener diode and a diode array. The diode strings respectively have a plurality of input output terminals. The diode array includes a first bypass diode and a second bypass diode. The first bypass diode is coupled between a common bus and a ground terminal, and provides a forward turned-on path from the ground terminal to the common bus. The second bypass diode is coupled to the first bypass diode in parallel, and provides a reverse turned-on path from the common bus to the ground terminal. A current dissipation path is formed between each of the input output terminals and the ground terminal by the diode array.

Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate and the body of the discharging transistor are electrically coupled together. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.

Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.

Abstract: A method for reducing conductor track spacings in a printed circuit board, wherein the printed circuit board has an input part, wherein the input part is fed by a supply voltage, and has an output part, comprising the following steps: inserting an intermediate conductor track which has an intermediate potential derived from the input part, maintaining a functional insulation gap between the intermediate conductor track and adjacent conductor tracks of the input part, maintaining a safety-relevant insulation gap between the intermediate conductor track and the adjacent conductor tracks of the output part. The intermediate potential has, with respect to adjacent conductor tracks of the output part, a voltage which corresponds at most to the supply voltage of the input part.

Abstract: A voltage monitor system includes a voltage rail. A voltage monitor is operatively connected to the voltage rail to monitor voltage of the voltage rail with at least one input connection. A self-test module is operatively connected to the voltage rail to perturb voltage at the at least one input connection of the voltage monitor for testing the voltage monitor.

Abstract: A liquid discharge head includes a recording element substrate including energy generating elements configured to generate energy for discharging liquid and a driving circuit configured to drive the energy generating elements, and a wiring unit including a plurality of connection terminals for connection with the main body side and electrically connected to the recording element substrate. In the wiring unit, wiring lines are respectively connected to the plurality of connection terminals, and a functional element configured to regulate an applied voltage to a predetermined voltage or less is provided between at least one signal wiring line connected to the driving circuit and used to transmit a signal for driving the energy generating element among the wiring lines and the wiring line having a relatively larger electric capacitance than that of the signal wiring line.

Abstract: An integrated circuit includes a stacked NPN having an upper NPN connected to a lower NPN. The upper NPN includes an upper collector, an upper base, and an upper emitter. The lower NPN includes a lower collector, a lower base, and a lower emitter. The upper collector includes collector segments on opposite sides of the lower emitter. The collector segments are laterally separated by collector separators which are aligned to orientation directions in the collector segments. The upper collector does not have collector separators across the orientation directions.

Abstract: A diode string for a semiconductor circuit configured with a guard ring silicon-controlled rectifier (SCR) for electrostatic discharge (ESD) protection. The diode string includes multiple NPN transistor diode structures formed in an N-well structure and electrically coupled in series between a reference voltage node and an I/O pad. Each diode structure may include a P-type retro-well structure including at least one N+ doped region and at least one P+ doped region. The P+ guard ring includes at least one P+ doped structure formed in the N-well structure disposed on either side of the first diode structure and electrically coupled to the reference voltage node. The P+ guard ring forms the SCR with the first diode structure. The diode string is triggered in response to an ESD event, which activates the SCR, and the SCR clamps the I/O pad to the reference voltage node and handles the ESD current.

Abstract: The present invention relates to a protection circuit and a ground fault circuit interrupter. A protection circuit may include a power supply circuit, a ground fault detection circuit, a signal amplifying and shaping circuit, a microcontroller control circuit, a power supply detection and indicator circuit, a tripping mechanism control circuit, and a reverse grounding detection and execution circuit. The microcontroller control includes a microcontroller, a first capacitor, and a reset filter circuit. The reset filter circuit comprises a reset IC, a second capacitor, and another capacitor. A ground fault circuit interrupter may comprise an interrupter body with a protection circuit in the interrupter body. The practice of the present disclosure may address installation safety risks of conventional ground fault circuit interrupters and arc fault circuit interrupter and improve the safety of ground fault circuit interrupters.

Abstract: Embodiments of the present invention disclose an apparatus including a power source and a plurality of electronic subsystems connected in parallel to the power source. Each of the plurality of electronic sub systems includes a circuit breaker, a transient-voltage-suppression (TVS) diode, and a load. The TVS diode is located downstream of the circuit breaker in each of the plurality of electronic systems.

Abstract: The present disclosure provides a surge protection device comprising a surge arrestor and an arrestor assistor. The surge arrestor is arranged within a circuit branch connected in parallel with a load and adapted to clamp a load voltage to a clamping voltage not larger than a load voltage limit when the load voltage rises to a breakdown voltage of the surge arrestor, the breakdown voltage increasing with a rising rate of the load voltage. The arrestor assistor is connected in parallel with the surge arrestor within the circuit branch and adapted to make the load voltage rise to the breakdown voltage not larger than the load voltage limit. The present disclosure also provides a telecommunication equipment comprising the surge protection device.

Abstract: Embodiments of the present invention disclose an apparatus including a power source and a plurality of electronic subsystems connected in parallel to the power source. Each of the plurality of electronic sub systems includes a circuit breaker, a transient-voltage-suppression (TVS) diode, and a load. The TVS diode is located downstream of the circuit breaker in each of the plurality of electronic systems.

Abstract: A power semiconductor device includes a substrate of a first conductivity type, a buried layer of a second conductivity type formed in at least a portion of the substrate, and at least one epitaxial layer of the first conductivity type formed on at least a portion of an upper surface of the substrate and covering the buried layer. The epitaxial layer and the buried layer form a junction capacitor. The device further includes at least one active power transistor formed in an upper surface of the epitaxial layer and above at least a portion of the buried layer.

Abstract: An ESD protection circuit has a diode that includes an anode connected to a first power-supply line and a cathode connected to a second power-supply line. A metal-oxide-semiconductor (MOS) transistor is connected in series with the diode. A trigger circuit is configured to output a trigger signal to a gate of the MOS transistor in synchronization with a surge on the first power-supply line. A first resistor and a first capacitor are connected in series between the first power-supply line and the second power-supply line. A well region, in which the source and the drain of the MOS transistor are disposed, is connected to a connection point between the first resistor and the first capacitor. A potential of the connection point varies so that a forward voltage is applied to a p-n junction between the well region and the source of the MOS transistor to correspond with the surge.

Abstract: The invention relates to an overvoltage protection device with leakage current cutoff, having a parallel connection of a first current branch and a second current branch, wherein the first current branch comprises a switching element and a first non-linear resistor element, and the second current branch comprises a securing element with signaling properties and a second non-linear resistor element and a complex resistor. Dependent on a state modification of the securing element with signaling properties, said switching element is switched.

Abstract: A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.

Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.

Abstract: A semiconductor device includes a first circuit block that is connected between a first power supply voltage line and a first reference voltage line, a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block, a first clamp circuit that clamps a potential difference between the second power supply voltage line and the first reference voltage line, a resistor circuit that is connected between the second power supply voltage line and the second circuit block and includes a resistance value that is greater than an impedance of the first clamp circuit, and a second clamp circuit that clamps a potential difference between a line connected between the resistor circuit and the second circuit block and the first reference voltage line.

Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.

Abstract: An electrostatic discharge protection circuit includes a transistor device, a first timing circuit including a first resistor and a first capacitor that is connected with the first resistor at a first node, a second timing circuit including a second resistor and a second capacitor that is connected with the second resistor at a second node, and a logic gate including a first input connected with the first node, a second input coupled with the second node, and an output connected with the transistor device.

Abstract: Provided is a relay unit that is inexpensive and has a long life, and a method for controlling a relay circuit. A series circuit of mechanical switches is connected in series to a load and a load power supply, and a control unit selects one of the mechanical switches as a selected switch, and performs a switching timing shift, which is constituted by at least one of a first operation in which the selected switch is switched to the closed state after the mechanical switch other than the selected switch, and a second operation in which the selected switch is switched to the open state prior to the mechanical switch other than the selected switch.

Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.

Abstract: Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.

Abstract: A spark-preventing element embedded in a printed circuit board includes a capacitive output electrode, a capacitive input electrode, an interlayer conductive member electrically connecting the capacitive output electrode to a signal line, and an interlayer insulation member electrically insulating the capacitive input electrode from the signal line, The capacitive input electrode is spaced apart from the capacitive output electrode with an air gap disposed between the capacitive output electrode and the capacitive input electrode, surrounds the capacitive output electrode, and is electrically connected to the ground layer. The spark-preventing element has an improved electrical characteristic and an increased durability.

Abstract: An overcharge protection circuit comprises a first series of first terminals a second series of second terminals, a first overvoltage protection device connected between each consecutive pair of first terminals, a current balancing device connected between each consecutive pair of second terminals, and a second overvoltage protection device connected between a first terminal and a second terminal. The second overvoltage protection device is configured to pass a current if a voltage over the second overvoltage protection device exceeds a threshold. The second overvoltage protection device may comprise a bidirectional ESD diode, while both the first overvoltage protection device and the second overvoltage protection device may comprise a unidirectional ESD diode.

Abstract: The present disclosure relates to a reverse grounding protection circuit and a ground fault circuit interrupter. The reverse grounding protection circuit may include a power supply circuit, a leakage signal amplifying circuit, a leakage grounding detection circuit, a power supply indicator circuit, a manual detection circuit, a tripping mechanism control circuit, a reverse connection detection and execution circuit, and a power-on driving signal generating circuit. A ground fault circuit interrupter may comprise an interrupter body and a reverse grounding protection circuit in the interrupter body. The practice of the present disclosure may avoid the risk from reverse connection of the ground fault circuit interrupter and output of power of reverse connection, and thus improve safety of the ground fault circuit interrupter.

Abstract: Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Abstract: Circuits and methods concerning voltage surge protection are disclosed. In an example embodiment, an apparatus includes a switching circuit configured to enable a current path between a first node and a second node in a first mode and disable the current path in a second mode. A biasing circuit configured to, in the surge protection mode, prevent a voltage surge at the first node from enabling the current path to the second node by biasing a voltage of the control node.

Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.

Abstract: An overvoltage protector uses a low-power shunt regulator to provide precise overvoltage protection at low voltages. The shunt regulator communicates with the current limiter to the input voltage allowing precise current measurement while protecting the shunt regulator from excessive power consumption.