Abstract: A multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked, wherein a concentration of a rare earth element in an active region with respect to a main component ceramic of the active region is equal to or more than a concentration of a rare earth element in at least a part of a protective region with respect to a main component ceramic of the protective region, wherein an average ionic radius of the rare earth element of the at least a part of the protective region is equal to or less than an average ionic radius of the rare earth element in the active region.

Abstract: A multilayer ceramic electronic component includes a laminate including dielectric ceramic layers and at least a pair of internal electrode layers laminated together, the laminate including a pair of main surfaces that oppose each other in a lamination direction, a pair of side surfaces that oppose each other in a width direction perpendicular or substantially perpendicular to the lamination direction, and a pair of end surfaces that oppose each other in a length direction perpendicular or substantially perpendicular to the lamination direction and the width direction, a pair of side surface layers respectively provided on the side surfaces of the laminate, a pair of main surface layers covering interfaces between the laminate and the side surface layers respectively provided on the main surfaces of the laminate, and a pair of external electrodes respectively connected to the internal electrode layers respectively provided on the end surfaces of the laminate.

Abstract: A ceramic electronic device includes: a multilayer chip having a multilayer structure and a cover layer, the multilayer structure having a structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, respective one ends of the plurality of internal electrode layers being alternately exposed to a first end face and a second end face of the multilayer structure, the cover layer being provided on each of an upper face and a lower face of the multilayer structure in a stacking direction of the multilayer structure, a main component of the cover layer being ceramic, wherein in each of two side faces of the multiplayer structure, a color of a first region is different from a color of a second region that is positioned at a height different from the first region in the stacking direction.

Abstract: A multilayer electronic component includes a multilayer body including dielectric layers and inner electrode layers. Each of the dielectric layers includes first crystal grains defining and functioning as plate-shaped objects that have an average thickness of less than or equal to about 300 nm and an average aspect ratio of more than or equal to about 5, each of the inner electrode layers includes second crystal grains defining and functioning as plate-shaped objects that have an average thickness of less than or equal to about 150 nm and an average aspect ratio of more than or equal to about 5, where an aspect ratio is represented by a ratio of a major axis of each plate-shaped object to a thickness of the plate-shaped object with the major axis of the plate-shaped object being orthogonal or substantially orthogonal to a thickness direction of the plate-shaped object.

Abstract: A multilayer ceramic electronic component includes a ceramic body comprising dielectric layers and first and second internal electrodes laminatedly disposed in a third direction with respective dielectric layers interposed therebetween, and first electrode and second external electrodes disposed on both surfaces of the ceramic body in the first direction and electrically connected to the first and second internal electrodes. When an absolute value of a horizontal angle in the second direction of the first internal electrode with respect to the first surface of the ceramic body is referred to a first angle of the internal electrode, a total sum of the first angles is less than 10°.

Abstract: A multi-layer ceramic electronic component includes: a ceramic body including a multi-layer unit having a side surface facing in a direction of a first axis and including internal electrodes laminated in a direction of a second axis orthogonal to the first axis and having end portions on the side surface, and a side margin including a first inner layer adjacent to the side surface and including a first region containing a glass component, a first outer layer outside of the first inner layer, and a ridge positioned at an end portion of the first outer layer in the direction of the second axis and including a second region containing a glass component at a lower concentration than a concentration of the glass component of the first region, the side margin having a dimension of 13 ?m or less in the direction of the first axis; and an external electrode.

Abstract: A dielectric composition includes main phases and Ca-RE-Si—O segregation phases. The main phases include a main component expressed by ABO3. “A” includes at least one selected from barium and calcium. “B” includes at least one selected from titanium and zirconium. “RE” represents at least one of rare earth elements. A molar ratio of (Si/Ca) is larger than one. A molar ratio of (Si/RE) is larger than one, provided that the molar ratio of (Si/RE) is a molar ratio of silicon included in the segregation phases to the rare earth elements included therein. An average length of major axes of the segregation phases is 1.30-2.80 times as large as an average particle size of the main phases. An average length of minor axes of the segregation phases is 0.21-0.48 times as large as an average particle size of the main phases.

Abstract: A multilayer ceramic capacitor includes a laminated body in which dielectric layers and internal electrodes are laminated alternately. The dielectric layer includes a first phase that contains calcium strontium zirconate titanate as a main component thereof and a second phase that contains barium zirconate as a main component thereof. At a cross section of the dielectric layer, a line parallel to the direction in which the dielectric layers and the internal electrodes are laminated contacts the boundaries between the first phase and the second phase once or more on average, thereby the statistically averaged contact number N of such a line with the boundaries determined by a prescribed procedure being 1.0 or greater.

Abstract: A multilayer ceramic electronic component includes a ceramic body having a capacitance forming portion including dielectric layers and first and second internal electrodes laminated with respective dielectric layers interposed therebetween, a first external electrode connected to the first internal electrode and including a first conductive layer and a first band portion, and a second external electrode connected to the second internal electrode and including a second conductive layer and a second band portion. Tb/Tc is 0.85 or more, where Tc is a maximum thickness of each of the first and second conductive layers and Tb is a maximum thickness of each of the first and second band portions.

Abstract: A ceramic electronic component includes a multilayer structure including dielectric layers and internal electrode layers, the internal electrode layers being alternately exposed to two edge faces of the multilayer chip opposite to each other. A rare earth element of a side margin has an ionic radius smaller than that of a rare earth element of a capacity section. The rare earth element of the side margin is a rare earth element when only the rare earth element is added to the side margin, or a rare earth element with a largest amount when rare earth elements are added to the side margin. The rare earth element of the capacity section is a rare earth element when only the rare earth element is added to the capacity section, or a rare earth element with a largest amount when rare earth elements are added to the capacity section.

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and inner electrodes stacked in an alternating manner, and first, second, third, and fourth outer electrodes provided on a surface of the multilayer body. An effective portion includes a capacitance generating portion in which first and second inner electrodes face each other to generate an electrostatic capacitance, a first successive stacking portion in which first inner electrodes are successively stacked, and a second successive stacking portion in which second inner electrodes are successively stacked. The following relational expressions (1) and (2) are satisfied. (1) about 0.168?Total thickness of inner electrodes/Dimension of multilayer body in stacking direction. (2) about 0.19?Total number of first and second inner electrodes opposing each other with dielectric layers interposed therebetween/Total number of inner electrodes?about 0.48.

Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second electrode layers laminated in a lamination direction, and first and second external electrodes respectively connected to the first and second internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The first and second internal electrode layers and the first and second external electrodes include Ni. In a cross section including the lamination direction and a width direction, a Ni content of the peripheral layer portion is larger at a surface portion than at a central portion in a thickness direction, and a Ni content of the side margin is larger at a surface portion than at a central portion in a thickness direction of the side margin.

Abstract: A multi-layer ceramic electronic component includes a multi-layer unit and a side margin. The multi-layer unit includes ceramic layers laminated in a first direction, and internal electrodes disposed between the ceramic layers, positions of end portions of the internal electrodes in a second direction orthogonal to the first direction being aligned with one another within a range of 0.5 ?m in the second direction. The side margin includes a center portion in the first direction and a third direction orthogonal to the first direction and the second direction, and corner portions in the first direction and the third direction, the corner portions having a lower porosity than a porosity of the center portion, the side margin covering the multi-layer unit from the second direction.

Abstract: A ceramic electronic device includes: a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked, the multilayer chip having a rectangular parallelepiped shape, the plurality of internal electrode layers being alternately exposed to a first end face and a second end face of the multilayer chip, the first end face facing with the second end face, a first external electrode provided on the first end face; a second external electrode provided on the second end face; and an organic compound that is adhered to at least a part of a region including a surface of the multilayer chip where neither the first external electrode nor the second external electrode is formed and surfaces of the first external electrode and the second external electrode, and has a siloxane bonding.

Abstract: A ceramic electronic device includes: a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, a main component of the dielectric layers being ceramic, wherein a relationship of IA/IB>1.40 is satisfied in a TSDC (Thermally Stimulated Depolarization Currents) of temperature elevation rate of 10 degrees C./min under a condition of 130 degrees C., 5 V/?m and a polarization of 30 min, when a peak current value on a lower temperature side in a temperature range of 130 degrees C. to 190 degrees C. is IA and a peak current value on a higher temperature side in a temperature range of 190 degrees C. to 280 degrees C. is IB.

Abstract: A multilayer ceramic capacitor includes a capacitive element including a stack of ceramic layers and internal electrodes, and external electrodes on a surface of the capacitive element. Each of the external electrodes includes a base electrode layer on the surface of the capacitive element and a Cu-plated electrode layer on a surface of the base electrode layer and including an edge portion facing the surface of the capacitive element. Sn is provided between the edge portion of the Cu-plated electrode layer and the surface of the capacitive element. On a surface of the Cu-plated electrode layer, at least one second plated electrode layer including an edge portion facing the surface of the capacitive element is provided.

Abstract: A method of manufacturing an electronic component includes preparing an unfired multilayer body including first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction, and first and second end surfaces facing each other in a length direction, bonding one main surface of the unfired multilayer body to an elongated first adhesive sheet, conveying the first adhesive sheet in a first direction in which the first adhesive sheet approaches an elongated second adhesive sheet, and bonding one side surface of the unfired multilayer body to the second adhesive sheet, conveying the second adhesive sheet in a second direction different from the first direction to peel off the unfired multilayer body from the first adhesive sheet, polishing another side surface of the unfired multilayer body, and forming a first insulating layer on the polished another side surface.

Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and having first and second surfaces opposing each other in a width direction, third and fourth surfaces connecting the first and second surfaces in a length direction, and fifth and sixth surfaces opposing each other in a thickness direction, internal electrodes disposed inside the ceramic body, exposed through the first and second surfaces, and having one end portion exposed through the third or fourth surface, and first and second side margin portions disposed on edges of the internal electrodes, exposed through the first and second surfaces. In a cross-section cut along a width-thickness plane of the ceramic body, an area of an oxide region disposed on the edges of the internal electrodes is less than 10% of an overall area of the internal electrodes exposed through the first and second surfaces.

Abstract: In a multilayer ceramic capacitor, when a ratio of an ICP peak intensity of Mn to an ICP peak intensity of Ti is an Mn/Ti peak intensity ratio, a value of the Mn/Ti peak intensity ratio in a dielectric ceramic layer in at least one of a main surface outer layer portion, a side surface outer layer portion, and an end surface outer layer portion is in a range of two times to fifteen times a value of the Mn/Ti peak intensity ratio in a dielectric ceramic layer in a central portion of an effective portion in a width direction, a length direction, and a stacking direction.

Abstract: A multilayer ceramic capacitor include: a ceramic body including first and second surfaces opposing each other and third and fourth surfaces connecting the first and second surfaces; a plurality of internal electrodes disposed inside the ceramic body and exposed to the first and second surfaces, the plurality internal electrodes each having one end exposed to the third or fourth surface; and first and second side margin portions disposed on sides of the internal electrodes exposed to the first and second surfaces. A dielectric composition of the first and second side margin portions is different from a dielectric composition of the ceramic body, and a dielectric constant of the first and second side margin portions is lower than a dielectric constant of the ceramic body.

Abstract: A multilayer capacitor and a board on which the multilayer capacitor is mounted provide increased capacitor effective area. The multilayer capacitor includes a capacitor body having first and second dielectric layers each with first and second internal electrodes, first and second external electrodes disposed on a surface of the capacitor body, a first via electrode connecting the first internal electrodes to the first external electrode, and a second via electrode connecting the second internal electrodes to the second external electrode. The first and second dielectric layers are alternately stacked in the first direction such that the first internal electrode of the first dielectric layer overlaps the second internal electrode of the second dielectric layer in a first direction, and the second internal electrode of the first dielectric layer overlaps the first internal electrode of the second dielectric layer in the first direction.

Abstract: A dielectric composition includes one of BaTiO3, (Ba,Ca) (Ti,Ca)O3, (Ba,Ca) (Ti,Zr)O3, Ba(Ti,Zr)O3 and (Ba,Ca) (Ti,Sn)O3, as a main component, a first subcomponent including a rare earth element, and a second subcomponent including at least one of a variable valence acceptor element and a fixed valence acceptor element. When a sum of contents of the rare earth element is defined as DT and a sum of contents of the variable valence acceptor element and the fixed valence acceptor element is defined as AT, (DT/AT)/(Ba+Ca) satisfies more than 0.5 and less than 6.0. In addition, a multilayer electronic component including the dielectric composition is provided.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer and a plurality of internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, and an external electrode formed outside the ceramic body. The external electrode includes an electrode layer, and a thickness T1 of the electrode layer corresponding to a central region of the ceramic body in a thickness direction is 5 ?m or more and 30 ?m or less, a thickness T2 of the electrode layer corresponding to a region in which an outermost internal electrode is located is 5 ?m or more and 15 ?m or less, and a thickness T3 of the electrode layer corresponding to a corner portion of the ceramic body is 0.1 ?m or more and 10 ?m or less.

Abstract: A multi-layer ceramic capacitor includes a multi-layer unit and a side margin. The multi-layer unit includes a capacitance forming unit and a cover. The capacitance forming unit includes ceramic layers laminated in a first direction and internal electrodes disposed between the ceramic layers and mainly containing nickel. The cover covers the capacitance forming unit from the first direction. The side margin covers the multi-layer unit from a second direction orthogonal to the first direction. The internal electrodes each include an oxidized area adjacent to the side margin and intensively including a metal element that forms an oxide together with nickel. The capacitance forming unit includes a first portion adjacent to the cover and a second portion adjacent to the first portion in the first direction and including the oxidized area having a smaller dimension in the second direction than that of the oxidized area of the first portion.

Abstract: An electronic component includes an element body and an external electrode disposed on the element body. The external electrode includes a conductive resin layer, a solder plating layer arranged to constitute an outermost layer of the external electrode, and an intermediate plating layer disposed between the conductive resin layer and the solder plating layer. The intermediate plating layer has better solder leach resistance than metal contained in the conductive resin layer. An opening is formed in the intermediate plating layer. The solder plating layer is formed on the conductive resin layer through the opening.

Abstract: A multilayer capacitor includes a capacitor body including first and second dielectric layers, a plurality of internal electrodes, and a plurality of second internal electrodes, and first and second external electrodes. First and second internal electrodes are disposed in one of the first dielectric layers to be spaced apart from each other. The first and second internal electrodes are disposed in one of the second dielectric layers to be spaced apart from each other. The first and second dielectric layers are alternately laminated in the first direction, such that the first internal electrode of the first dielectric layer and the second internal electrode of the second dielectric layer overlap each other in the first direction and the second internal electrode of the first dielectric layer and the first internal electrode of the second dielectric layer overlap each other in the first direction.

Abstract: A composite electronic component includes a composite body including a multilayer ceramic capacitor and a ceramic chip coupled to each other. The multilayer ceramic capacitor includes a first ceramic body and first and second external electrodes, and the ceramic chip is disposed below the multilayer ceramic capacitor and includes a second ceramic body having first and second terminal electrodes. The multilayer ceramic capacitor and the ceramic chip are coupled by solder disposed between the first and second external electrodes and the first and second terminal electrodes, and each angle (?) defined by inner side surfaces of the solder, respectively disposed on inner ends of bent portions of the first and second terminal electrodes disposed on an upper surface of the second ceramic body, and an upper plane of the second ceramic body of the ceramic chip satisfies 45 degrees or less.

Abstract: An electronic component includes an element body and an external electrode. The element body includes a principal surface arranged to constitute a mounting surface and an end surface adjacent to the principal surface. The external electrode includes a conductive resin layer disposed to continuously cover a part of the principal surface and a part of the end surface, and a plating layer covering the conductive resin layer. The conductive resin layer includes a first region positioned on the end surface, a second region positioned on a ridge portion between the end surface and the principal surface, and a third region positioned on the principal surface. In a case where a maximum thickness of the first region is T1 (?m) and a minimum thickness of the second region is T2 (?m), the maximum thickness T1 and the minimum thickness T2 satisfy a relation of T2/T1?0.26.

Abstract: A composite electronic component includes a composite body including a multilayer ceramic capacitor and a ceramic chip coupled to each other. The multilayer ceramic capacitor includes a first ceramic body in which dielectric layers and internal electrodes disposed to face each other with one of the dielectric layers interposed therebetween are stacked, and first and second external electrodes disposed on opposite end portions of the first ceramic body, respectively. The ceramic chip is disposed below the multilayer ceramic capacitor, and includes a second ceramic body including ceramic and first and second terminal electrodes disposed on opposite end portions of the second ceramic body, respectively, and connected to the first and second external electrodes, respectively. A ratio (T1/T2) of a thickness (T1) of the multilayer ceramic capacitor to a thickness (T2) of the ceramic chip satisfies 1.6?(T1/T2)?3.5.

Abstract: Provided is a multilayer capacitor and a board on which the multilayer capacitor is mounted. The multilayer capacitor includes a capacitor body including first to six surfaces, first and second dielectric layers, and first and second internal electrodes; first and second external electrodes disposed on the first surface of the capacitor body; the first and second dielectric layers are alternately layered in a first direction such that the first internal electrode of the first dielectric layer overlaps the second internal electrode of the second dielectric layer in the first direction, and the second internal electrode of the first dielectric layer overlaps the first internal electrode of the second dielectric layer in the first direction.

Abstract: A multilayer ceramic electronic component includes a ceramic body having a dielectric layer and an internal electrode, an electrode layer connected to the internal electrode, and a conductive resin layer disposed on the electrode layer and including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin. The conductive carbon is included in the conductive resin layer in an amount of 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal.

Abstract: A multilayer ceramic capacitor includes a laminate and an external electrode, the laminate includes a central layer portion in which first and second internal electrode layers are alternately laminated with a dielectric ceramic layer therebetween, a peripheral layer portion sandwiching the central layer portion in a lamination direction and made of a ceramic material, and a side margin sandwiching the central layer portion and the peripheral layer portion in a width direction and made of a ceramic material, the side margin includes an inner layer on an innermost side in the width direction and an outer layer on an outermost side in the width direction, and an element of an additive of the ceramic material included in the peripheral layer portion is the same as an element of an additive of a ceramic material included in the inner layer.

Abstract: A dielectric ceramic composition and a multilayer ceramic capacitor comprising the same are provided. The dielectric ceramic composition includes a BaTiO3-based base material main ingredient and an accessory ingredient, where the accessory ingredient includes dysprosium (Dy) and cerium (Ce) as first accessory ingredients. A total content of Dy and Ce is greater than 0.25 mol % and equal to or less than 1.0 mol % based on 100 mol % of the base material main ingredient.

Abstract: A multilayer capacitor includes: a capacitor body formed by placing two or more stacked units in a row in a stacking direction of dielectric layers, each stacked unit including a plurality of dielectric layers, and a plurality of first and second internal electrodes alternately disposed with the dielectric layers interposed therebetween; and first and second external electrodes disposed on the capacitor body to be electrically connected to the first and second internal electrodes, respectively, and, in the capacitor body, adjacent stacked units are disposed to allow surfaces with similar density to be adjacent to each other.

Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second internal electrode layers laminated in a lamination direction, and first and second external electrode connected to the internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The side margin including an inner layer and an outer layer. In a cross section including a lamination direction and a width direction obtained by cutting the laminate at a central portion in a length direction, Si is segregated in an inner region including the inner layer and a boundary between the inner layer and the central layer portion, and a Si segregation spot in the inner region has a larger area than a Si segregation spot in the outer layer.

Abstract: A multilayer ceramic electronic component includes a ceramic body; and first and second external electrodes disposed on the ceramic body, wherein the first and second external electrodes include first and second conductive layers disposed on corners of the ceramic body, and first and second base electrodes covering the first and second conductive layers, respectively, and wherein a ratio, A1/A2, of an area, A1, of the first conductive layer disposed on the fifth surface or the second conductive layer disposed on the sixth surface of the ceramic body to an area, A2, of a cross-sectional surface of the ceramic body taken in the second direction and the first direction is in a range of 0.1 to 0.3.

Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes, and external electrodes. The corners of the cover portions of the body include curved surfaces, a length of each of internal electrodes disposed in the cover portions among the plurality of internal electrodes is smaller than a length of an internal electrode disposed in a central portion, and when a distance from a surface of the body to a closest internal electrode among the plurality of internal electrodes is defined as a margin, a portion of the margin region, located directly above or below the internal electrodes disposed in the cover portions in the stacking direction, includes at least two layers including different densities of dielectric layers.

Abstract: A multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers and a plurality of electrode regions. The plurality of electrode regions can include a dielectric region, an active electrode region, and a shield electrode region. The active electrode region may be located between the dielectric region and the shield electrode region in a Z-direction. The dielectric region may extend from the active electrode region to the top surface of the broadband multilayer ceramic capacitor. The capacitor may include a plurality of active electrodes arranged within the active electrode region and at least one shield electrode arranged within the shield electrode region. The dielectric region may be free of electrode layers that extend greater than 25% of a length of the capacitor. A ratio of a capacitor thickness to a thickness of the dielectric region may be less than about 20.

Abstract: A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of first and second internal electrodes; and first and second external electrodes provided at each of both end faces of the ceramic body. Each of the plurality of dielectric layers contain Ba, Ti, P and Si. The plurality of dielectric layers include an outer dielectric layer located on an outermost side in the stacking direction; an inner dielectric layer located between the first and second internal electrodes; and a side margin portion in a region where the first and second internal electrodes do not exist. In at least one of the outer dielectric layer, the inner dielectric layer and the side margin portion, the P and the Si segregate in at least one of grain-boundary triple points of three ceramic particles.

Abstract: An element body includes a principal surface arranged to constitute a mounting surface and a first side surface adjacent to the principal surface. An external electrode includes a first electrode portion disposed on the principal surface and a second electrode portion disposed on the first side surface. The first electrode portion includes a sintered metal layer, a conductive resin layer formed on the sintered metal layer, and a plating layer formed on the conductive resin layer. The second electrode portion includes a first region and a second region. The first region includes a sintered metal layer and a plating layer formed on the sintered metal layer. The second region includes a sintered metal layer, a conductive resin layer formed on the sintered metal layer, and a plating layer formed on the conductive resin layer. The second region is located closer to the principal surface than the first region.

Abstract: The present invention provides a method of fabrication and device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes or post to form one or more high surface area capacitive device for monolithic system level integration on a glass substrate.

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

Abstract: A multilayer ceramic capacitor includes a laminated body including dielectric layers and internal electrode layers alternately laminated in a width direction, and first and second external electrodes on a bottom surface of the laminated body. Among ridges located on a side of an upper surface of the laminated body of an inner layer generating capacitance, a ridge located on the side of a first end surface is a first ridge, and a ridge located on the side of a second end surface is a second ridge. When r1 is a curvature radius of the first ridge at a central position in the width direction of the laminated body, and r2 is a curvature radius of the second ridge at the central position in the width direction of the laminated body, conditions of r1?50 ?m and r2?50 ?m are satisfied.

Abstract: A multilayer ceramic capacitor includes a multilayer body in which a plurality of internal electrodes including Ni and a plurality of ceramic dielectric layers are alternately stacked, and external electrodes. The ceramic dielectric layer includes an inner dielectric layer located between internal electrodes, and an outer dielectric layer located outside in a stacking direction and including at least NiO. A difference between average grain sizes of dielectric grains of the outer dielectric layers and the inner dielectric layers is about 10% or less. A molar amount of NiO with respect to about 100 moles of Ti is larger by about 0.6 mole or more in the outer dielectric layer than in the inner dielectric layer.

Abstract: An element body includes a principal surface arranged to constitute a mounting surface and a first side surface adjacent to the principal surface. An external electrode includes a first electrode portion disposed on the principal surface and a second electrode portion disposed on the first side surface. The first electrode portion includes a sintered metal layer, a conductive resin layer formed on the sintered metal layer, and a plating layer formed on the conductive resin layer. The second electrode portion includes a first region and a second region. The first region includes a sintered metal layer and a plating layer formed on the sintered metal layer. The second region includes a sintered metal layer, a conductive resin layer formed on the sintered metal layer, and a plating layer formed on the conductive resin layer. The second region is located closer to the principal surface than the first region.

Abstract: The present invention is directed to a multilayer ceramic capacitor. A plurality of active electrodes may be arranged within a monolithic body of the capacitor and parallel with a longitudinal direction. A first shield electrode may be arranged within the monolithic body and parallel with the longitudinal direction. The first shield electrode may be connected with a first external terminal. The first shield electrode may have a first longitudinal edge and a second longitudinal edge that are each aligned with the lateral direction and face away from the first external terminal. The second longitudinal edge may be offset in the longitudinal direction from the first longitudinal edge by a shield electrode offset distance. A second shield electrode may be connected with a second external terminal. The second shield electrode may be approximately aligned with the first shield electrode in the Z-direction.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer, and first and second internal electrodes disposed to oppose each other with the dielectric layer therebetween; first and second external electrodes having first electrode layers electrically connected to the first and second internal electrodes, respectively, and second electrode layers disposed on the first electrode layers, respectively; and an auxiliary electrode disposed between an end portion of each of the first electrode layers and an inflection point of the ceramic body. A width of the auxiliary electrode is in a range of 20 to 70% of a width of a margin portion of the first or second internal electrode.

Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

Abstract: A broadband multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers stacked in the Z-direction, a first external terminal, and a second external terminal. A plurality of active electrodes, a bottom shield electrode, and a top shield electrode may be arranged within the monolithic body. The top shield electrode may be positioned between the active electrodes and a top surface of the capacitor and spaced apart from the top surface of the capacitor by a top-shield-to-top distance. A bottom shield electrode may be positioned between the active electrodes and the bottom surface of the capacitor and spaced apart from the bottom surface of the capacitor by a bottom-shield-to-bottom distance. A ratio of the top-shield-to-top distance to the bottom-shield-to-bottom distance may be between about 0.8 and about 1.2. The bottom-shield-to-bottom distance may range from about 8 microns to about 100 microns.

Abstract: A multilayer capacitor and a board having the same mounted thereon are provided. The multilayer capacitor includes a capacitor body including dielectric layers and first and second internal electrodes, and first to sixth surfaces, the first internal electrode being exposed through the third surface and the fifth surface and the second internal electrode being exposed through the fourth surface and the sixth surface; first and second side portions disposed on the fifth and sixth surfaces, respectively, of the capacitor body; first and second external electrodes; a first step-compensating portion disposed on a margin portion in a width direction on the second dielectric layer on which the second internal electrode is formed on the first internal electrode; and a second step-compensating portion disposed on another margin portion in the width direction on the first dielectric layer on which the first internal electrode is disposed on the second internal electrode.