Abstract: A variable IC capacitor includes a semiconductor layer doped to contain mobile charge carriers. Capacitor electrodes C1 and C2 are disposed adjacent to each other on the layer's surface, gate electrodes G1 and G2 are disposed on opposite sides of C1 and C2, and source and sink electrodes are disposed on opposite sides of G1 and G2. Potentials are applied to the electrodes as needed to inject and then confine a finite charge into the region under C1 and C2. A drive voltage V applied between C1 and C2 causes the charge packet to move back and forth beneath them, such that the effective capacitance C seen by drive voltage V is given by C=Q/V, where Q is the magnitude of the charge packet.

Abstract: Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

Abstract: A thin-dielectric unit capacitor is disclosed having a first node coupled to a first circuit connection point and a second node coupled to a second circuit connection point. It further contains a first and second thin-dielectric capacitors connected in series between the first and second nodes, wherein a thickness of a gate dielectric for each thin-dielectric capacitor is less than 50 angstroms.

Abstract: The invention proposes an interposer assembly architecture for noise suppression circuits on the package of a CPU or high power, high frequency VLSI device. In this architecture, charge is stored on dedicated capacitors at a voltage substantially higher than the operating voltage of the VLSI device. These capacitors are mounted upon active circuits that are packaged to match the size and form factor of the capacitors and this assembly is then attached to the package substrate. Charge is conveyed from the capacitor terminals on the backside of the packaged active circuits chip. Depending upon the capacitor construction, these terminals may either be double-sided contact terminals along the edge of the active device's package, or may be feed-through contacts.

Abstract: A method for attaching a capacitor to the feedthrough assembly of a medical device having a terminal pin comprises threading a first washer over the terminal pin, and placing a body of epoxy in contact with the first washer. The capacitor is positioned over the terminal pin such that the first washer and the body of epoxy are between the lower surface of the capacitor and a support surface. The body of epoxy is cured to couple the capacitor to the insulating structure. During curing, the body of epoxy is substantially confined between the upper surface and the lower surface by the ferrule, the insulating structure, the capacitor, and the first washer.

Abstract: A decoupling capacitor includes a first MOS transistor having a first conductivity type. The first MOS transistor functions as a resistor element due to an on-resistance between its source and drain. The source is connected to first power supply wiring. The decoupling capacity further includes a second MOS transistor having a second conductivity type. The second MOS transistor is connected to second power supply wiring. The second MOS transistor functions as a capacitor element and has a gate length greater than that of the first MOS transistor.

Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A semiconductor device having the thin film capacitor includes a first electrode formed on a substrate, a capacitor insulating film containing a laminated film, which is constructed by laminating an amorphous dielectric film and a polycrystalline dielectric film via a wave-like interface, on the first electrode, and a second electrode formed on the capacitor insulating film.

Abstract: A capacitor having a first nickel electrode. A BCTZ dielectric covers a side of the first nickel electrode. A second nickel electrode sandwiches the BCTZ.

Abstract: A capacitor charging semiconductor apparatus including a plurality of serially connected capacitors to be charged. A direct current source is applied to the plurality of capacitors. A plurality of bypass transistors is provided to bypass charge current supplied to the plurality of capacitors when a voltage of a capacitor exceeds a prescribed reference level. A plurality of parallel monitor circuits is provided to control the plurality of bypass transistors to equally charge the plurality of capacitors. A plurality of capacitor connection terminals is connected to both ends and intersections of the plurality of capacitors. A plurality of transistor connection terminals is connected to the plurality of control terminals of the bypass transistor. A prescribed number of capacitors is optionally charged by increasingly shorting a number of capacitor connection terminals from the highest and lower voltage side capacitor connection terminals.

Abstract: A feedthrough filter capacitor assembly includes a conductive terminal pin which extends through a first passageway of a capacitor in conductive relation with a first set of electrode plates, and through a conductive ground plane and an insulator in non-conductive relation. The insulator includes ground plates conductively coupled to the ferrule. A second set of electrode plates of the capacitor are conductively coupled to the insulator ground plates, such as by a ground pin extending through the capacitor in relation with the second set of electrode plates, and at least partially extending through a second passageway of the insulator in conductive relation with the ground plates. In this manner, the exterior electrical/mechanical connection between the capacitor and ground plane or other ground member is eliminated.

Abstract: In an embodiment, an electrolytic polymer capacitor includes a metal first electrode and a polymer-containing second electrode.

Abstract: An electromagnetic interference (EMI) filter or frequency filters (e.g. bandpass or band reject filters) in which a capacitor has an inductance cancellation loop. Inductive coupling between capacitors can allow undesired high frequencies to propagate across a filter. This is particularly a concern when the capacitors are oriented in parallel. In the present invention, the inductance cancellation loop is disposed adjacent to one capacitor so that mutual inductance between the capacitors is reduced. The attenuation of the filter at high frequencies is thereby increased. The loop can increase voltage attenuation of an EMI filter by about 20 dB. In another aspect, inductors in the filter are oriented horizontally relative to a circuitboard. Horizontal orientation reduces leakage inductance coupling between the inductors and circuitboard traces, and between the inductor and capacitors, thereby preventing unwanted propagation of high frequencies.

Abstract: An on-chip bypass capacitor and method of manufacturing the same, the on-chip bypass capacitor including at least two capacitor arrays, each capacitor array including a first layer connecting the at least two capacitor arrays in series, each capacitor array including a plurality of capacitors, each of the plurality of capacitors including a second layer connecting the plurality of capacitors in parallel. The on-chip bypass capacitor may be part of a chip which also includes a memory cell array including at least one cell capacitor.

Abstract: A circuit substrate comprises a first substrate on a first surface of which circuit elements are loaded, a second substrate on which the first substrate is loaded, and noise reduction elements. Each of the noise reduction elements is sandwiched between an area of a second surface of the first substrate over against the first surface of the first substrate and a surface of the second substrate facing the second surface of the first substrate. The noise reduction element is connected between a power source terminal of the second surface of the first substrate and a power source terminal of the surface of the second substrate, and/or between a ground terminal of the second surface of the first substrate and a ground terminal of the surface of the second substrate.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first to fourth inner electrodes are alternately arranged, and first to fourth terminal electrodes formed on side faces of the multilayer body. The multilayer capacitor has a first capacitor portion including first and second inner electrodes, and a second capacitor portion including third and fourth inner electrodes and exhibiting a capacitance different from that of the first capacitor portion. The first inner electrodes are electrically connected to respective ones of the plurality of first terminal electrodes through lead conductors, whereas the second inner electrodes are electrically connected to respective ones of the plurality of second terminal electrodes through lead conductors. The third and fourth inner electrodes are electrically connected to the third and fourth terminal electrodes through lead conductors, respectively.

Abstract: A capacitor cell for reducing noise in a high drive cell includes a plurality of vias for supplying power to an interconnection layer positioned over the capacitor cell from an upper interconnection layer, so that the resistance of the power supply path is reduced.

Abstract: A decoupling module for decoupling high-frequency signals from A power supply line, the module including a layer (30) of dielectric material which is arranged between a first and a second metallic layer (20, 22), where the first metallic layer (20) is connected as a ground electrode of the decoupling module and the second metallic layer (22) includes at least two surfaces of different size which are consecutively electrically connected between an input connection point and an output connection point, while two respective consecutive surfaces are connected to each other by only one conducting section.

Abstract: A linear capacitor design providing shielding on all sides of the linear capacitor. In one aspect the capacitor provides a signal side metal layer substantially enclosed by a dielectric material which is, in turn, substantially enclosed by an upper and lower metal shield layer. in another aspect, the upper and lower shield metal layers may be coupled by a plurality of vias. In another aspect, a plurality of alternating intermediate layers provide signal side metal and shield metal separated by dielectric material such that each signal side layer is substantially enclosed by one or more shield metal layers. In another aspect, multiple intermediate signal side metal layers are conductively coupled to one another by a plurality of vias and multiple shield metal layers are conductively coupled to one another by a plurality of vias.

Abstract: There are provides the steps of forming sequentially a first conductive film, a dielectric film, and a second conductive film on an insulating film, forming a first film on the second conductive film, forming a second film made of insulating material on the first film, forming hard masks by patterning the second film and the first film into a capacitor planar shape, etching the second conductive film and the dielectric film in a region not covered with the hard masks, etching the first conductive film in the region not covered with the hard masks up to a depth that does not expose the insulating film, removing the second film constituting the hard masks by etching, etching a remaining portion of the first conductive film in the region not covered with the hard masks to the end, and removing the first film.

Abstract: A feedthrough terminal assembly for an active implantable medical device utilizes an insert to establish a reliable electrical connection between capacitor electrode plates, via inner surface metallization of a capacitor aperture, and an associated terminal pin 10, which passes at least partially therethrough. The inserts are preferably resiliently flexible, such as a spring, to establish this connection. The insert also serves to establish a mechanical connection between the capacitor and the terminal pin.

Abstract: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.

Abstract: A semiconductor device is disclosed which has a plurality of unit capacitive elements. At least one lead-out electrode of bottom electrodes of the unit capacitive elements of the capacitive element group is disposed along a circumference going around top electrodes as a whole of the capacitive element group, and a given capacitive element is connectable to the capacitive element group, the given capacitive element having a capacitance value that is set to eliminate effects of parasitic capacitance of at least the capacitive element group. Furthermore, the given capacitive element may consist of a capacitive element group.

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract: A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.

Abstract: An electrical component includes a ceramic base body having at least four contact surfaces. Two of the contact surfaces are on opposite sides of the ceramic base body. First protective layers are arranged on regions of the opposite sides of the ceramic base body that do not include the contact surfaces. The first protective layers have a composition that allows the first protective layers to be sintered at a higher temperature than the contact surfaces. Second protective layers are arranged on at least two opposite surfaces of the ceramic base body. The ceramic base body, the first protective layers, and the second protective layers are sintered together.

Abstract: An EMI filter capacitor assembly utilizes biocompatible and non-migratable materials to adapt electronic components for direct body fluid exposure. The assembly includes a capacitor having first and second sets of electrode plates which are constructed of non-migratable biocompatible material. A conductive hermetic terminal of non-migratable and biocompatible material adjacent to the capacitor is conductively coupled to the second set of electrode plates. One or more conductive terminal pins having at least an outer surface of non-migratable and biocompatible material are conductively coupled to the first set of electrode plates, while extending through the hermetic terminal in non-conductive relation. The terminal pins may be in direct contact with the first set of electrode plates, or in contact with a termination surface of conductive connection material. The termination surface is also constructed of non-migratable and biocompatible materials.

Abstract: In accordance with the invention there is provided a semiconductor capacitor having a first semiconductor layer which forms a first capacitor electrode and which includes silicon, a second capacitor electrode and a capacitor dielectric including praseodymium oxide between the capacitor electrodes, in which provided between the capacitor dielectric including praseodymium oxide and at least the first semiconductor layer including silicon is a first thin intermediate layer representing a diffusion barrier for oxygen. In particular the thin intermediate layer can include oxynitride.

Abstract: The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

Abstract: A base structure is formed from a green material having first and second opposing sides and having a plurality of via openings therein. The green material is then sintered so that the green material becomes a sintered ceramic material and the base structure becomes a sintered ceramic base structure having the via openings. A conductive via is formed in each via opening of the sintered ceramic base structure. First and second capacitor structures are formed on the sintered ceramic base structure, each on a respective side of the sintered ceramic base structure. The power and ground planes of the capacitor structure are connected to the vias. As such, a capacitor structure can be formed and connected to the vias without the need to drill via openings in brittle substrates such as silicon substrates. Capacitor structures on opposing sides provide more capacitance without manufacturing complexities associated with the manufacture of one capacitor structure having a large number of power and ground planes.

Abstract: A semiconductor device, in which four pieces of strip-shaped electrodes, whose longitudinal directions are the same, are formed in each layer of a plurality of wiring layers that are provided by a same design rule with each other, simultaneously with regular wirings. In each wiring layer, two pieces each of first electrode and second electrode are formed parallelly with each other, alternately, and remote from each other. Then, the first electrodes formed in each layer are connected to each other by a first via, the second electrodes formed in each layer are connected to each other by a second via, a first structure body formed by connecting the first electrodes and the first via to each other is connected to a ground wiring, and a second structure body formed by connecting the second electrodes and the second via to each other is connected to a power source wiring.

Abstract: A capacitor structure is fabricated by forming a pattern of first dielectrics over a foil, forming first electrodes over the first dielectrics, and co-firing the first dielectrics and the first electrodes. Co-firing of the dielectrics and the electrodes alleviates cracking caused by differences in thermal coefficient of expansion (TCE) between the electrodes and the dielectrics. Co-firing also ensures a strong bond between the dielectrics and the electrodes. In addition, co-firing allows multi-layer capacitor structures to be constructed, and allows the capacitor electrodes to be formed from copper.

Abstract: A stacked capacitor includes a dielectric member, a plurality of internal electrodes, and a plurality of extraction electrodes. The dielectric member is a stacked member formed of stacked dielectric layers and having at least one side surface. The internal electrodes are stacked alternately with the dielectric layers and have first edges positioned near the side surface. Each of the extraction electrodes leads from each first edge to the side surface. Each of the extraction electrodes has a width W on the side surface in a direction orthogonal to the stacking direction and is separated from adjacent extraction electrodes by a distance G on the side surface in the direction orthogonal to the stacking direction. The width W and distance G are set such that 1.2?W/G?4.0.

Abstract: A sheet capacitor of the invention has a contact portion formed in a through-hole requiring electrical connection with an IC connection pin among the through-holes in which the IC connection pins are inserted, and a capacitor element connected to the contact portion. Another sheet capacitor of the invention includes an insulating board and a capacitor element mounted on the insulating board. The insulating board has a connection land with an IC at the upper side, and a connection land with a printed wiring board at the lower side. The capacitor element and connection lands at the upper and lower side of the insulating board are connected with each other electrically. In any one of these configurations, a capacitor element of large capacity and low ESL is connected closely to the IC, and the mounting area of the peripheral circuits of the IC can be increased.

Abstract: A capacitor-embedded substrate for reliably compensating for fluctuation of a power source voltage is provided. A decoupling capacitor is formed between an input side electrode layer and an output side electrode layer via interlayer insulating layers, the decoupling capacitor includes a ground layer, a power source layer, and a dielectric layer interposed therebetween. A plurality of power supply terminals used for power supply to a semiconductor device is formed by patterning the output side electrode layer and is connected to the power source layer via a capacitor via.

Abstract: A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.

Abstract: A feedthrough filter capacitor assembly includes a conductive terminal pin which extends through a first passageway of a capacitor in conductive relation with a first set of electrode plates, and through a conductive ferrule and an insulator in non-conductive relation. The insulator includes ground plates conductively coupled to the ferrule. A second set of electrode plates of the capacitor are conductively coupled to the insulator ground plates, such as by a ground pin extending through the capacitor in relation with the second set of electrode plates, and at least partially extending through a second passageway of the insulator in conductive relation with the ground plates. In this manner, the exterior electrical/mechanical connection between the capacitor and ferrule or other ground member is eliminated.

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract: A capacitor structure includes a first electrode provided on an insulating basic member, a dielectric member provided on the electrode, a second electrode provided on the dielectric member, and a plurality of electrode terminals aligned in a grid on the electrode. Respective electrode terminals are aligned such that opposite polarities (+,?) are alternately allocated to neighboring electrode terminals, and respective divided partial electrodes of the first and second electrodes are also aligned such that opposite polarities (+,?) are alternately allocated to neighboring electrode terminals. According to this structure, the inductance of the capacitor structure is reduced and thus the decoupling effect can be effectively achieved. This contributes to a stable operation in the high-frequency (GHz band) range.

Abstract: An EMI filter capacitor assembly utilizes biocompatible and non-migratable materials to adapt electronic components for direct body fluid exposure. The assembly includes a capacitor having first and second sets of electrode plates which are constructed of non-migratable biocompatible material. A conductive hermetic terminal of non-migratable and biocompatible material adjacent to the capacitor is conductively coupled to the second set of electrode plates. One or more conductive terminal pins having at least an outer surface of non-migratable and biocompatible material are conductively coupled to the first set of electrode plates, while extending through the hermetic terminal in non-conductive relation. The terminal pins may be in direct contact with the first set of electrode plates, or in contact with a termination surface of conductive connection material. The termination surface is also constructed of non-migratable and biocompatible materials.

Abstract: A capacitor includes a capacitor main body having a front surface on which a semiconductor device is to be mounted and a rear surface at which the capacitor main body is to be mounted on a first main surface of a circuit substrate, a plurality of internal electrodes disposed within the capacitor main body, and a plurality of via conductors penetrating the capacitor main body between the front surface and the rear surface and electrically connected to the internal electrodes, wherein the capacitor main body has a first dielectric layer located on a side of the capacitor main body closer to the front surface and a second dielectric layer located on a side of the first dielectric layer closer to the rear surface, the second dielectric layer having a higher thermal expansion coefficient and a higher dielectric constant than the first dielectric layer.

Abstract: A monolithic capacitor array (18) is disclosed which may be suitable for incorporation into a multi-way electrical connector and comprises a dielectric body (20)with a set of through-going cavities (22) for receiving respective connector pins. The cavities are associated with respective capacitors (30, 32) each formed by a first and a second set of capacitor plates (38, 40, 44, 46) interleaved within the dielectric body. The first set of capacitor plates is connectable to ground through a contact (42) at the body's exterior. The second set of capacitor plates is interconnected by metallization of the interior of a connection cavity (62) formed in the dielectric body, the connection-cavity being separately formed form its associated pin-receiving cavity and the metallization therein being contactable from the body's exterior to enable connection of a pin received in the pin-receiving cavity to the second capacitor plates of the associated capacitor.

Abstract: A system for delivering power to an integrated circuit includes a decoupling capacitance located in a connector that is formed as a socket, or frame for the IC. The power delivery system takes the form of a power reservoir that is integrated into a connector, thereby eliminating the need for complex and expensive power traces to be formed in or discrete capacitors mounted on a circuit board to which the IC is connected. The system includes a connector that takes the form of a cover member that fits over the IC and which contains a recess that accommodates a portion of the IC therein. The cover member includes at least a pair of spaced-apart capacitor plates that are disposed therewithin. Electricity is supplied to the plates so that they will become charged as a capacitor and the plates are formed with a plurality of terminals that extend into contact with the IC so that the plates may selectively discharge to the IC and thereby provide it with operating and surge currents.

Abstract: The invention provides a semiconductor device and a method for manufacturing the same that are capable of contributing to a further chip downsizing in the cross-point FeRAM. More particularly, a first local wiring can be formed on a first interlayer insulating layer so as to connect a drain region and part of a gate electrode in a MOS transistor and a top layer wiring. A second local wiring can be formed on a second interlayer insulating layer so as to connect a source region in the MOS transistor and a lower electrode layer in a ferroelectric capacitor, and further to connect part of a gate electrode in the MOS transistor and the top layer wiring. The MOS transistor that makes up of a peripheral circuitry using only the first and second local wiring can be formed directly under a capacitor array forming region of cross-point FeRAM.

Abstract: A capacitor has electrodes at surfaces thereof, with one of the electrodes secured onto one surface of a grounding metal. Through conductors pass through the capacitor and the grounding metal and are connected to the other electrodes so as to achieve electrical continuity. An insulating case is provided at one surface of the grounding metal, with one end of the insulating case fitted around the external circumference of the raised portion of the grounding metal. Insulating resin fills a space inside the insulating case, the internal space of the grounding metal and a space around the capacitor. The insulating resin comprises an epoxy resin containing a brominated fire retardant, and the brominated fire retardant is a brominated aromatic glycidyl ether.

Abstract: A semiconductor device includes a semiconductor bare chip and an electrically-insulative board member with a thin-film structure capacitor. The semiconductor bare chip has a power supply terminal and a grounding terminal on the back surface thereof. The semiconductor bare chip is mounted on a circuit board by flip-chip bonding. The board member includes a board and a thin-film structure capacitor provided on the board. The capacitor has terminals corresponding to the power supply terminal and the grounding terminal of the semiconductor bare chip thereon. The side of the board member where the capacitor is provided is bonded to the back surface of the semiconductor bare chip. The terminals of the capacitor are electrically connected to the power supply terminal and the grounding terminal of the semiconductor bare chip.

Abstract: Systems for power delivery to an integrated circuit include a decoupling capacitance located in a connector that is formed as a socket, or frame for the IC. The power delivery system delivers power to the IC along various surfaces thereof by way of a plurality of discrete capacitors that are supported by a socket-style connector. The socket-style connector has an insulative body portion that is mounted to a circuit board and has a recess defined thereon that receives the IC therein. A plurality of capacitors are integrated with the body portion and, each of the capacitors supplies a desired amount of power to the IC. The capacitors are charged by way of leads on the circuit board that bring power to current to the capacitors and then are discharged as the IC draws power from the socket such that the capacitors form a power reservoir integrated with the socket, thereby eliminating the need for mounting such capacitors on the circuit board near the IC and freeing up space on the circuit board.

Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.