Layered Patents (Class 361/313)
  • Patent number: 8432662
    Abstract: In a ceramic capacitor according to the present invention, the electrode strips of an internal electrode and the dielectric strips of a ceramic dielectric member are arranged perpendicularly to the surface of a substrate, and as such, the plurality of electrode strips and the plurality of dielectric strips are arranged alternately along a parallel direction relative to the substrate surface. That is, the electrode strips and the dielectric strips are multi-layered along a parallel direction relative to the substrate surface, thereby facilitating the realization of multi-layering in the ceramic capacitor by a known patterning technology.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: April 30, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Atsushi Iijima, Hiroshi Ikejima
  • Patent number: 8424177
    Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 23, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Patent number: 8411409
    Abstract: When an external terminal electrode of a ceramic electronic component such as a laminated ceramic capacitor is formed by plating, plating growth may be also caused even in an undesired location. The ceramic surface provided by a component main body is configured to include a high plating growth region of, for example, a barium titanate based ceramic, which exhibits relatively high plating growth, and a low plating growth region of, for example, a calcium zirconate based ceramic, which exhibits relatively low plating growth. The plating film constituting a first layer to define a base for an external terminal electrode is formed in such a way that the growth of a plated deposit deposited with conductive surfaces provided by exposed ends of internal electrodes as starting points is limited so as not to cross over a boundary between the high plating growth region and the low plating growth region toward the low plating growth region.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: April 2, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makoto Ogawa, Akihiro Motoki, Masahito Saruban, Toshiyuki Iwanaga, Syunsuke Takeuchi, Kiyoyasu Sakurada
  • Patent number: 8405953
    Abstract: A capacitor-embedded substrate includes a base material having a desired thickness, and a pair of conductors (feedthrough electrodes) each formed in a desired pattern to penetrate through the base material in the thickness direction thereof, and oppositely disposed with an insulating layer interposed therebetween. The pair of electrodes are formed in comb-shaped patterns, and are oppositely disposed in such a manner that respective comb-tooth portions are meshed with each other.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: March 26, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tomoharu Fujii, Masahiro Sunohara
  • Patent number: 8400781
    Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: March 19, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventor: Peter B. Gillingham
  • Publication number: 20130063863
    Abstract: A method and apparatus for a capacitor comprises a first plate and a second plate. An insulator between the first plate and the second plate includes a first dielectric layer and a second dielectric layer. At least one interface between the first dielectric layer and the second dielectric layer includes one or more additives.
    Type: Application
    Filed: July 9, 2012
    Publication date: March 14, 2013
    Inventors: John P. Timler, David A. Baldwin
  • Patent number: 8390985
    Abstract: A highly moisture resistant dielectric ceramic is prepared by providing a compact containing a dielectric ceramic component powder and a second powder including a compound containing an alkali metal element, and firing the compact and a second composition containing an alkali metal element at the same time. A laminated ceramic capacitor using the dielectric ceramic is described.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: March 5, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Naito, Seiichi Jono, Tomotaka Hirata
  • Patent number: 8390984
    Abstract: The disclosed is a capacitor substrate structure to reduce the high leakage current and low insulation resistance issue of organic/inorganic hybrid materials with ultra-high dielectric constant. The insulation layer, disposed between two conductive layers, includes multi-layered dielectric layers. At least one of the dielectric layers has high dielectric constant, including high dielectric constant ceramic powder and conductive powder evenly dispersed in organic resin. The other dielectric layers can be organic resin, or further include high dielectric constant ceramic powder dispersed in the organic resin. The substrate has an insulation resistance of about 50K? and leakage current of below 100 ?Amp under operational voltage.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: March 5, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Shur-Fen Liu, Meng-Huei Chen, Bih-Yih Chen, Yun-Tien Chen
  • Publication number: 20130050895
    Abstract: Provided is a multilayer capacitor that can be manufactured with a high yield, and wherein the warp thereof can be limited. The multilayer capacitor, manufacturing method thereof, circuit board, and electronic device are characterized by having resin layers and metal layers laminated alternately a plurality of times in the thickness direction, having the front and back faces thereof covered with surface layers containing resin material, having either the front face or the back face comprised of a first face (30) that is a gently sloping face without any recess section, having the other face comprised of a second face (32) with recess sections (34), and characterized by having two or more laminated bodies (20A, 20B), with warps, pasted together, and by further having at least two adjacent laminated bodies (20A, 20B) pasted together with either the first faces (30) thereof, or with the second faces (32) thereof.
    Type: Application
    Filed: October 13, 2010
    Publication date: February 28, 2013
    Applicant: RUBYCON CORPORATION
    Inventors: Takenori Tezuka, Chiharu Ito, Tomonao Kako
  • Patent number: 8385047
    Abstract: A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: February 26, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Huikai Xie, Khai D. T. Ngo
  • Patent number: 8375539
    Abstract: A method of manufacturing a low capacitance density, high voltage MIM capacitor and the high density MIM capacitor. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: James Stuart Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8373968
    Abstract: Dielectric ceramic composition includes a hexagonal type barium titanate as a main component shown by a generic formula (Ba1-?M?)A(Ti1-?Mn?)BO3 and having hexagonal structure wherein an effective ionic radius of 12-coordinated “M” is ?20% or more to +20% or less with respect to an effective ionic radius of 12-coordinated Ba2+ and the A, B, ? and ? satisfy relations of 0.900?(A/B)?1.040, 0.003???0.05, 0.03???0.2, and as subcomponents, with respect to the main component, certain contents of alkaline earth oxide such as MgO and the like, Mn3O4 and/or Cr2O3, CuO, Al2O3, rare earth element oxide and glass component including SiO2. According to the present invention, it can be provided the hexagonal type barium titanate powder and dielectric ceramic composition which are preferable for producing electronic components such as a capacitor and the like showing high specific permittivity, having advantageous insulation property and sufficient reliability.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: February 12, 2013
    Assignees: TDK Corporation, Japan Aerospace Exploration Agency
    Inventors: Tatsuya Ishii, Hidesada Natsui, Takeo Tsukada, Shinichi Yoda, Kentei Yono
  • Patent number: 8373966
    Abstract: A structural body which includes a first dielectric layer formed on a first substrate and including first conductive particles, each surface of the first conductive particles being entirely covered with a first dielectric film; and a second dielectric layer formed on the first dielectric layer wherein a volume ratio of a dielectric in the second dielectric layer is higher than a volume ratio of a dielectric in the first dielectric layer.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: February 12, 2013
    Assignee: Fujitsu Limited
    Inventor: Yoshihiko Imanaka
  • Patent number: 8363383
    Abstract: A dielectric ceramic composition includes BaTiO3 as a main component; as subcomponents, with respect to 100 moles of BaTiO3, 0.9 to 2.0 moles of an oxide of RA in terms of RA2O3, where RA is at least one selected from Dy, Gd and Tb; 0.3 to 2.0 moles of an oxide of RB in terms of RB2O3, where RB is at least one selected from Ho and Y; 0.75 to 2.5 moles of an oxide of Yb in terms of Yb2O3; and 0.5 to 2.0 moles of an oxide of Mg in terms of Mg. when contents of oxide of RA, oxide of RB and oxide of Yb with respect to 100 moles of BaTiO3 are defined as “?”, “?” and “?”, respectively, “?”, “?” and “?” satisfy relations of 0.66?(?/?)?3.0 and 0.85?(?+?)/??2.4. According to the present invention, a dielectric ceramic composition having good properties can be provided.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: January 29, 2013
    Assignee: TDK Corporation
    Inventors: Jun Sato, Takashi Kojima, Tomoya Shibasaki, Osamu Kido
  • Patent number: 8351181
    Abstract: There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 ?m or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 ?m or less.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: January 8, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ghyu Ahn, Byoung Hwa Lee, Min Cheol Park, Young Hoon Song, Mi Hee Lee
  • Patent number: 8351180
    Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: January 8, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ghyu Ahn, Byoung Hwa Lee, Min Cheol Park, Sang Soo Park, Dong Seok Park
  • Patent number: 8339766
    Abstract: A method of manufacturing a thin film capacitor, having: a base electrode; dielectric layers consecutively deposited on the base electrode; an internal electrode deposited between the dielectric layers; an upper electrode deposited opposite the base electrode with the dielectric layers and the internal electrode being interposed therebetween; and a cover layer deposited on the upper electrode, has depositing an upper electrode layer which is to be the upper electrode, and a cover film which is to be the cover layer on the unsintered dielectric film which is to be the dielectric layer, to fabricate a lamination component, and sintering the lamination component.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 25, 2012
    Assignee: TDK Corporation
    Inventors: Yoshihiko Yano, Yasunobu Oikawa
  • Publication number: 20120320494
    Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.
    Type: Application
    Filed: August 29, 2012
    Publication date: December 20, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
  • Patent number: 8335073
    Abstract: A dielectric ceramic composition includes, as a main component, a compound having perovskite type crystal structure shown by a general formula ABO3, as subcomponents, in terms of respective element with respect to 100 moles of the compound, and 0.6 to 2.0 moles of an oxide of Mg, 0.010 to 0.6 mole of oxide of Mn and/or Cr, 0.010 to 0.2 mole of an oxide of at least one selected from V, Mo and W, 0.10 to 1.0 mole of an oxide of R1 (R1 is at least one selected from Y, Yb, Er and Ho), 0.10 to 1.0 mole of an oxide of R2 (R2 is at least one selected from Dy, Gd and Tb) and 0.2 to 1.5 moles of a component consisting of an oxide of Ba and/or oxide of Ca and an oxide of Si. According to the present invention, even when a dielectric layer is made thinner, a dielectric ceramic composition having good characteristics can be provided.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: December 18, 2012
    Assignee: TDK Corporation
    Inventors: Kazuhiro Komatsu, Yoichiro Hoshi, Shuhei Yoshikawa, Yuichiro Sueda
  • Patent number: 8331079
    Abstract: A multilayer ceramic capacitor and a method of manufacturing the same are provided. The multilayer ceramic capacitor includes a capacitive part, a passivation layer, and first and second outer electrodes. In the capacitive part, a plurality of dielectric layers and a plurality of first and second inner electrodes are alternately laminated, and ends of the first and second inner electrodes are alternately and respectively exposed in a direction of lamination of the dielectric layers. The passivation layer is provided at either or both of the top and bottom surfaces of the capacitive part. The first and second outer electrodes are electrically connected to the first and second inner electrodes exposed in a direction of lamination of the dielectric layers. One or more inner electrodes disposed at both ends in a direction of lamination among the plurality of inner electrodes include oxide represented by Ni—Mg—O.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: December 11, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kang Heon Hur, Doo Young Kim, Mun Su Ha, Chul Seung Lee
  • Patent number: 8331076
    Abstract: A clad capacitor and method of manufacture includes assembling a preform comprising a ductile, electrically conductive fiber; a ductile, electrically insulating cladding positioned on the fiber; and a ductile, electrically conductive sleeve positioned over the cladding. One or more preforms are then bundled, heated and drawn along a longitudinal axis to decrease the diameter of the ductile components of the preform and fuse the preform into a unitized strand.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: December 11, 2012
    Assignee: UT-Battelle, LLC
    Inventor: Enis Tuncer
  • Patent number: 8315032
    Abstract: A ductile preform for making a drawn capacitor includes a plurality of electrically insulating, ductile insulator plates and a plurality of electrically conductive, ductile capacitor plates. Each insulator plate is stacked vertically on a respective capacitor plate and each capacitor plate is stacked on a corresponding insulator plate in alignment with only one edge so that other edges are not in alignment and so that each insulator plate extends beyond the other edges. One or more electrically insulating, ductile spacers are disposed in horizontal alignment with each capacitor plate along the other edges and the pattern is repeated so that alternating capacitor plates are stacked on alternating opposite edges of the insulator plates. A final insulator plate is positioned at an extremity of the preform. The preform may then be drawn to fuse the components and decrease the dimensions of the preform that are perpendicular to the direction of the draw.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 20, 2012
    Assignee: UT-Battelle, LLC
    Inventor: Enis Tuncer
  • Patent number: 8310813
    Abstract: An electrolytic capacitor sealer is formed of a modified butyl rubber composition obtained by using an organic peroxide to crosslink a modified butyl rubber composition which has been modified by reacting butyl rubber with a compound (a) having in the molecule a nitroxide free radical that is stable at room temperature even in the presence of oxygen, a radical initiator (b), and a bifunctional or higher radical polymerizable monomer (c), and of a modified butyl rubber composition obtained by compounding a radical polymerizable monomer (c) with a modified butyl rubber composition that has been obtained by reacting butyl rubber with a compound (a) having in the molecule a nitroxide free radical that is stable at room temperature even in the presence of oxygen and a radical initiator (b), and then crosslinking the composition thus obtained with an organic peroxide.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: November 13, 2012
    Assignees: Nippon Chemi-Con Corporation, The Yokohama Rubber Co., Ltd.
    Inventors: Hiroaki Fujita, Kazuhiko Kimura, Masatoshi Iemura, Masashi Ozawa, Makoto Ashiura, Tetsuji Kawazura
  • Patent number: 8310807
    Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: November 13, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
  • Patent number: 8305730
    Abstract: A method for manufacturing a capacitor includes the steps of: sequentially laminating, on a substrate, a lower electrode layer, a dielectric layer and an upper electrode layer; forming a patterned mask layer on the upper electrode layer; patterning at least the upper electrode layer and the ferroelectric layer using the mask layer as a mask; removing the mask layer; and conducting a plasma treatment to contact plasma with an exposed surface of the dielectric layer.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 6, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Masao Nakayama
  • Patent number: 8295029
    Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes MxN capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 23, 2012
    Assignee: Altera Corporation
    Inventors: Shuxian Chen, Jeffrey T. Watt
  • Patent number: 8295028
    Abstract: Capacitive coupling devices and methods of fabricating a capacitive coupling device are disclosed. The coupling device could include a stack of layers forming electrodes and at least one insulator. The insulator could include a region of doped silicon. The silicon could be doped with a species selected from Ce, Cr, Co, Cu, Dy, Er, Eu, Ho, Ir, Li, Lu, Mn, Pr, Rb, Sm, Sr, Tb, Tm, Yb, Y, Ac, Am, Ba, Be, Cd, Gd, Fe, La, Pb, Ni, Ra, Sc, Th, Hf, Tl, Sn, Np, Rh, U, Zn, Ag, and Yb in relief and forming roughnesses relative to the neighboring regions of the same level in the stack. The electrodes and the insulator form conformal layers above the doped silicon region.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: October 23, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Benoit Froment
  • Patent number: 8279578
    Abstract: [Problem to be Solved] To provide a helical capacitor for controlling a high-frequency power which flows in power lines, and a manufacturing method of the helical capacitor. [Solution] A helical capacitor is constituted by helically spiraling a belt shape capacitor line 1001 which includes an internal metal body to be a helically spiraled belt-shape internal electrical conductor, a dielectric film covering the internal electrical conductor, and an electrically conductive layer covering the dielectric film. The capacitor line of belt shape 1001 can be wrapped around the internal support body 1200. Internal metal body lead terminals 1311, 1321 are respectively formed at both ends of the internal metal body, and electrically conductive layer lead terminals 1312, 1322 can be respectively formed at both ends of the electrically conductive layer.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: October 2, 2012
    Assignee: NEC Corporation
    Inventor: Koichiro Masuda
  • Patent number: 8274779
    Abstract: Provided are an embedded capacitor, an embedded capacitor sheet using the embedded capacitor, and a method of manufacturing the same that may increase a surface area to thereby increase a capacity for each unit area and may provide an embedded capacitor in a sheet to thereby readily lay the embedded capacitor on an embedded printed circuit board. The embedded capacitor may include: a common electrode member 11 including a plurality of grooves 11a; a sealing dielectric layer 12 being formed by sealing a nano dielectric powder with a high dielectric constant in the plurality of grooves 11a formed in the common electrode member 11; a buffer dielectric layer 13 sealing and smoothing an uneven portion of the sealing dielectric layer 12 by applying a paste or a slurry including epoxy of 20 Vol % through 80 Vol % and dielectric powder of 20 Vol % through 80 Vol % with respect to the sealing dielectric layer 12; and an individual electrode member 14 being formed on the buffer dielectric layer 13.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: September 25, 2012
    Assignee: Samhwa Capacitor Co., Ltd.
    Inventors: Jung Rag Yoon, Kyung Min Lee, Jeong Woo Han
  • Patent number: 8270144
    Abstract: The present invention relates to borosilicate glass compositions for a sintering agent, dielectric compositions containing the borosilicate glass compositions and a multilayer ceramic capacitor using the dielectric compositions. Borosilicate glass compositions for a sintering agent according to an aspect of the invention include an alkali oxide, an alkaline earth oxide and a rare earth oxide, can sinter ceramic dielectrics at low temperatures and improve the hot insulation resistance of a multilayer ceramic capacitor. Correspondingly, dielectric compositions including these borosilicate glass compositions and a multilayer ceramic capacitor using the dielectric compositions can be sintered at a low temperature of 1100° C. or less and have high hot insulation resistance, thereby ensuring high levels of reliability.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: September 18, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung Bum Sohn, Young Tae Kim, Kang Heon Hur, Min Hee Hong, Hew Young Kim, Doo Young Kim
  • Patent number: 8264815
    Abstract: A multilayer ceramic capacitor includes: a ceramic element; a plurality of first and second inner electrodes formed at the interior of the ceramic element and including capacity contribution portions facing each other and capacity non-contribution portions extending from the capacity contribution portions and having one end alternately exposed from the side of the ceramic element; first and second outer electrodes formed at the side of the ceramic main body and electrically connected with the first and second inner electrodes, wherein the thickness of the capacity non-contribution portion is greater than that of the capacity contribution portion and connectivity of the capacity non-contribution portion is higher than that of the capacity contribution portion at one or more of the first and second inner electrodes.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: September 11, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyea Sun Yun, Gee Lyong Kim, Doo Young Kim, Gi Woo Lee, Dong Ik Chang
  • Patent number: 8264817
    Abstract: A laminated ceramic capacitor which has a dielectric ceramic with a high dielectric constant and has excellent reliability against changes in temperature and mechanical shocks, even when dielectric ceramic layers are reduced in thickness employs a dielectric ceramic containing (Ba1-xCax)yTiO3 (where 0.045?x?0.15 and 0.98?y?1.05) as its main constituent and containing Re2O3 (where Re is at least one of Gd, Dy, Ho, Yb, and Y), MgO, MnO, V2O5, and SiO2 as accessory constituents, which is represented by the general formula: 100(Ba1-xCax)yTiO3+aRe2O3+bMgO+cMnO+dV2O5+eSiO2, and satisfies each of the following conditions: 0.65?a?1.5; 0.98?y?1.05; 0.15?b?2.0; 0.4?c?1.5; 0.02?d?0.25; and 0.2?e?3.0.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 11, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masanori Nakamura, Toshihiro Okamatsu, Akira Kato, Shinya Isota
  • Patent number: 8259432
    Abstract: Devices for storing energy at a high density are described. The devices include a solid dielectric that is preformed to present a high exposed area onto which an electrode is formed. The dielectric material has a high dielectric constant (high relative permittivity) and a high breakdown voltage, allowing a high voltage difference between paired electrodes to effect a high stored energy density.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: September 4, 2012
    Assignee: Space Charge, LLC
    Inventors: Daniel C. Sweeney, John B. Read
  • Patent number: 8259434
    Abstract: There is provided a multilayer ceramic capacitor including: a capacitor main body formed by stacking a dielectric layer having a thickness of td and alternately stacking more than one opposing pair of a first internal electrode having a thickness of te and a second internal electrode having the same thickness as the first internal electrode, and having the dielectric layer therebetween; and a protective layer formed by stacking a second dielectric layer on at least one of an upper surface and a lower surface of the capacitor main body so that a dielectric material layer has a thickness of tc, wherein when a thickness from an end of a region where the first internal electrode and the second internal electrode oppose each other to side and end surfaces of the capacitor main body is a, it satisfies the following Equation 1 and a method of fabricating a multilayer ceramic capacitor are provided.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: September 4, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyo Jung Kim, Ji Hun Jeong, Dong Ik Chang, Doo Young Kim
  • Patent number: 8254083
    Abstract: There are provided a ceramic electronic component and a method for producing the ceramic electronic component, where a ground electrode layer can be directly coated with lead-free solder without lowering reliabilities. Terminal electrode 3 is provided with a ground electrode layer 21 of Cu having been formed by firing, a solder layer 22 formed of a lead-free solder based on five elements of Sn—Ag—Cu—Ni—Ge, and a diffusion layer 23 having been formed by the diffusion of Ni between the ground electrode layer 21 and the solder layer 22. Because the diffusion layer 23 of Ni is formed between the ground electrode layer 21 and the solder layer 22, the diffusion layer 23, which functions as a barrier layer, suppresses the solder leach of Cu from the ground electrode layer 21. The diffusion layer 23 of Ni can also suppress the growth of fragile intermetallic compounds of Sn—Cu. Therefore, a decrease in the bonding strength between the ground electrode layer 21 and the solder layer 22 can be prevented.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: August 28, 2012
    Assignee: TDK Corporation
    Inventors: Takashi Sakurai, Shinya Yoshihara, Ko Onodera, Hisayuki Abe, Masahiko Konno, Satoshi Kurimoto, Hiroshi Shindo, Akihiro Horita, Genichi Watanabe, Yoshikazu Ito
  • Patent number: 8247700
    Abstract: A wired circuit board has a metal supporting board, an insulating layer formed on the metal supporting board, a conductive pattern formed on the insulating layer and having a pair of wires arranged in spaced-apart relation, and a semiconductive layer formed on the insulating layer and electrically connected to the metal supporting board and the conductive pattern. The conductive pattern has a first region in which a distance between the pair of wires is small and a second region in which the distance between the pair of wires is larger than that in the first region. The semiconductive layer is provided in the second region.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: August 21, 2012
    Assignee: Nitto Denko Corporation
    Inventors: Jun Ishii, Yasunari Ooyabu, Visit Thaveeprungsriporn
  • Patent number: 8248752
    Abstract: A multilayer ceramic capacitor is provided. In the multilayer ceramic capacitor, a plurality of first and second inner electrodes are formed inside a ceramic sintered body. Ends of the first and second inner electrodes are alternately exposed to both ends of the ceramic sintered body. First and second outer electrodes are formed on both ends of the ceramic sintered body and connected to the first and second inner electrodes. The first and second outer electrodes include a first region having a porosity in the range of 1% to 10%, and a second region having a porosity less than that of the first region.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: August 21, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kang Heon Hur, Sang Hoon Kwon, Doo Young Kim, Eun Sang Na, Byung Gyun Kim, Seok Joon Hwang, Kyoung Jin Jun, Hye Young Choi
  • Patent number: 8243419
    Abstract: A capacitor structure includes: a first electrode configured to include a plurality of openings; a second electrode formed in each center of the openings; and a dielectric layer formed to surround the second electrode and fill the openings of the first electrode.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: August 14, 2012
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Yu-Shin Ryu
  • Publication number: 20120199944
    Abstract: Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material. Capacitors, semiconductor devices and methods of forming a semiconductor device including the capacitors are also disclosed.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 9, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chun-I Hsieh, Chris Carlson
  • Patent number: 8236372
    Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hall, Chris Carlson
  • Patent number: 8229554
    Abstract: One embodiment includes an apparatus that includes an implantable device housing, a capacitor disposed in the implantable device housing, the capacitor including a dielectric comprising CaCu3Ti4O12 and BaTiO3, the dielectric insulating an anode from a cathode and pulse control electronics disposed in the implantable device housing and connected to the capacitor.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: July 24, 2012
    Assignee: Cardiac Pacemakers, Inc.
    Inventor: Gregory J. Sherwood
  • Patent number: 8223472
    Abstract: A capacitor having at least one electrode pair being separated by a dielectric component, with the dielectric component being made of a polymer such as a norbornylene-containing polymer with a dielectric constant greater than 3 and a dissipation factor less than 0.1 where the capacitor has an operating temperature greater than 100° C. and less than 170° C.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: July 17, 2012
    Assignee: Sandia Corporation
    Inventors: Shawn M. Dirk, David R. Wheeler
  • Patent number: 8218287
    Abstract: A thin-film device comprises a base electrode made of a metal, a first dielectric layer, a first inner electrode, a second dielectric layer, a second inner electrode, and a third dielectric layer. Letting T1 be the thickness of the lowermost first dielectric layer in contact with the base electrode in the plurality of dielectric layers, and Tmin be the thickness of the thinnest dielectric layer in the plurality of dielectric layers excluding the first dielectric layer, T1>Tmin. Making the first dielectric layer thicker than the thinnest, dielectric layer in the other dielectric layers can increase the distance between a metal part projecting from a metal surface because of the surface roughness of the base electrode and the inner electrode mounted on the lowermost dielectric layer, thereby reducing leakage currents.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: July 10, 2012
    Assignee: TDK Corporation
    Inventors: Akira Shibue, Yoshihiko Yano, Hitoshi Saita, Kenji Horino
  • Publication number: 20120170170
    Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 5, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Mickael Gros-Jean
  • Patent number: 8213153
    Abstract: A dielectric ceramic with stable insulation properties even after calcination under a reducing atmosphere, as is preferred for a laminated ceramic capacitor, is a CaTiO3 composition containing Sn. It is preferable for the dielectric ceramic to contain, as its main component, (Ca1-xBaxSny)TiO3 (0?x<0.2, 0.01?y<0.2) with a solution of Sn at the B site.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: July 3, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Megumi Morita, Shoichiro Suzuki, Toshikazu Takeda, Tomomi Koga
  • Patent number: 8213154
    Abstract: A nickel oxide that is co-doped with a first alkali metal dopant and a second metal dopant may be used, for example, to form a dielectric material in an electronic device. The dielectric material may be used, for example, in a capacitor. The second metal dopant of the nickel oxide may be, for example, tin, antimony, indium, tungsten, iridium, scandium, gallium, vanadium, chromium, gold, yttrium, lanthanum, ruthenium, rhodium, molybdenum or niobium.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: July 3, 2012
    Assignee: Agency for Science, Technology and Research
    Inventors: Michael B. Sullivan, Jian Wei Zheng, Ping Wu
  • Patent number: 8209829
    Abstract: A method of fabricating an electronic device includes selectively forming a glass layer on a ceramic substrate by printing, baking the glass layer, and forming a capacitor on the glass layer, the capacitor including metal electrodes and a dielectric layer interposed between the metal electrodes.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: July 3, 2012
    Assignees: Taiyo Yuden Co., Ltd., Fujitsu Limited
    Inventors: Takeo Takahashi, Xiaoyu Mi, Satoshi Ueda
  • Patent number: 8208241
    Abstract: Methods of forming an oxide are disclosed and include contacting a ruthenium-containing material with a tantalum-containing precursor and contacting the ruthenium-containing material with a vapor that includes water and optionally molecular hydrogen (H2). Articles including a first crystalline tantalum pentoxide and a second crystalline tantalum pentoxide on at least a portion of the first crystalline tantalum pentoxide, wherein the first tantalum pentoxide has a crystallographic orientation that is different than the crystallographic orientation of the second crystalline tantalum pentoxide, are also disclosed.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishwanath Bhat, Vassil Antonov
  • Patent number: 8203825
    Abstract: To provide a dielectric ceramics achieving a high insulation resistance even at a low applied voltage, and minimizing insulation resistance drop when the voltage is increased, and also provide a multilayer ceramic capacitor including the dielectric ceramics as a dielectric layer, and having excellent life characteristics in a high temperature load test. The dielectric ceramics has crystal grains composed mainly of barium titanate and containing vanadium, and a grain boundary phase existing between the crystal grains. The dielectric ceramics contains 0.0005 to 0.03 moles of vanadium in terms of V2O5, with respect to 1 mole of barium constituting the barium titanate. In the X-ray diffraction chart of the dielectric ceramics, the diffraction intensity of (004) plane indicating the tetragonal system of barium titanate is larger than the diffraction intensity of (400) plane indicating the cubic system of barium titanate.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 19, 2012
    Assignee: Kyocera Corporation
    Inventors: Yusuke Azuma, Youichi Yamazaki
  • Patent number: RE43868
    Abstract: This invention provides navel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 25, 2012
    Assignee: Nanosys, Inc.
    Inventors: Calvin Y. H. Chow, Robert Dubrow