Abstract: The present invention is directed to a microfabricated RF capacitor. The capacitor includes two signal wirebond pads configured for being connected to an electrical current source. The capacitor further includes two backbone structures which are connected to the wirebond pads and receive electrical current from the electrical current source via the wirebond pads, each backbone structure including a first backbone portion and a second backbone portion. The capacitor further includes a plurality of protrusions which are connected to the backbone portions of the backbone structures. The protrusions are spaced apart from each other and parallel to each other. Further, the protrusions are configured for distributing current received by the backbone structures and for promoting structural stability of the capacitor. The capacitor further includes a ground wall structure which may be configured for receiving ground current from a ground current source.

Abstract: A capacitor and a method of manufacturing the capacitor are disclosed. The capacitor may include a board, a polymer layer formed on one side of the board, a circuit pattern selectively formed over the polymer layer, and a titania nanosheet corresponding with the circuit pattern. Embodiments of the invention can provide flatness in the board, and allows the copper of the board to maintain its functionality as an electrode while increasing the adhesion to the titania nanosheet. The titania nanosheet may thus be implemented on a patterned board in a desired shape, number of layers, and thickness.

Abstract: A multilayer ceramic capacitor includes a capacitor body in which inner electrodes and dielectric layers are alternately laminated, and a length difference rate (D) of the inner electrodes is 7% or less. The length difference rate (D) is defined by D={L?1}/L×100, where L is a maximum length of the inner electrode, and l is a minimum length of the inner electrode.

Abstract: A ceramic material has a perovskite structure and is represented by formula of (1?x)ABO3-xYZO3. In the formula, “x” is a real number that is greater than 0 and is less than 1 each of “A,” “B,” “Y,” and “Z” is one or more kinds selected from a plurality of metal ions M other than a Pb ion and alkali metal ions, “A” is bivalent, “B” is tetravalent, “Y” is trivalent or combination of trivalent metal ions, and “Z” is bivalent and/or trivalent metal ions, or a bivalent and/or pentavalent metal ions.

Abstract: Disclosed herein is a capacitative element, including: a first electrode formed on a substrate; and a second electrode provided so as to sandwich a dielectric between the first electrode and the second electrode and so as to surround the first electrode on four sides along a surface of the substrate.

Abstract: A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer.

Abstract: There is provided a multilayer capacitor including: a capacitor body where a plurality of dielectric layers are laminated, the capacitor body including first and second surfaces opposing each other in a laminated direction, wherein the first surface provides a mounting surface; a plurality of first and second inner electrodes; an inner connecting conductor; and a plurality of first and second outer electrodes formed on an outer surface of the body, wherein a corresponding one of the outer electrodes having identical polarity to the inner connecting conductor includes at least one outer terminal formed on the first surface of the body to connect to the inner connecting conductor, and at least one outer connecting conductor formed on the second surface of the body to connect a corresponding one of the inner electrodes of identical polarity to the inner connecting conductor.

Abstract: Provided is a dielectric element comprising a dielectric thin film formed of a layer of perovskite nanosheets. The dielectric element has the advantages of inherent properties and high-level texture and structure controllability of the perovskite nanosheets, therefore realizing both a high dielectric constant and good insulating properties in a nano-region.

Abstract: A monolithic ceramic capacitor includes dielectric ceramic layers having a thickness of less than 1 ?m. When this thickness is t and the crystal grains of a dielectric ceramic of the layers have a mean diameter of r, a mean number N of grain boundaries satisfies 0<N?2 where N=t/r?1. The dielectric ceramic contains, as a main component, a perovskite type compound ABO3 (where A is Ba or Ba and at least one of Ca and Sr, B is Ti or Ti and at least one of Zr and Hf), and further contains Mn and V as auxiliary components. On the basis of 100 molar parts of the main component, the content of Mn is 0.05 to 0.75 molar parts, the content of V is 0.05 to 0.75 molar parts, and the total content of Mn and V is 0.10 to 0.80 molar parts.

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, and cause a short-circuit. The inner conductor is printed in such a manner that the center of each of the via conductors is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability that the inner conductor contact the via conductor and cause a short-circuit is minimized.

Abstract: The dielectric of a capacitor is formed by superposition of at least two thin layers made from the same metal oxide, respectively in crystalline and amorphous form and respectively presenting quadratic voltage coefficients of capacitance of opposite signs.

Abstract: The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiO2 layer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers. Crystallization is obtained via heat treatment. When used in a metal-insulator-metal capacitor, the stack of layers can provide improved characteristics as a consequence of the TiO2 layer being present in the sub-stack.

Abstract: A method and class of circuit configurations for coupling low-frequency signals from one stage of an electronic apparatus to another stage, from the outside world to such a stage, or from such a stage to the outside world, through the use of a plurality of symmetrical double-layer capacitors combined with other electronic components are disclosed. The capacitors are used for signal transmission while blocking direct current, rather than for energy storage. Use of double-layer capacitors in place of more conventional capacitors permits the transmission of a much wider range of signals with far less distortion. The technology is particularly well-adapted to use in medical devices, including bioelectronic stimulators, where redundant devices are required for safety in case of single component failure while unacceptable levels of distortion may occur when conventional components are used.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: Systems and methods are provided for fabricating a thin film capacitor involving depositing an electrode layer of conductive material on top of a substrate material, depositing a first layer of ferroelectric material on top of the substrate material using a metal organic deposition or chemical solution deposition process, depositing a second layer of ferroelectric material on top of the first layer using a high temperature sputter process and depositing a metal interconnect layer to provide electric connections to layers of the capacitor.

Abstract: A method for manufacturing a laminated electronic component includes the steps of preparing a component main body having a laminated structure, the component main body including a plurality of internal electrodes formed therein, and each of the internal electrodes being partially exposed on an external surface of the component main body, and forming an external terminal electrode on the external surface of the component main body such that the external terminal electrode is electrically connected to the internal electrodes. The step of forming the external terminal electrode includes the steps of forming a first plating layer on exposed surfaces of the internal electrodes of the component main body, applying a water repellant at least on a surface of the first plating layer and on a section in the external surface of the component main body at which an end edge of the first plating layer is located, and then forming a second plating layer on the first plating layer having the water repellant applied thereon.

Abstract: As system is disclosed for providing power averaging for the utility grids and more specifically to utilizing a unique EESU unit with the capability to store electrical energy over 24 hour periods each day and provide power averaging to homes, commercial, and industrial sites to reduce the peak power requirements. Charging such power averaging units during the non-peak times and delivering the energy during the peak-demands times provides for more efficient utilization of utility-grid power-generating plants and the already existing power transmission lines. Such a unit may also have the capability of isolating the users from utility-grid power failures, transients, and AC noise.

Abstract: In a laminated ceramic electronic component including a ceramic element body including a plurality of effective sections, each of which constitutes a circuit element such as a laminated capacitor unit, bumps generated between the effective portions and a gap interposed between the effective portions can be made minimized. Specifically, the ceramic element body includes a first effective section including a first circuit element and a second effective section including a second circuit element. A gap is provided between the first and second effective section. Floating internal conductors are arranged in the gap at least in one of first and second external layer sections, the first external section being interposed between a first main surface and the first and second effective sections, and the second external layer section being interposed between a second main surface and the first and second effective sections.

Abstract: An electronic component includes a substantially rectangular parallelepiped electronic component body and first to fourth external electrodes. The first to fourth external electrodes are arranged such that a shaped defined by joining the centers of portions of the first to fourth external electrodes on a first main surface with a substantially straight line is substantially square. The first main surface is provided with a substantially linear orientation identifying mark disposed thereon. The orientation identifying mark passes through an intersection of two diagonals of the substantially square shape and extends along the longitudinal direction or the width direction.

Abstract: A capacitor comprises a substrate layer, a first electrode layer disposed on the substrate layer, and a first dielectric layer disposed on the electrode layer. The dielectric layer comprises a polymeric material having an elongation less than or equal to about 5 percent.

Abstract: A structural capacitor includes a first carbon fiber material layer, a second carbon fiber material layer, and an interlayer dielectric including a diamond-like-carbon material layer.

Abstract: Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a continuous concentration gradient of a second component relative to a first component. The continuous concentration gradient may correspond to a decreasing concentration of the second component as a distance from the first capacitor electrode increases. The first component may be selected from the group consisting of zirconium oxide, hafnium oxide and mixtures thereof; and the second component may be selected from the group consisting of niobium oxide, titanium oxide, strontium oxide and mixtures thereof. A second capacitor electrode may be formed over the first capacitor electrode. Some embodiments include capacitors that contain at least one metal oxide mixture having a continuous concentration gradient of the above-described second component relative to the above-described first component.

Abstract: A laminated ceramic capacitor capable of achieving both a high dielectric constant and high electrical insulation property even when the thickness of the dielectric ceramic layer is less than 1 ?m, contains a plurality of laminated dielectric ceramic layers and a plurality of internal electrodes at interfaces between the dielectric ceramic layers, where dielectric ceramic layers are made of dielectric ceramic containing a perovskite-type compound represented by ABO3 as a main ingredient, and R (R is La or the like), M (M is Mn or the like) and Si as accessory ingredients.

Abstract: A dielectric ceramic includes crystal grains containing barium titanate as a main component, magnesium, a rare-earth element, and manganese, wherein the crystal grains have a cubic crystal structure; and the dielectric ceramic contains, per mole of barium, 0.033 to 0.085 mol of magnesium in terms of MgO, 0.1 to 0.2 mol of the rare-earth element (RE) in terms of RE2O3, and 0.006 to 0.018 mol of manganese in terms of MnO. Such a dielectric ceramic has a high relative dielectric constant, stable temperature characteristic of the relative dielectric constant, and no spontaneous polarization.

Abstract: A multilayer capacitor comprises a capacitor element body constituted by a plurality of laminated dielectric layers; first and second signal terminal electrodes and a ground terminal electrode which are arranged on an outer surface of the capacitor element body; and a ground electrode, first and second signal electrodes, and an intermediate internal electrode which are arranged within the capacitor element body. The first signal electrode is connected to the first signal terminal electrode, while the second signal electrode is connected to the second signal terminal electrode. The ground electrode is connected to the ground terminal electrode and has a first region overlapping the first signal electrode in a first direction in which the plurality of dielectric layers are laminated and a second region overlapping the second signal electrode in the first direction.

Abstract: In one aspect of the present invention, a method for increasing the dielectric breakdown strength of a polymer is described. The method comprises providing the polymer and contacting a surface of the polymer in a reaction chamber with a gas plasma, under specified plasma conditions. The polymer is selected from the group consisting of a polymer having a glass transition temperature of at least about 150° C., and a polymer composite comprising at least one inorganic constituent. The contact with the gas plasma is carried out for a period of time sufficient to incorporate additional chemical functionality into a surface region of the polymer film, to provide a treated polymer. Also provided are an article and method of manufacture.

Abstract: A resistance memory element is provided which has a relatively high switching voltage and whose resistance can be changed at a relatively high rate. The resistance memory element includes an elementary body and a pair of electrodes opposing each other with at least part of the elementary body therebetween. The elementary body is made of a semiconductor ceramic expressed by a formula: {(Sr1-xMx)1-yAy}(Ti1-zBz)O3 (wherein M represents at least one of Ba and Ca, A represents at least one element selected from the group consisting of Y and rare earth elements, and B represents at least one of Nb and Ta), and satisfies 0<x?0.5 and 0.001?y+z?0.02 (where 0?y?0.02 and 0?z?0.02); 0.5<x?0.8 and 0.003?y+z?0.02 (where 0?y?0.02 and 0?z?0.02); or 0.8<x?1.0 and 0.005?y+z?0.01 (where 0?y?0.02 and 0?z?0.02).

Abstract: A capacitor device may include a first electrode, a second electrode, a third electrode, a first dielectric layer, and a second dielectric layer. The first electrode may be coupled with a first terminal of the capacitor device. The second electrode is under the first electrode and may be coupled with a second terminal of the capacitor device. The second electrode may be electrically isolated from the first electrode. The third electrode is under the first electrode and the second electrode and may be electrically isolated from the second electrode and electrically coupled with the first electrode. The first dielectric layer has a first dielectric constant and may be sandwiched between the first electrode and the second electrode. The second dielectric layer may have a second dielectric constant and may be sandwiched between the second electrode and the third electrode. In one embodiment, the second dielectric constant is at least five times larger than the first dielectric constant.

Abstract: A method for manufacturing a multilayer ceramic electronic component includes a first substep of depositing precipitates primarily made of a specific metal on an end of each of internal electrodes exposed at a predetermined surface of a laminate and growing the precipitates to coalesce into a continuous plated sublayer, and a second substep of heat-treating the laminate including the plated sublayer at a temperature of at least about 800° C., wherein a plated layer including a plurality of plated sublayers is formed by continuously performing at least two cycles of the first substep and the second substep.

Abstract: Capacitors are provided comprising a first plate, a second plate spaced from the first plate and a dielectric between the first and second plates. In certain embodiments the plates are arranged generally opposite each other and each is shaped in a periodically repeating pattern that is spatially out of phase with the other so that misregistration of the plates is compensated. In certain embodiments, a floating equipotential conductor is positioned between the plates and has a larger dimension than a corresponding dimension of the plates so that misregistration of the plates is compensated. Methods of manufacturing the capacitors are also provided.

Abstract: A multilayer electronic component includes a ceramic body including ceramic layers that are laminated to one another and internal conductors having exposed portions at side surfaces of the ceramic body. Substantially linear connection portions extend in the lamination direction of the ceramic layers so as to connect the exposed portions to one another. External terminal electrodes cover the exposed portions of the internal conductors and the connection portions and include base plating films directly disposed on the side surfaces by plating. The connection portions are formed by polishing the side surfaces in which the internal conductors are exposed using, for example, a brush so as to elongate the exposed portions of the internal conductors.

Abstract: A multilayer capacitor comprises a capacitor element body; a first signal terminal electrode, a second signal terminal electrode, and a ground terminal electrode which are arranged on an outer surface of the capacitor element body; and a ground internal electrode and first to third signal internal electrodes which are arranged within the capacitor element body. The ground internal electrode is connected to the ground terminal electrode. The first signal internal electrode is connected to the first signal terminal electrode and opposes the ground internal electrode so as to construct a first capacitor. The second signal internal electrode is connected to the first signal terminal electrode and opposes the ground internal electrode so as to construct a second capacitor. The third signal internal electrode is connected to the second signal terminal electrode and opposes the ground internal electrode so as to construct a third capacitor.

Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

Abstract: A capacitor element includes a positive electrode body made of valve metal, a dielectric oxide layer on the positive electrode body, a solid electrolytic layer made of conductive polymer on the dielectric oxide layer, and a negative electrode layer on the solid electrolytic layer. A solid electrolytic capacitor includes the capacitor element, a package made of insulating resin covering the capacitor element, a base electrode provided at an edge surface of the package and made of non-valve metal coupled with the positive electrode body, a diffusion layer for connecting the positive electrode body to the base electrode, an external electrode on the base electrode, and an external electrode connected to the negative electrode layer. The solid electrolytic capacitor reduces the number of components and processes to reduce its cost and to have a small size, and has a small equivalent series resistance and a small equivalent series inductance.

Abstract: A monolithic ceramic electronic component includes a dummy electrode having a dummy body portion and an internal electrode having an extended portion, in which the conductor density of the dummy body portion is less than the conductor density of the extended portion of an internal electrode. With this configuration, the fixing strength of an external terminal electrode to a ceramic element assembly is improved, and undesirable deformation caused by a dummy conductor provided in a monolithic ceramic electronic component is prevented.

Abstract: A connector assembly utilizes improved capacitive coupling for connecting together electrical circuits on two substrates (7, 8). The connector assembly includes first (2) and second (3) connectors respectively attached to first and second circuit substrates. The first connector includes a plurality of first conductors (25) connected to circuits (75) on the first circuit substrate and these conductors have exposed contact surfaces with a dielectric material (4) disposed thereon. The first conductors and associated dielectric material confront second, opposing conductors (35) supported by the second connector frame when the connector frames are engaged together. A liquid dielectric material (45) is interposed between the terminals and the dielectric portions that fills minute gaps which may occur in the dielectric portions to improve the capacitive coupling ability of the connector assembly.

Abstract: The invention relates to a multilayer ceramic capacitor having dielectric layers and internal electrode layers disposed alternately. The dielectric layers include a dielectric ceramic containing barium titanate as a main component, and also calcium, magnesium, vanadium, manganese, and a rare-earth element. Crystals constituting the dielectric ceramic are constituted by grains containing barium titanate as their main component and containing calcium in a concentration of 0.2 atomic % or less or containing the calcium in a concentration of 0.4 atomic % or more. The crystals grains are also distinct in their relative distributions of magnesium and rare-earth elements between the center of the grain and the surface of the grain. Finally, the relative areas of the two kinds of crystals observed in the plane of a polished surface of the dielectric ceramic are described by a ratio b/(a+b), which is 0.5 to 0.8.

Abstract: A multi-layered circuit board is provided having a buried capacitive layer and a device-specific embedded, localized, non-discrete, and distributive capacitive element. A printed circuit board is provided including (1) a first dielectric layer, (2) a first conductive layer coupled to a first surface of the first dielectric layer, (3) a second conductive layer coupled to a second surface of the first dielectric layer, and (4) a localized distributive non-discrete capacitive element adjacent the first conductive layer, wherein the capacitive element occupies a region that approximately coincides with a location over which a device to be coupled to the capacitive element is to be mounted. The embedded, localized, non-discrete, and distributive capacitive element may provide device-specific capacitance to suppress voltage/current noise for a particular device.

Abstract: Provided are a high voltage multi-layer ceramic capacitor (MLCC) that may enable a surface mounting, and may form a guide electrode between inner electrodes or between sealing electrodes to thereby prevent a decrease in an inner voltage, caused by a parasitic capacitance, and a director current (DC)-link capacitor module using the MLCC.

Abstract: Provided is a MLCC module used as a direct current (DC) link capacitor that is included in an inverter of a hybrid vehicle.

Abstract: A SrTiO3-based grain boundary insulation type semiconductor ceramic contains a donor element in solid solution in crystal grains, an acceptor element at least in crystal grain boundaries, an integral width of (222) face of the crystal face of 0.500° or less, and an average powder grain size of crystal grains of 1.0 ?m or less. A semiconductor ceramic is obtained by firing this ceramic, and a monolithic semiconductor ceramic capacitor is obtained by using the semiconductor ceramic. The SrTiO3-based grain boundary insulation type semiconductor ceramic powder has a large apparent relative dielectric constant ?rAPP of 5,000 or more even when the average ceramic grain size of crystal grains is 1.0 ?m or less and which has an excellent insulating property. The monolithic semiconductor ceramic capacitor is capable of having a large capacity through reduction in thickness and multilayering.

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract: A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes.

Abstract: An MOM capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one oxide layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: Various capacitors for use with integrated circuits and other devices and fabrication methods are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first capacitor plate that has at least two non-linear strips and forming a second capacitor plate that has a non-linear strip positioned between the at least two non-linear strips of the first capacitor plate. A dielectric is provided between the non-linear strip of the second capacitor plate and the at least two non-linear strips of the first capacitor plate.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a plurality of ceramic layers, the ceramic body having a first main surface and a second main surface and a plurality of side surfaces that connect the first main surface to the second main surface, an internal conductor including nickel, the internal conductor being disposed in the ceramic body and having an exposed portion exposed at least one of the side surfaces, and an external terminal electrode disposed on at least one of the side surfaces of the ceramic body, the external terminal electrode being electrically connected to the internal conductor. The external terminal electrode includes a first conductive layer including a Sn—Cu—Ni intermetallic compound, the first conductive layer covering the exposed portion of the internal conductor at least one of the side surfaces of the ceramic body.

Abstract: Electronic device 1 comprises an element body 10, comprising a dielectric layer 2 constituted by a dielectric ceramic composition, and a terminal electrode 4, formed outside of the element body 10. The dielectric ceramic composition comprised a main component including barium titanate; a first subcomponent including at least one oxide of Mg and Ca; a second subcomponent including SiO2; a third subcomponent including at least one oxide of Mn and Cr; and a fourth subcomponent including an oxide of rare earth elements, wherein the net valence of Mn and/or Cr in the third subcomponent is 2.2 to 2.4. According to the electronic device 1, both high temperature accelerated lifetime characteristics and capacity stress aging characteristics can be improved in a balanced manner.

Abstract: Better high-temperature load characteristics are obtained in a laminated ceramic capacitor including a dielectric ceramic layer with a thickness of 1 ?m or less. The laminated ceramic capacitor includes a plurality of stacked dielectric ceramic layers, a plurality of internal electrode layers, each disposed between dielectric ceramic layers, and external electrodes that are electrically connected to internal electrode layers. In this laminated ceramic capacitor, when the thickness of each dielectric ceramic layer is denoted by tc and the thickness of each internal electrode layer is denoted by te, tc is 1 ?m or less, and tc/te is equal to or less than 1.

Abstract: A capacitor includes a multi layer structure on a ceramic or crystalline substrate. The multilayer structure includes a lower electrode, an upper electrode, and a dielectric that is tunable by a voltage applied to the electrodes. The multilayer structure is configured such that resonant oscillation modes of bulk acoustic waves can be propagated in the multilayer structure and such that the resonant frequencies of the oscillation modes are outside a first band range of between 810 and 1000 MHz, second band range of between 1700 and 2205 MHz and third band range of between 2400 and 2483.5 MHz.