Shared Electrode Patents (Class 361/330)
  • Patent number: 7457100
    Abstract: A capacitor device is provided which includes a plurality of electric double-layer capacitors connected in series, and a balance resistor portion where five resistors having an equivalent resistance are connected in parallel. In this capacitor device, the balance resistor portion is connected to each electric double-layer capacitor, so that the electric double-layer capacitors connected in series can be charged uniformly.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: November 25, 2008
    Assignee: Panasonic Corporation
    Inventors: Norio Nakajima, Kouji Moriyama, Yoshihiro Watanabe
  • Publication number: 20080174938
    Abstract: A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 24, 2008
    Inventors: John S. Guzek, Cengiz A. Palanduz, Victor Prokofiev
  • Publication number: 20080130200
    Abstract: The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
    Type: Application
    Filed: February 21, 2008
    Publication date: June 5, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Anil K. Chinthakindi, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Sarah L. Lane, Anthony K. Stamper
  • Patent number: 7342768
    Abstract: Provided are active balancing modules that control voltage imbalances between capacitors stacked in a series arrangement and methods for their manufacture. These modules are simple and inexpensive to manufacture, and versatile. They may be used alone or they may be combined together to form a multi-module active balancing circuitry for a plurality of capacitors stacked in a series arrangement. The modules may further be aligned in either a side-by-side topology or an overlapping topology.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: March 11, 2008
    Assignee: Cooper Technologies Company
    Inventors: Frank Anthony Doljack, Neal Schultz, Hundi P. Kamath, Jim Strain
  • Patent number: 7301752
    Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: November 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Natalie B. Feilchenfeld, Michael L. Gautsch, Zhong-Xiang He, Matthew D. Moon, Vidhya Ramachandran, Barbara Waterhouse
  • Patent number: 7161792
    Abstract: A capacitor cell for reducing noise in a high drive cell includes a plurality of vias for supplying power to an interconnection layer positioned over the capacitor cell from an upper interconnection layer, so that the resistance of the power supply path is reduced.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: January 9, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Taro Sakurabayashi, Toshikazu Kato
  • Patent number: 7102873
    Abstract: A capacitor element on a chip, e.g., a MMIC chip, includes a main capacitor in parallel with a series configuration of trimming capacitors. The total capacitance value of the parallel arrangement can be increased from its inherently minimum value by applying one or more laser pulses to one or more of the trimming capacitors, such that in each case a short-circuit is produced between the metallization layer to which the pulses are applied and the other metallization layer making up the trimming capacitor.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: September 5, 2006
    Assignee: Marconi Communications GmbH
    Inventors: Stefan Kern, Marco Trautwein, Martin Schallner
  • Patent number: 7042704
    Abstract: The present invention is directed to a high-voltage capacitor, high-voltage capacitor device and magnetron in which, undesirable radiation waves generated in the frequency range of 450 MHz to 1000 MHz in a magnetron are suppressed to such a level that there is no adverse effect on the peripheral devices. The dielectric porcelain comprises a body 210 and through holes 211, 212. The body 210 includes a portion (216, 217) that is narrowed on both sides in the middle of the body in the plan view. The through holes 211, 212 are formed in the body, arranged at a distance from each other over the narrowed portion (216, 217). One individual electrode 213 is provided on the surface of the body 210 at which the through hole 211 opens. The other individual electrode 214 is provided on the surface of the body 210 at which the through hole 212 opens. The common electrode 215 is provided on another surface of the body 210 at which the through holes 211, 212 open.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: May 9, 2006
    Assignee: TDK Corporation
    Inventors: Tsukasa Sato, Isao Fujiwara, Ryo Kudo, Hisashi Tanaka
  • Patent number: 7042701
    Abstract: A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: May 9, 2006
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Frederic J. Bernard
  • Patent number: 7019959
    Abstract: Upper, inner and lower sections (182, 180 and 184) of a PCB (100) are formed with each section having a substrate (140, 150 and 160) having patterned layers of metallization (105 and 110, 115 and 120, and 125 and 130), respectively. Some of the patterned layers of metallization (110, 115, 120, and 125) have thicker portions (171, 173) and part (188) of portion (186), and thinner portions (172, 174, 187, 190, 191, 192 and 193). The resultant thinner portion (175 and 194) in the prepreg layers (145 and 155) with the respective thicker portions of metallization provide decoupling capacitors, while the resultant thicker portions (196 and 198), for example, provide a lower capacitance for improved trace impedance for the signal traces (191 and 192).
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: March 28, 2006
    Assignee: Gul Technologies Singapore Ltd
    Inventor: Ah Lim Chua
  • Patent number: 6944009
    Abstract: Systems and apparatuses for providing a broadband capacitor assembly. One broadband capacitor assembly includes a first capacitor operable to provide a first end of an operational band of frequencies within an operational band of a broadband capacitor assembly. The broadband capacitor assembly also includes a second capacitor coupled in parallel to the first capacitor, the second capacitor operable to provide a second end of the operational band of frequencies within the operational band of the broadband capacitor assembly. A DC block can be provided including a broadband capacitor assembly.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: September 13, 2005
    Assignee: Oplink Communications, Inc.
    Inventors: John A. Nguyen, Anand Gundavajhala
  • Patent number: 6928726
    Abstract: A substrate assembly (10) and method of making same has at least one embedded component (25) in a via (24) of a substrate core (22) and includes a first adhesive layer (20) coupled to the substrate core, and a second adhesive layer (26) on at least portions of a top surface of the substrate core and above portions of the embedded component. The substrate assembly can further include a first conductive layer (18) adhered to the bottom surface of the substrate core and a second conductive layer (28) on the second adhesive layer. The substrate assembly can further include an interconnection (36) between a conductive surface of the embedded component and at least one among the first conductive layer and the second conductive layer. The interconnection can be formed through an opening (34) that at least temporarily exposes at least a conductive surface (32) of the embedded component.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: August 16, 2005
    Assignee: Motorola, Inc.
    Inventors: James A. Zollo, John K. Arledge, John C. Barron, Gary R. Burhance, John Holley, Henry F. Liebman
  • Patent number: 6842327
    Abstract: A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate comprising a first semiconductive body and a second plate comprising a floating electrode. The first and second semiconductor bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: January 11, 2005
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Frederic J. Bernard
  • Publication number: 20030231459
    Abstract: My present Ion Chip Composite Emitter Invention was developed specifically to overcome problems experienced of an operational and maintenance nature of prior designs. And relates to the inherently stable ionising capability of a three layered robust construction connected to a regulated High Voltage power source. To provide highly directional reliable strongly focused, predictable modularly adjustable streams of small active negative air ions with only trace ozone entrained. To be safely and strategically injected into the ambient air and ion multiplying ventilation air flows of an enclosed, occupied, prospectively hazardous environment. Providing the control and precipitation of harmful air borne contaminants and remedying deficiencies of Electrical Air Quality of unacceptable levels of positive air ion imbalance.
    Type: Application
    Filed: October 25, 2001
    Publication date: December 18, 2003
    Inventor: Reginald R. Robertson
  • Patent number: 6611421
    Abstract: Non-polar tantalum capacitors and non-polar tantalum capacitor arrays with compact designs are provided. The reduced volume and footprint of the capacitors and arrays in turn reduces the amount of space required in any device in which they are used. In addition, the cost of materials is reduced, and the manufacturing is simplified. Some embodiments of the present invention provide an electromechanical connector between the anode rods of each pair of polar tantalum capacitors, and insulation between the remainder of the capacitor bodies, thus providing a non-polar tantalum capacitor. These non-polar capacitors are mechanically connected to make a non-polar tantalum capacitor array. Other embodiments of the present invention provide for physically connecting the anode rods of the polar capacitors. An insulating encapsulant around the connected rods and between the polar capacitor bodies also holds the capacitors and capacitor arrays together.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: August 26, 2003
    Assignees: AVX Corporation, Advanced Bionics Corporation
    Inventors: Paul M. Meadows, James A. McAllister, David H. Payne, Douglas M. Edson
  • Patent number: 6597561
    Abstract: An electrical contact system is provided which comprises an electrically conductive porous fleece and one or more contact bodies. The electrically conductive porous fleece and the contact bodies are sintered to each other, so avoiding hot spots during the use of the element.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: July 22, 2003
    Assignee: N.V. Bekaert S.A.
    Inventors: Geert Devooght, Willy Marrecau
  • Patent number: 6545565
    Abstract: In a band elimination filter, a trap capacitor and a frequency control capacitor are made by using a simple capacitor plate individually provided for each respective resonance circuit.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: April 8, 2003
    Assignee: Murata Manufacturing Co. Ltd.
    Inventor: Masayuki Atokawa
  • Patent number: 6525628
    Abstract: Both discrete and array RC components are described using cofireable resistive material as part of internal electrodes of the device. The devices include a sintered body of multilayer ceramic material in which multiple first and second electrode layers are stacked. Each of the first layers comprises at least one resistive electrode pattern extending across the sintered body between respective pairs of terminations. The second layers comprise an electrode pattern extending transverse to the resistive electrode pattern, such as between end terminations. In some embodiments, opposing side electrodes serve as input and output terminals of a respective feedthrough filter. In a feedthrough arrangement, the third terminal may be provided by one or both of the end terminals. The invention also describes an improved termination structure including a layer made from a metal oxide material.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: February 25, 2003
    Assignee: AVX Corporation
    Inventors: Andrew P. Ritter, Andrew Blair, Maureen Strawhorne, Clare Ashley Moore, Robert H. Heistand, II
  • Patent number: 6525924
    Abstract: The invention relates to a device for accumulation of electrical energy. The device is a substantially cylindrical winding of strips. At least one strip is a strip conductor. The device is defined transversally by a substantially cylindrical lateral face and longitudinally by two opposite end faces. Each of the two opposite end faces contains an edge of the strip conductor. In the device, at least one of the edges of at least one strip conductor contains a plurality of teeth. The teeth are disposed on at least one of the end faces and form at least one set in which they are substantially superimposed in a predetermined direction, approximately perpendicular to a plane tangent to the cylindrical face. The teeth constitute a group of elements of electrical connection to a terminal and in which each element extends itself in continuity with the strip conductor which comprises the element.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: February 25, 2003
    Assignee: Montena Components S.A.
    Inventors: Roland Gallay, Dominique Guillet, Vincent Hermann, Adrian Schneuwly
  • Publication number: 20020163769
    Abstract: A capacitive device formed on a substrate is provided that comprises a first set of terminals and a second set of terminals. The first set of terminals comprises a positive input terminal and a negative input terminal. The second set of terminals comprises a positive output terminal and a negative output terminal. The capacitor structure further comprises a first film electrode layer disposed above the substrate and having an input side and an output side, the input side having means for providing a coupling location for the negative input terminal, the output side having means for providing a coupling location for the negative output terminal. The capacitor structure further comprises a second film electrode layer also disposed above the substrate and having an input side and an output side, the input side having means for providing a coupling location for the positive input terminal, the output side having means for providing a coupling location for the positive output terminal.
    Type: Application
    Filed: April 19, 2001
    Publication date: November 7, 2002
    Inventor: David Richard Brown
  • Patent number: 6470545
    Abstract: Embedded green multi-layer ceramic capacitors in low-temperature co-fired ceramic (LTCC) substrates are provided. A first set of electrodes is printed on a ceramic tape. A first dielectric layer is placed over the first set of electrodes and the ceramic tape. A second set of electrodes is printed on the first dielectric layer. A second dielectric layer is placed over the second set of electrodes and the first dielectric layer. A third set of electrodes is printed on the second dielectric layer. The sheet is then cut to form separate green multi-layer ceramic capacitor chips. The green multi-layer ceramic capacitor chips are then placed in a cavity formed by ceramic tape.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 29, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Shaul Branchevsky
  • Patent number: 6469886
    Abstract: A monolithic integrated capacitor is formed by two conductive coatings applied to a substrate and separated from each other by a dielectric layer. The upper coating lying on the dielectric layer is connected via at least one conductive air bridge with at least one of a pair of connection lines of the capacitor. Parasitic inductances of the capacitor are largely compensated by connecting the two connection lines together by at least one high resistance line bridging the capacitor.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: October 22, 2002
    Assignee: Robert Bosch, GmbH
    Inventor: Hardial Gill
  • Patent number: 6441459
    Abstract: A multilayer electronic device comprised of a capacitor body in which a plurality of internal electrodes are separately arranged in a plurality of blocks via ceramic layers. At least one lead is led out from each internal electrode. The terminal electrodes connected to each lead is arranged at the side faces of the capacitor body. The polarities of the voltages supplied to the nearby terminal electrodes in the same side face differ.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: August 27, 2002
    Assignee: TDK Corporation
    Inventors: Masaaki Togashi, Taisuke Ahiko, Osamu Honjyo
  • Patent number: 6243605
    Abstract: A multi-capacitor module carries vertically-oriented surface mount tantalum capacitors. The module provides at least one conductor for coupling to the substrate capacitor terminals that are distal thereto. The module occupies less space, when mounted to a circuit board substrate, than individually mounting the bases of the surface mount capacitors to the substrate. This allows more efficient use of volume within an implantable cardiac rhythm management device, reducing its size, or alternatively, increasing its implanted longevity.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: June 5, 2001
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Nick A. Youker, Ronald L. Anderson, Sandra J. Overkamp
  • Patent number: 5940263
    Abstract: A device is disclosed for connecting a plurality of capacitors between a first and a second terminal. The device includes a plurality of bus bars located in a parallel spaced apart relationship. A plurality of fasteners fasten the plurality of capacitors between adjacent bus bars. A plurality of shims are interposed between selected bus bars and the first and second terminal for electrically connecting the plurality of capacitors between the first and second terminals.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: August 17, 1999
    Inventor: Albert Jakoubovitch
  • Patent number: 5822174
    Abstract: A multilayer feedthrough capacitor of the present invention has an internal structure of stacking one over another alternately dielectric sheets 1a, on each of which signal feedthrough electrodes 2a, 2b and 2c and separating earth electrodes 7a and 7b are disposed alternately, and dielectric sheets 1b, on each of which earth electrodes 3a and 3b having protrusions 8a and 8b, respectively, are formed. On one pair of the end surfaces of this stacked dielectric body are formed first external electrodes 4a, 4b and 4c that are connected to signal feedthrough electrodes 2a, 2b and 2c, respectively, and third external electrodes 9a and 9b that are connected to both separating earth electrodes 7a and 7b and protrusions 8a and 8b, respectively. On the other pair of the end surfaces are formed second external electrodes 5a and 5b that are connected to earth electrodes 3a and 3b, respectively.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: October 13, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazunori Yamate, Chikara Watanabe
  • Patent number: 5777839
    Abstract: A capacitor using a dielectric film wherein plural capacitor units each including one or two capacitor elements are formed on an insulator upper electrodes of at least two capacitor elements of different capacitors units are electrically connected. Each of the capacitors includes a lower filmy electrode, a dielectric film formed on the lower filmy electrode, and an upper filmy electrode formed on the dielectric film. Since plural capacitor units are suitably connected to have desired characteristics, a great deal of flexibility is realized.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: July 7, 1998
    Assignee: ROHM Co., Ltd.
    Inventors: Katsumi Sameshima, Teruo Shiba
  • Patent number: 5751539
    Abstract: An improved ceramic feedthrough capacitor design which results in distinct advantages in EMI (electromagnetic interference) filtering and therapeutic waveform management for implantable defibrillators and pacemakers and the like. The invention provides ceramic capacitor electrode plate designs which provide both low impedance decoupling for EMI suppression, and, at the same time provide an isolated common ground point through a separate coupling capacitor for electrical isolation of the filtered circuit from the metal case (usually titanium) of the defibrillator or the like. Such an arrangement allows the defibrillator HV (high voltage) output pulse to the heart to be referenced lead to lead (including reverse polarity), or from either lead to a common floating ground point or to the titanium case. The primary application of the invention is directed to implantable defibrillators where the output pulse to the heart is typically high voltage (up to 750 volts) and of short duration (typically in the 10.times.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: May 12, 1998
    Assignee: Maxwell Laboratories, Inc.
    Inventors: Robert A. Stevenson, Dick H. Ni
  • Patent number: 5726608
    Abstract: The invention provides a trimmable multi-terminal capacitor. The multi-terminal capacitor comprises a plurality of capacitors with each of the capacitors having a common terminal. The capacitors are formed on a layer of dielectric material having a common plate of conductive material disposed on its top surface, and a plurality of separate plates of conductive material disposed on its lower surface. The capacitance value of each of the capacitors is separately tunable to tight tolerances. The capacitor is particularly suited to be used in a voltage controlled oscillator (VCO) to couple a plurality of devices to a resonator.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: March 10, 1998
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Michael .ANG.rlin
  • Patent number: 5694309
    Abstract: A power conversion array delivers power to a load. The array includes at least four power converters, each of the power converters comprising an output power port for connection to the load and a synchronization port for passing synchronization information. A synchronization medium connected to the synchronization ports of the converters carries the synchronization information among the converters. The synchronization medium defines paths among the synchronization ports such that every synchronization port is connected to every other synchronization port by at least one path that does not include a connection to the synchronization port of any of the other converters. In another aspect, in arrays which include at least three power converters, the synchronizing medium conveys synchronizing information via impedance elements connected to the synchronization ports by coupling conductors, and the path between any pair of coupling conductors includes exactly two impedance elements.
    Type: Grant
    Filed: April 16, 1996
    Date of Patent: December 2, 1997
    Assignee: VLT Corporation
    Inventors: Jay Prager, Patrizio Vinciarelli
  • Patent number: 5644468
    Abstract: An X-Y condenser having an X-capacitance and two Y-capacitances, for example, for connection as a line filter, has a base winding of metallized dielectric foil strip on which a pair of axially spaced auxiliary windings are applied. A deposited metal contact at each end connects each Y-capacitance winding with the X-capacitance winding while a metal deposit between the Y-capacitance windings forms a common contact therewith.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: July 1, 1997
    Assignee: Eichhoff GmbH
    Inventors: Reinhold Wink, Mathias Gruner
  • Patent number: 5608246
    Abstract: An integrated circuit capacitor and method for making the same utilizes a ferroelectric dielectric, such as lead-zirconate-titanate ("PZT"), to produce a high value peripheral capacitor for integration on a common substrate with a ferroelectric memory array also utilizing ferroelectric memory cell capacitors as non-volatile storage elements. The peripheral capacitor is linearly operated in a single direction and may be readily integrated to provide capacitance values on the order of 1-10 nF or more utilizing the same processing steps as are utilized to produce the alternately polarizable memory cell capacitors. The high value peripheral capacitor has application, for example, as a filter capacitor associated with the on-board power supply of a passive radio frequency ("RF") identification ("ID") transponder.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: March 4, 1997
    Assignee: Ramtron International Corporation
    Inventors: Michael W. Yeager, Dennis R. Wilson
  • Patent number: 5589298
    Abstract: Electrochemical devices comprise at least a pair of electrodes and a lithium ion conductive electrolyte provided between the pair of electrodes. At least one of the electrodes comprises a lithium nitride-metal compound having a one-dimensional chain structure. By this, the number of end groups which greatly take part in characteristic degradation of the device can be reduced significantly, ensuring good characteristic properties. The devices include lithium secondary cells, electric double-layer capacitors, and electrochemical display devices.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: December 31, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazunori Takada, Shigeo Kondo, Osamu Yamamoto, Motoaki Nishijima
  • Patent number: 5590016
    Abstract: The invention decreases crosstalk due to capacitive coupling between through type capacitor elements in a multilayer through type capacitor array. On dielectric sheets between electrodes, which constitute a multi capacitor array, through-holes filled with conductive materials are formed, where a central conductor is not present. By electrically connecting conductive materials filled in the through-holes, electrostatic shielding is provided between the through type capacitor elements. Electrical connection is achieved through conductive layers formed outside or inside the through type capacitor elements.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: December 31, 1996
    Assignee: TDK Corporation
    Inventors: Yoshikazu Fujishiro, Takaya Ishigaki, Hiraku Harada
  • Patent number: 5544002
    Abstract: A high voltage capacitor is disclosed that comprises a grounding member (1), two through type capacitors (2 and 3), an insulating case (6) and insulating resin (71 and 72). The grounding member (1) has two raised portions (101 and 102) on which the through type capacitors (2 and 3) are secured. The insulating case (6) has two hollow cylindrical portions (61, 62) spaced apart by a distance D with their upper open ends joined to each other to form a recessed enclosure (63) in line with and following the inner diameter sections (611, 621) of the hollow cylindrical portions (61, 82) and their lower open ends fitted on the outer circumference of the raised portions (101, 102). The insulating resin (71 and 72) is provided around the through type capacitors (2 and 3) within the inner diameter sections (611, 621).
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: August 6, 1996
    Assignee: TDK Corporation
    Inventors: Shouichi Iwaya, Masahiro Yahagi, Hitoshi Kudou, Shigeru Itou, Isao Fujiwara, Tadashi Ogasawara, Makoto Morita, Teruo Taguchi, Setuo Sasaki
  • Patent number: 5539613
    Abstract: In a semiconductor device which has a substrate, at least one thin film capacitor having a lower electrode layer deposited on the substrate, a dielectric layer overlaid on the lower electrode layer, and an upper electrode layer stacked on the dielectric layer, the lower electrode layer is surrounded by an insulator layer of Si.sub.3 N.sub.4.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: July 23, 1996
    Assignee: NEC Corporation
    Inventors: Shintaro Yamamichi, Toshiyuki Sakuma, Yoichi Miyasaka
  • Patent number: 5521784
    Abstract: Filter unit for connectors comprising at least a substrate (2) made of electrically insulating material and having two mutually opposite sides and through openings (3) for contact elements of the connector, capacitors being situated at least one of the two sides of the substrate in the region of the through openings, which capacitors each comprise at least one first conducting layer (5) in contact with the substrate, a dielectric layer (7) and a second conducting layer (9) and there being provided above each of the capacitors a cover layer (13, 22) composed of at least one first flexible layer (13) substantially covering the top surface of each of the capacitors and having a low moisture absorption coefficient and a high moisture diffusion coefficient and a second hard layer (22) at least entirely covering the first flexible layer and having a high moisture absorption coefficient and a low moisture diffusion coefficient.
    Type: Grant
    Filed: August 2, 1995
    Date of Patent: May 28, 1996
    Assignee: Berg Technology, Inc.
    Inventor: Hubertus B. Libregts
  • Patent number: 5517385
    Abstract: A capacitor structure is described as having a plurality of dielectric materials located so that each dielectric material is in parallel between capacitor plates. The capacitor value of this structure is preset, therefore, for operation electrically at different specific temperatures. The description gives a specific stacked arrangement for the various dielectric materials in which this capacitor can be formed, as one example of that to which it is adaptable.
    Type: Grant
    Filed: July 20, 1994
    Date of Patent: May 14, 1996
    Assignee: International Business Machines Corporation
    Inventors: John Galvagni, Richard G. Murphy, George J. Saxenmeyer
  • Patent number: 5508881
    Abstract: A multi-region material structure and process for forming capacitors and interconnect lines for use with integrated circuits provides (1) capacitor first or bottom electrodes comprising a transition-metal nitride; (2) a capacitor dielectric comprising a transition-metal oxide; (3) capacitor second or top electrodes comprising a transition-metal nitride, a metal or multiple conductive layers; (4) one or more levels of interconnect lines; (5) electrical insulation between adjacent regions as required by the application; and (6) bonding between two regions when such bonding is required to achieve strong region-to-region adhesion or to achieve a region-to-region interface that has a low density of electrical defects.
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: April 16, 1996
    Assignee: Quality Microcircuits Corporation
    Inventor: E. Henry Stevens
  • Patent number: 5495387
    Abstract: A plurality of capacitor elements defined by first and second capacitor electrodes are formed in the interior of a laminated ceramic block, while a plurality of first terminal electrodes to be electrically connected to the first capacitor electrodes and a ground terminal electrode to be connected to the second capacitor electrodes in common are formed on one side surface of the block. A plurality of resistor films are formed on a major surface of the block, to be connected to the first terminal electrodes. A plurality of second terminal electrodes are formed on another side surface of the block, to be electrically connected to the resistor films. Another ground terminal electrode is formed on this side surface, to be connected to the second capacitor electrodes in common. Thus, an RC array being applicable to a high frequency filter array is integrated and miniaturized to cope with high density packaging, as well as to enable surface mounting.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: February 27, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Yoshikazu Chigodo, Kazuhiro Iida
  • Patent number: 5453906
    Abstract: A series section metallized film capacitor in which the metal layers are varied in thickness such that high oxidation areas are thicker than low oxidation areas. In particular, the edge portions bordering a center margin electrode gap have a thickness which is greater than the remaining area of the center margin electrode. The increased thickness at the edge portions reduces the oxidation effect and the associated decrease in capacitance which normally occurs due to the electric potential across the gap. By varying the thickness, the oxidation effect at the edge portions is reduced while the self-healing capabilities at the low oxidation areas is maintained.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: September 26, 1995
    Assignee: Philips Electronics North America Corporation
    Inventor: Kevin J. Doll
  • Patent number: 5442516
    Abstract: A capacitor structure which provides improved electrical performance, utilizing a segmented plate and varied registration alignment. A method for providing improved electrical performance in a capacitor, utilizing a segmented plate structure with varied registration alignment.
    Type: Grant
    Filed: January 3, 1994
    Date of Patent: August 15, 1995
    Inventor: J. Peter Moncrieff
  • Patent number: 5428499
    Abstract: A printed circuit board laminate is disclosed having a high capacitance power distribution core. The power distribution core comprises a pair of conductive plates electrically connected to an array of high capacitance core tiles, separated by a compliant dielectric filler. The resulting capacitance of the power distribution core is sufficient to eliminate the need for decoupling capacitors on a typical printed circuit board. Separate power supply areas of variable decoupling capacitance can be formed for mounted integrated circuits with different power supply requirements. A method for manufacturing such board laminates is also disclosed that is compatible with standard printed circuit board assembly technology.
    Type: Grant
    Filed: January 28, 1993
    Date of Patent: June 27, 1995
    Assignee: Storage Technology Corporation
    Inventors: Stanley R. Szerlip, Floyd G. Paurus, Archibald W. Smith
  • Patent number: 5414589
    Abstract: The present invention provides a capacitor having a changeable dielectric capacity which has advantages in changing the dielectric capacity and increasing the maximum dielectric capacity. The capacitor having a changeable dielectric capacity comprises ceramic main body part 1 in which a first and second internal electrodes 2a and 2b are formed. Four terminal electrodes 3 are formed apart on a face of the ceramic main body part 1. A common terminal electrode 4 is formed on the ceramic main body part 1 so that it connects with the internal electrodes 2a and 2b. To these terminal electrodes 3 and 4 are connected their respective lead wires 5 for wiring.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: May 9, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Koshi Amano, Satoru Yatake
  • Patent number: 5388024
    Abstract: A ceramic capacitor and method of making same is disclosed. The capacitor is trapezoidal in longitudinal section with the electrodes exposed at the angled ends of the trapezoid. The ends face generally in the same direction such that both ends may be simultaneously exposed to a sputtering or vapor deposition procedure and thus sputtered in a single operation without requiring re-masking. The sputtering step, in addition to providing terminations, functions to mechanically couple a multiplicity of capacitors into a compact grouping from which one or more capacitors may be readily extracted.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: February 7, 1995
    Assignee: AVX Corporation
    Inventor: John Galvagni
  • Patent number: 5377072
    Abstract: A single metal-plate bypass capacitor (10) includes a metal top plate (26) separated from a silicon substrate (12) by a thermally-grown, silicon dioxide dielectric (16) layer. An additional silicon plate (36) can be included intermediate to the metal top plate (26) and the silicon substrate (12) for multiple power supply devices. The silicon substrate (12) is electrically accessed through a metal contact pad (28) overlying a doped region (34) of the silicon substrate (12). The metal contact pad (28) is electrically isolated from the top plate (26) by an isolation structure (30). The bypass capacitor (10) is designed to be attached directly to the top surface of a semiconductor device (18), which enables the bypass capacitor (10) to be interconnected to the semiconductor device (18) by a plurality of bonding wires (25) having a minimal length. Because the capacitor dielectric (16) is formed as a very thin layer by the thermal oxidation of silicon, the self-inductance of bypass capacitor (10) is minimized.
    Type: Grant
    Filed: January 10, 1994
    Date of Patent: December 27, 1994
    Assignee: Motorola Inc.
    Inventors: Aubrey K. Sparkman, Kevin A. Calhoun, Jonathan C. Dahm, Joseph M. Haas, Jr., Rolando J. Osorio
  • Patent number: 5339212
    Abstract: The invention provides a decoupling capacitor which utilizes a plurality of tungsten studs and metal interconnects to maximize the surface area of the capacitor, thereby increasing the capacitance. The metal interconnects only partially overlap the tungsten studs, forming the first plate of the capacitor, so that the tops of the studs as well as the sides and tops of the interconnects provide the increased surface area. A method of forming the capacitors, and a method of increasing capacitance of a capacitor, are also provided.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: August 16, 1994
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Geffken, Lawrence J. Dunlop
  • Patent number: 5214300
    Abstract: A monolithic semiconductor integrated circuit-ferroelectric device is disclosed together with the method of manufacturing same. The ferroelectric device preferably consists of a layer of stable ferroelectric potassium nitrate disposed between electrical contacts positioned on opposite surfaces of the ferroelectric layer. The ferroelectric layer has a thickness of less than 110 microns, and preferably falling within a range of from 100 Angstrom units to 25,000 Angstrom units. The process of manufacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: May 25, 1993
    Assignee: Ramtron Corporation
    Inventors: George A. Rohrer, Larry McMillan
  • Patent number: 5122924
    Abstract: An electronic component includes a plurality of current path pairs which are arranged on the same circle. Currents flow through first current paths forming respective current path pairs in first directions, and currents flow through second current paths in second directions opposite to the first directions. The first current paths and the second current paths are arranged alternately. Therefore, magnetic fields generated by the currents in the first directions and magnetic fields generated by the currents in the second directions are canceled by each other, whereby residual inductance becomes small. In the case where the electronic component is a cable, the current paths are conductors buried in an insulation member. In the case where the electronic component is a capacitor, at least one of the current paths forming the pair is a capacitor unit.
    Type: Grant
    Filed: December 5, 1989
    Date of Patent: June 16, 1992
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Mitsunao Okumura
  • Patent number: 5117206
    Abstract: A variable capacitance circuit comprising a capacitor array, associated switching elements and transient impedance varying circuits. The capacitor array comprises a plurality of capacitor elements connected to a common node coupled to a crystal oscillator in a crystal oscillator portion and each capacitor element includes a connected switching element that controls activation of selected capacitor elements that are selectively placed in operation as load capacitance with the crystal oscillator to change and adjust its frequency. Further, circuits are provided in a temperature compensation portion to selectively control the activation of the switching elements based upon decoded compensating values provided in memory, such as based upon sensed oscillator temperature conditions.
    Type: Grant
    Filed: December 4, 1990
    Date of Patent: May 26, 1992
    Assignee: Seiko Epson Corporation
    Inventor: Yoichi Imamura