Stacked Patents (Class 361/735)
  • Patent number: 6958531
    Abstract: A multi-substrate, microsystem package and a method for assembling same including a high-density flexible connector array are disclosed for use in compact and multi-substrate packages containing circuits, sensors, and actuators in a re-workable and modular approach. The package is designed as a cube with highly flexible connectors providing electrical and fluidic connections between the substrates. The cables are integrated in the inside walls of the cube and make pressure contacts to the pads on stacked substrates. The cables are designed to be flexible and capable of being manipulated so that individual dice can be inserted to populate the cube. Several material candidates for the cables, including polymers such as Parylene, and metal such as gold, are provided.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: October 25, 2005
    Assignee: The Regents of the University of Michigan
    Inventors: Asli B. Ucok, Khalil Najafi, Joseph M. Giachino
  • Patent number: 6951982
    Abstract: Various aspects of the invention provide microelectronic component assemblies, memory modules, computer systems, and methods of assembling microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a non-leaded first package, a second package, and a plurality of electrical junctions. The first package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces. The second package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces of a number of leads. Each of the junctions couples one of the contacts to the contact surface of one of the leads. The electrical junctions may also physically support the packages with their respective confronting surfaces juxtaposed with but spaced from one another, defining a peripherally open fluid passage and enhancing thermal performance.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: October 4, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Lim Thiam Chye, Setho Sing Fee, Eric Tan Swee Seng
  • Patent number: 6944031
    Abstract: A printed circuit board structure for a scope unit of an electronic endoscope system, which is provided with a first printed circuit board formed with a first circuit section, and a second printed circuit board formed with a second circuit section. The first printed circuit board is piled on the second printed circuit board. The second printed circuit board having an area covered with the first printed circuit board and at least one area which is not covered with the first circuit board. The at least one area is used for electrically connecting the second circuit section with an electrical unit other than the second circuit section.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: September 13, 2005
    Assignee: PENTAX Corporation
    Inventor: Satoshi Takami
  • Patent number: 6922341
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: July 26, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Tim J. Bales
  • Patent number: 6914324
    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: July 5, 2005
    Assignee: Staktek Group L.P.
    Inventors: Russell Rapport, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr., Jeff Buchle
  • Patent number: 6914786
    Abstract: The present invention is directed to a converter device. In a first aspect of the present invention, a converter device includes a board having a first side and a second side. The first side includes a first set of contacts suitable for electrically contacting an integrated circuit having a first configuration. The second side includes a second set of contacts suitable for electrically contacting a circuit board having a second configuration. The second set of contacts is communicatively coupled to the first set of contacts.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: July 5, 2005
    Assignee: LSI Logic Corporation
    Inventors: Erik Paulsen, William Page, Erich S. Otto
  • Patent number: 6910637
    Abstract: A stacked small memory card includes an upper memory card and a lower memory card, the upper memory card and the lower memory card respectively formed a first heat sink and a second heat sink, the first heat sink and the second heat sink are stacked together, so that, the heat of the upper memory card and the lower memory card may be dispersed via the first heat sink and the second heat sink. Thus, the stacked small memory card of present invention having high function of disperses heat to promote its durability and lifetime effectively.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: June 28, 2005
    Assignee: Kingpak Technologies Inc.
    Inventors: Jackson Hsieh, Jichen Wu, Abnet Chen
  • Patent number: 6900540
    Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: May 31, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, David Overhauser, Akira Fujimura
  • Patent number: 6870271
    Abstract: One embodiment of the present invention provides an integrated circuit assembly module, including a first semiconductor die and a second semiconductor die, each semiconductor die with an active face upon which active circuitry and signal pads reside and a back face opposite the active face. The first and second semiconductor dies are positioned face-to-face within the assembly module so that signal pads on the first semiconductor die overlap with signal pads on the second semiconductor die, thereby facilitating capacitive communication between the first and second semiconductor dies. Additionally, the first and second semiconductor dies are pressed together between a first substrate and a second substrate so that a front side of the first substrate is in contact with the back face of the first semiconductor die and a front side of the second substrate is in contact with the back face of the second semiconductor die.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: March 22, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Ivan E. Sutherland, Robert J. Drost, Gary R. Lauterbach, Howard L. Davidson
  • Patent number: 6867981
    Abstract: The invention is to set a resonance frequency to various resonance frequencies by cutting a signal line which connects a tuning capacitor for trimming and an antenna currently with a milling step making a hole for mounting an IC module.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: March 15, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaru Murohara
  • Patent number: 6862189
    Abstract: An electronic component including an element main body section for performing an electrical function and a terminal section for electrically connecting the element main body section to a conductive member of an external device, the electronic component comprises a pair of sections arranged above the terminal section and opposite to each other in a stacking direction of the electronic component and a distance between the sections corresponding to a maximum thickness of the electronic component.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuhito Higuchi
  • Patent number: 6859370
    Abstract: A board to board array type connector comprising an array type connector, an upper supporting cover, a lower supporting cover, a screw with a bolt and a screw nut; during application, the upper supporting cover is on the top of the upper PCB, the upper pressing area/point presses down on the top of the upper PCB, the lower supporting cover is on the bottom of the lower PCB, the lower pressing area/point presses up on the bottom of the lower PCB; the screw with bolt passes through all the through holes and is fastened with the screw nut on the end to assemble the whole set, the stress is distributed equilibrium to the upper and lower pressing area/point, the pressure is evenly over all the connection pins of the array type connector for better electrical conductivity.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: February 22, 2005
    Assignee: Speed Tech Corp.
    Inventors: Chien-Yu Hsu, Yen-Jang Liao, Li-Sen Chen
  • Patent number: 6846693
    Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: January 25, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiko Kawase, Hidenobu Kimoto
  • Patent number: 6839238
    Abstract: The invention relates to a module for measuring purposes comprising an electrical or electronic circuit, which has at least one power supply connection and at least one data line connection for connecting, in the manner of a bus, to at least one other module of the same type that is also used for measuring purposes. According to the invention, the electronic circuit (80) is arranged inside a housing, the housing has a first contact surface (90) and a second contact surface (91), and the first contact surface (90) is joined to the second contact surface (91) of the other module (22, 32, 42) in a manner that permits it to be mechanically detached. The at least one power supply connection has a power supply contact (84a, 85a) in the first contact surface (90) and has a corresponding power supply contact (84b, 85b) in the second contact surface (91).
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: January 4, 2005
    Assignee: Testo AG
    Inventors: Andreas Derr, Manfred Streicher, Peter Schulz
  • Patent number: 6829147
    Abstract: The invention is related to the computer science and may be used in the design of miniature high-performance computing systems. The purpose of the invention is to increase the IC stuffing density and to reduce the microelectronic module assembly effort. The multilayered hybrid electronic module contains a backplane with multilayer wiring with ICs and sockets installed. A socket body is a box of elastic dielectric material, whose vertical walls have vertical metallized contact slots connected to the contact pads on the outer bottom surface of the socket. IC packages to be installed in the sockets have a rigid peripheral frame with cylindrical leads on the perimeter. The leads are parallel to the base of the package and lie in the same plane. Dimensions and shape of the IC package correspond to those of the socket cavity. Dimensions and positions of the IC leads correspond to those of the contact slots.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: December 7, 2004
    Assignee: Sÿnergestic Computing Systems ApS
    Inventor: Nikolai Victorovich Streltsov
  • Patent number: 6817892
    Abstract: As a structure for electrically connecting conductors of a flat cable (flat wire member) with a circuit board, an end of the flat cable is split into split pieces, and connectors (second connectors) are mounted at the ends of the respective split pieces. A connector (first connector) provided with two connecting portions for the connectors are mounted on the circuit board. When the respective connectors mounted on the flat cable are connected with the connector, the respective conductors of the split pieces are brought into contact with terminals accommodated in the connector. The flat cable or the flat wire member can be easily and securely connected.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: November 16, 2004
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Yoshito Sakai, Hiroki Hirai, Kenji Okamura
  • Patent number: 6798667
    Abstract: A solder ball collapse control apparatus and method thereof includes a plurality of first solder members, pieces of solder material in a shape capable of being used to properly create a solder joint. The first solder members have a first solder dimension and a first melting temperature and are disposed on a carrier substrate, wherein the first solder members include any piece of material capable of being disposed using a solder dispensing machine. The apparatus and method further includes a plurality of second members having a second dimension and a second melting temperature, disposed on the carrier substrate in relation to the plurality of first solder members. The second members include any piece of material capable of being disposed using the solder dispensing machine, wherein the first solder member dimension is greater than the second member dimension and the second melting temperature is greater than the first melting temperature.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: September 28, 2004
    Assignee: ATI Technologies, Inc.
    Inventor: Vincent K. Chan
  • Patent number: 6795318
    Abstract: A portable modular electronic system comprises a controller module, at least one memory module; and at least one application module that are mechanically connectable and disconnectable with respect to each other and include mating electrical connectors for communicating electrical signals between modules when the modules are mechanically connected.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 21, 2004
    Assignee: Hewlett-Packard Development Company, LP.
    Inventors: William R. Haas, Kirk S. Tecu
  • Patent number: 6788535
    Abstract: An outdoor telecommunications cabinet comprising an electronic compartment adapted to contain heat-generating electrical equipment, having a main electronic compartment including a rear wall panel and two clamshell doors, a floor panel and a cover panel, including access areas and an equipment storage area, the main compartment being adapted to contain heat-generating electrical equipment, at least one rack inside said main electronic compartment for electronic equipment, a base assembly supporting the said electronic compartment, having a width and depth similar to said main electronic compartment capable of being anchored to a base plate or pad, a ventilated sub-compartment in the base assembly containing an environmental cooling system, a pair of clamshell doors, movable between an open position permitting access to both front and back sides of said electrical equipment and a closed position in which the doors maintain a substantially closed environment in the electronic compartment, a cable entry port, ty
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: September 7, 2004
    Assignee: 3M Innovative Properties Company
    Inventors: Charles H. Dodgen, Sergio A. Alarcon, Jerome A. Pratt, Mark C. Woods
  • Patent number: 6781844
    Abstract: A modular computer system mechanical interconnection includes a primary chassis having a first opening and a secondary chassis attached to the primary chassis and having a second opening, wherein the first opening and the second opening are generally aligned. The apparatus further includes a backplate covering the aligned first opening and second opening.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: August 24, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Jimmy Clidaras, Kenneth Kitlas
  • Patent number: 6778404
    Abstract: A stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to a pre-formed packages which have alignment features to allow for the stacking of the ball grid arrays. The alignment features are used to align and orient each package with respect to an adjacent package, substrate or printed circuit board. The alignment features also support the weight of the adjacent package during solder ball reflow to maintain stack height and parallelism between packages. Each memory device is serially connected to the adjacent memory device through the vias and solder balls on each package.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: August 17, 2004
    Inventors: Todd O. Bolken, Cary J. Baerlocher, Chad A. Cobbley, David J. Corisis
  • Patent number: 6775149
    Abstract: A multichip mounted structure has a substrate 11 provided with substrate-side terminals 16a and 16b and a plurality of IC chips 12a and 12b provided with bumps 14a and 14b, respectively, so that the substrate-side terminals 16a and 16b are conductively connected with the bumps 14a and 14b, respectively. The bumps 14a and 14b provided on the plurality of IC chips 12a and 12b, respectively, form pairs of terminal lines opposing each other. Since the plurality of IC chips 12a and 12b are mounted on the substrate 11 so that central lines L1 and L2 between the pairs of terminal lines which are individually formed approximately coincide with each other, it is not necessary to transport a position of a compressive head, and one piece of ACF 19 can be commonly used.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: August 10, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Kenji Uchiyama
  • Patent number: 6760218
    Abstract: The present invention is to provide a network device having a parallelepiped housing comprising a plurality of slots on two opposite sides and two opposite edges at each of an underside and a top and a plurality of pads each fastened the slots to form a short distance between a supporting surface and the underside of the housing by the projected pad. Also, housings of the same type of network devices can be stacked or horizontally coupled together by fastening the pads in the slots to form a gap between two stacked housings by the coupled pads for dissipating heat of the housings therefrom.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: July 6, 2004
    Assignee: D-Link Corporation
    Inventor: Shu-Chu Fan
  • Patent number: 6759307
    Abstract: The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a stacked semiconductor device package. The methods and apparatus include providing a first semiconductor device with an adhesive flow control dam located on an upper surface thereof. The dam is positioned between electrical contacts and a substrate attach site on the upper surface of the first semiconductor device. The dam is rendered of a sufficient height and shape to block applied adhesive from flowing over the electrical contacts of the first semiconductor device when a second substrate is mounted onto the upper surface of the first semiconductor device. The semiconductor device package may be encapsulated with the dam in place or with the dam removed. The adhesive flow control dam thus protects the electrical contacts of the first semiconductor device from contamination by excess adhesive, which can result in unusable electrical contacts.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: July 6, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Jicheng Yang
  • Publication number: 20040125574
    Abstract: Provided is a multi-chip semiconductor package incorporating stacked semiconductor package structures with each package structure including a substrate, a semiconductor chip mounted on the substrate, an enclosure body formed across the entire surface of the substrate where the semiconductor chip is mounted, a plurality of conductive studs extending through the enclosure body outside the periphery of the semiconductor chip and one or more conductive members provided below the substrate and in contact with the conductive studs. During assembly of the multi-chip semiconductor package, the conductive member of an upper semiconductor package structure provides electrical contact to corresponding conductive studs on a lower semiconductor package structure.
    Type: Application
    Filed: October 9, 2003
    Publication date: July 1, 2004
    Inventor: Ki-Myung Yoon
  • Patent number: 6751096
    Abstract: A modular electronic housing system is provided, having a plurality of modules. Each module includes a plurality of bolt holes for attachment of various components and other modules, and a gasket interface for placement of gaskets for electromagnetic shielding or drip proof protection. The electronic housing further includes a removable end panel for convenient access to the contents of the electronic housing, and a support system is provided for isolation—of contents from vibration or shock. The electronic housing is designed to facilitate integration inside submarines or through small hatches. Cabling and wiring do not need to be removed during integration of the electronic housing.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: June 15, 2004
    Assignee: 901D LLC
    Inventor: Jean-Claude Aldon
  • Patent number: 6747871
    Abstract: The present invention relates to an electronic assembly and, more particularly, to a computing assembly comprising a computing platform and an external power supply. The computing platform has an internal cooling mechanism which generates an externally directed flow of air. The external power supply is disposed relative to the cooling mechanism such that the outwardly directed flow of air, or at least a portion thereof, passes through the power supply and exerts a cooling influence on the external power supply.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: June 8, 2004
    Assignee: Hewlett-Packard Development Copany, L.P.
    Inventor: Jean-Marie Jeudi
  • Patent number: 6735968
    Abstract: A refrigerating apparatus comprises: a first substrate, on one surface of which an active converter and an inverter are mounted, and on a reverse surface of which a radiation fin is closely fixed; a second substrate, on which a microcomputer, a current detecting mechanism, and a terminal block are mounted; a resin casing covering sides of the first and second substrates and provided with a step permitting the terminal block to be arranged thereon; and a third substrate, on which an interface connector and a photo-coupler are mounted. The first substrate, the second substrate, and the third substrate are layered in this order on a bottom surface of the casing. Gel is filled up to a power semiconductor surface of the first substrate, and a resin is filled up to an upper surface of the second substrate.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: May 18, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiaki Kurita, Kuniaki Takatuka, Tatsuo Ando, Noriaki Yamada, Satoshi Furusawa
  • Patent number: 6724630
    Abstract: In order to progress a mounting consistency of electric devices on a substrate, an electronic device assembly, comprising a lower electronic device having electrodes in a surface opposed to the substrate and an upper electronic device having a plurality of the leads each extending from the side surface of own package toward the substrate.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: April 20, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Nobuhiro Kato, Masataka Kawai
  • Patent number: 6716672
    Abstract: A method of interconnection in three dimensions and to an electronic device obtained by the method. To increase the compactness of integrated circuit modules, the method stacks and adhesively bonds packages containing a chip connected to output leads by connection conductors inside each package, cuts through the packages near the chips to form a block, the conductors being flush with the faces of the block, and makes the connections on the faces of the block by metalizing and then etching the outlines of the connections. The method also applies to the matching of packages in the replacement of obsolete circuits.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: April 6, 2004
    Assignee: 3D Plus
    Inventor: Christian Val
  • Patent number: 6714418
    Abstract: An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: March 30, 2004
    Assignee: Infineon Technologies AG
    Inventors: Gerd Frankowsky, Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez
  • Patent number: 6710246
    Abstract: A package, a method of making and a method of assembly of packages for semiconductor chips are disclosed. The package includes a die attach pad on which a semiconductor die is mounted. A lead is electrically connected to the semiconductor die which is encapsulated in packaging material. The lead is exposed at opposed sides of the package. Exposing the lead on both sides of the package allows the package to be stacked or assembled so that the leads of adjacent pairs of packages are in electrical contact. Making the semiconductor packages includes forming a piece of electrically conductive material into a die attach pad and at least one lead associated with the die attach pad. A semiconductor die is mounted on the die attach pad and an electrical connection is made between the semiconductor die and the lead. The package is formed by encapsulation with the lead exposed on opposite sides of the package.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: March 23, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Joseph O. Smith
  • Patent number: 6704248
    Abstract: The present invention is directed towards a multilayered circuit module and a method for constructing such a module, wherein the module has passive components such as capacitors, inductors, transformers distributed into a ceramic substrate. This module provides an optimally close packing density of these components without wasting large areas of unused substrate. The module of the present invention weaves capacitors, inductors, and transformers into the substrate without the use of printed circuit boards and eliminating discrete components. The substrate of the module becomes a functional component itself, rather than just a block receptacle for discrete components. The module of the present invention provides a very densely packed power supply with good heat conduction properties and which is also less costly to build than HDI modules.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: March 9, 2004
    Assignee: Lockheed Martin Corporation
    Inventor: Shabriar Shey Sabripour
  • Patent number: 6697260
    Abstract: An integrated high-speed package comprising a package housing having a housing lip and connector having a center pin abutting along a bottom surface of the housing lip. For signal registration of a first substrate to the signal lead, the substrate is “floated” up to the housing lip, which provides an alignment reference to ensure that the top surface of the first substrate is aligned and in direct registration with the signal lead. In another embodiment, the center pin to substrate registration is provided at a top surface of a housing base. The housing base preferably comprises a first portion of a first height and a second portion of a second height. Accordingly, the housing base can accommodate substrates of different thickness while allowing a top surface of the first and a second substrate to be coplanar to facilitate signal registration there between.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: February 24, 2004
    Assignee: Big Bear Networks, Inc.
    Inventors: Yu Ju Chen, Thomas J. Sleboda, Michael Zhong Xuan Wong, Hui Wu
  • Patent number: 6696768
    Abstract: An arrangement of equipment for a motor vehicle is designed to perform a variable number of functions such as to assist and/or enhance driving. The arrangement comprises at least one plurality of electronic components based equipment elements (1). According to the invention, remote processing members which are common to the entire set of equipment elements are provided. The electronic components have specific functions according to each equipment element and act as additional processing members, whereby it is possible for each equipment element to carry out one or several given functions of the arrangement by combining them with the common processing members. The invention also relate to a dashboard for a motor vehicle which is provided with the arrangement of equipment.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: February 24, 2004
    Assignees: Valeo, Visteon Systems Interieurs
    Inventors: Didier Barat, Andrew Nash
  • Patent number: 6690582
    Abstract: In an electronic control unit mounting structure, electronic control units are mounted on a junction block, and printed circuit boards 4a and 4b of the electronic control units, each having a connector 41a, 41b of a through construction mounted thereon, are superposed in such a posture that these connectors 41a and 41b are disposed in registry with each other in an upward-downward direction, and connection terminals 31 of the junction block are inserted in the connectors 41a and 41b.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: February 10, 2004
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Yoshitaka Sumida
  • Patent number: 6690580
    Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: February 10, 2004
    Assignees: AMD, Inc., Motorola, Inc.
    Inventors: Cindy K. Goldberg, John Iacoponi
  • Patent number: 6690088
    Abstract: A stack of integrated circuits in thin small outline packages (TSOP's) is constructed with an air space in between adjacent packages. The TSOP's have a plurality of connection terminals extending therefrom. A lead frame is disposed adjacent to the packages, positioned medially of the air space and having a plurality of connection terminals in registration with and in electric contact with the plurality of TSOP connection terminals. The TSOP's have a chip select terminal and several unused terminals. The lead frame has a strain-relieved conductor extending between the chip select terminal on a TSOP higher in the stack to the adjacent TSOP lower in the stack. Moreover, TSOP locating surfaces are included on the lead frame in the finished stack.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: February 10, 2004
    Inventor: Donald M. MacIntyre
  • Patent number: 6682955
    Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: January 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Chad A. Cobbley, Timothy L. Jackson
  • Patent number: 6678140
    Abstract: Improved modular transient voltage surge suppressor apparatus that provide a simple structure for coupling multiple modules are disclosed. In general, such apparatus includes a substrate; a mounting post coupled to and extending substantially perpendicular to the substrate; and a transient voltage surge suppression module, wherein the module includes a non-conductive housing having a surge suppression circuit contained therein, and mounting means coupled to the non-conductive housing, the mounting means comprising a bore therethrough for slidably mounting the transient voltage surge suppression module on the mounting post, the bore having an internal profile corresponding to an external profile of the mounting post.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: January 13, 2004
    Assignee: Current Technology, Inc.
    Inventors: Asif Y. Jakwani, Getzel Gonzalez Garcia, Fyodor M. Shterenberg, Simon Hoi-Keung Yu
  • Patent number: 6678167
    Abstract: The specification describes a multi-chip IC package in which IC chips are flip-chip bonded to both sides of a flexible substrate. The upper (or lower) surface of the flexible substrate is bonded to a rigid support substrate with openings in the support substrate to accommodate the IC chips bonded to the upper (or lower) surface of the flexible substrate. In a preferred embodiment a plurality of IC memory chips are mounted on one side of the flexible substrate and one or more logic chips to the other. A very thin flexible substrate is used to optimize the length of through hole interconnections between the memory and logic devices. If logic chips are flip-chip mounted in the cavity formed by the openings, a heat sink plate can be used to both cap the cavity and make effective thermal contact the backside of the logic chips.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: January 13, 2004
    Assignee: Agere Systems INC
    Inventors: Yinon Degani, Thomas Dixon Dudderar, King Lien Tai
  • Patent number: 6674646
    Abstract: An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: January 6, 2004
    Assignee: Skyworks Solutions, Inc.
    Inventors: Khosrow Golshan, Siamak Fazelpour, Hassan S. Hashemi
  • Patent number: 6667883
    Abstract: The present invention provides for cooling a plurality of racked electronic devices having a first electronic device having at least one cooling vent at a first end and a plurality of cooling holes at a top, each of the cooling vents having a cooling fan, means for flowing air through the cooling vent, means for outputting the air flow through a plurality of cooling holes on the top of the first electronic device. The present invention further provides for a second electronic device having a plurality of heat sink fins on the bottom. The bottom of the second electronic device coupled to the top of said first electronic device, means for aligning the plurality of cooling holes under the plurality of heat sink fins, and means for outputting the air through an output of the heat sink fins.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 23, 2003
    Assignee: Proxim Corporation
    Inventors: Craig Solis, Peter Smidth
  • Patent number: 6650539
    Abstract: A modular backup power housing consists of at least one module and a base. Additional modules may be stacked to accommodate a larger bank of power cells. Each module has a cuboid frame, multiple top rails and multiple bottom tracks. The top rails and the bottom tracks are attached to top and bottom surfaces of the cuboid frame respectively and mate with the top rails and bottom tracks of adjacent modules or the base. By virtue of the interlocking top rails and bottom tracks, the total height of the modular backup power housing is less than a conventional housing, and the strength and stability of the modular backup power housing is improved.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: November 18, 2003
    Assignee: Handsome Electronics Ltd.
    Inventors: Hsin-An Lin, Kuo-Hsien Tsai
  • Patent number: 6636421
    Abstract: A method for datum sharing between modular computer system components, includes determining a position and orientation of a motherboard, defining at least one datum feature in a primary chassis describing the position and orientation of the motherboard, and defining at least one datum feature in a secondary chassis corresponding to the at least one datum feature in the primary chassis. An apparatus for datum sharing includes at least one datum feature of the primary chassis, at least one datum feature of the motherboard, wherein a location of the at least one datum feature of the primary chassis is based upon the at least one datum feature of the motherboard, and at least one datum feature of the secondary chassis, wherein a location of the at least one datum feature of the secondary chassis is based upon the location of the at least one datum feature of the primary chassis.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: October 21, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Jimmy Clidaras, Matthew Schutte
  • Patent number: 6630727
    Abstract: A modularly expandable semiconductor component includes at least one carrier layer, at least one intermediate layer, at least one coverlayer, at least one semiconductor chip, external contacts and a conductor configuration. The intermediate layer is provided with at least one opening, into which the at least one semiconductor chip is inserted. The carrier layer, the intermediate layer and the coverlayer are connected one above another and form a submodule. If a plurality of submodules are installed above one another, a semiconductor component is provided in which the semiconductor chips are located in several mutually overlying planes. The semiconductor chips can be interconnected. A method for producing a semiconductor component is also provided.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: October 7, 2003
    Assignee: Infineon Technologies AG
    Inventors: Günter Tutsch, Thomas Münch
  • Patent number: 6625000
    Abstract: Improved modular transient voltage surge suppressor apparatus are disclosed that equalize transient current sharing between multiple modules. In general, such apparatus includes first and second transient voltage surge suppression modules, each module having a non-conductive housing with a surge suppression circuit contained therein, and first and second electrically-conductive buses mechanically coupled to the non-conductive housing and electrically coupled to first and second terminals of the surge suppression circuit, respectively. A first bus coupler couples the first electrically-conductive buses of the first and second transient voltage surge suppression modules and a second bus coupler couples the second electrically-conductive buses of the first and second transient voltage surge suppression modules, whereby the surge suppression circuits in each of the first and second modules are electrically coupled in parallel.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: September 23, 2003
    Assignee: Current Technology, Inc.
    Inventors: Asif Y. Jakwani, Paul Jeffries, Fyodor M. Shterenberg, Getzel Gonzalez Garcia
  • Patent number: 6617693
    Abstract: A semiconductor device has a first semiconductor chip and a second semiconductor chip superposed on and bonded to the surface of the first semiconductor chip. In the region on the first semiconductor chip where the second semiconductor chip is bonded thereto, connection pads are arranged in positions that fit a plurality of predetermined types of semiconductor chips. On the second semiconductor chip, connection pads are arranged in positions that fit the connection pads arranged on the first semiconductor chip.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: September 9, 2003
    Assignee: Rohm Co., Ltd.
    Inventors: Junichi Hikita, Hiroo Mochida
  • Patent number: 6603072
    Abstract: In a leadframe type of semiconductor package, the internal electrical interconnectability of and signal routing between multiple dies laminated in a stack with the die paddle of the leadframe is substantially enhanced by laminating an “interposer” in the stack. The interposer comprises a dielectric layer and a metallic layer patterned to include wire bonding pads arrayed around the periphery of a surface thereof, and circuit traces interconnecting selected ones of the wire bonding pads in a single plane across the horizontal span of the interposer. In packages having multiple dies and relatively few leads, the bonding pads and circuit traces can be flexibly arranged on the interposer by the package designer to substantially increase the number and routings of internal electrical interconnections otherwise possible between the dies and between the dies and the leads of the package.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: August 5, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Donald C. Foster, David A. Zoba
  • Patent number: 6600659
    Abstract: A new physical design for electronic devices (100) comprises a multi-layer stacked assembly (104-110) of a plurality of pan-shaped conductive units that form the layers of the assembly. Each unit is preferably formed from a single sheet of metal into which electronic components, such as an antenna array (208) or a filter array (314) of a transceiver, have been stamped, cut, or etched, and which is then bent around its periphery to form a pan shape. The pans are oriented to face the same direction, are stacked one on top of another, and are fixedly attached to each other by weld, solder, or adhesive. The electrical components defined by the different units are electrically interconnected in a connectorless manner, preferably by flanges (122, 124) formed in the same sheets of metal as the units themselves and extending between the units. Adjacent units in the stack define electromagnetically isolated chambers, e.g., for the filter array. Some layers perform double duty, e.g.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: July 29, 2003
    Assignee: Avaya Technology Corp.
    Inventors: Ron Barnett, Charles Joseph Buondelmonte, Ilya Alexander Korisch, Louis Thomas Manzione, Richard F Schwartz, Thaddeus Wojcik, Hui Wu