Abstract: An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 50 is accommodated in a core 11, and a first and a second buildup layers 12 and 13 are formed on the upper and lower sides, respectively, of the capacitor 50.

Abstract: A circuit board assembly includes two external circuit boards, at least one electrical connector, at least one electronic component, and at least one hollow substrate. Each external circuit board includes an external electromagnetic shielding layer, a circuit layer and a dielectric layer. In each external circuit board, the dielectric layer is located between the external electromagnetic shielding layer and the circuit layer. The electrical connector is connected between the circuit layers located between the external electromagnetic shielding layers. The electronic component is disposed between the external circuit boards and connected with one of the circuit layers. The hollow substrate with plural openings is disposed between the external circuit boards. The electronic component and the electrical connector are located in the openings. Both a thickness of the electronic component and a height of the electrical connector are smaller than or equal to a thickness of the hollow substrate.

Abstract: A wiring board including a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on one surface of the first substrate and including multiple interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including multiple conductive circuits for being connected to multiple semiconductor elements, and a filler filling the opening portion of the built-up layer such that the interposer is held in the opening portion of the built-up layer. The opening portion of the built-up layer has a tapered portion tapering toward the outermost surface of the built-up layer.

Abstract: The present invention provides a dual chip signal conversion device, comprising: a carrier, one side surface thereof being provided with at least a first contact and a second contact while the other side surface thereof being provided with at least a third contact and a fourth contact; a first chip disposed at one side surface of the carrier and electrically connected to the second and fourth contacts; a second chip disposed at one side surface of the carrier and electrically connected to the first chip; and an antenna disposed within the carrier and electrically connected to the second chip.

Abstract: A miniaturized wideband surface mount bias tee comprises a printed circuit board with a functioning first capacitor and a dummy second capacitor, and an inductor bonded atop the two capacitors. The capacitors, adhesive and solder are depositable by standard surface mount pick and place machinery. The inductor wires are bonded to one of the first capacitor bonding pads and to an inductor bonding pad. The circuit element bonding pads include portions bordering the pc board edges and are conductively connected to bonding pads on the bottom face of the pc board. Conductive thru-vias for the first capacitor bonding pads reduce parasitic inductance and extend the operating frequency range. A flat-topped insulating cap encloses the bias tee sides and top. The cap forms an air gap between the inductor and circuit elements and provides a surface for manipulating the bias tee with present-day assembly equipment.

Abstract: Provided is a circuit board including a resin base, and a resistance element formed above the resin base. The resistance element includes a resistance pattern including an electrode portion and an extending portion, and an electrode formed on the electrode portion of the resistance pattern and including a foot portion reduced in thickness toward the extending portion.

Abstract: A method for producing an arrangement of optoelectronic components (10) is specified, comprising the following steps: producing at least two fixing regions (2) on a first connection carrier (1); introducing solder material (3) into the fixing regions (2); applying a second connection carrier (4) to the fixing regions (2); and soldering the second connection carrier (4) onto the first connection carrier (1) with the solder material (3) in the fixing regions (2).

Abstract: An assembly carrying a radioisotope power source for attaching to a printed circuit board.

Abstract: A multi-layer PCB includes a plurality of insulating layers and a plurality of conductive pattern layers alternatively and repeatedly stacked; contact-hole formed in the insulating layers so as to allow electrical connection through the contact-holes; a first integrated circuit arranged in a first insulating layer as one of the insulating layers so as to be embedded in the multi-layer PCB, the first integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the first integrated circuit; and a second integrated circuit stacked on a lower surface of the first integrated circuit, the second integrated circuit having a plurality of connection bumps for electric connection on an upper surface of the second integrated circuit.

Abstract: A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

Abstract: A system has a circuit board, an integrated circuit being mounted on the circuit board by external contacts, and a cover irreversibly connected to the circuit board. The cover covers the external contacts so that external access to the external contacts is prohibited by the cover.

Abstract: Disclosed herein is a capacitor-embedded printed circuit board, including first to fourth layers forming a four-layer laminated structure; and one or more capacitors embedded through the second layer and the third layer among the first to fourth layers, wherein the respective capacitors embedded through the second layer and the third layer are electrically connected to one or more power terminals of active elements and ground terminals, and wherein at the second or third layer, power terminal wirings are connected to thereby allow the capacitors to form a mutual parallel connection structure, and thus, in embedding capacitors in a laminated structured board having a plurality of layers, a capacitor-embedded printed circuit board capable of reducing the impedance in the entire frequency region and having a high capacitance and a low equivalent series inductance can be realized by effectively connecting capacitors embedded inside the printed circuit board in parallel with each other.

Abstract: A card connector having a housing with a receiving slot and connector pins are provided. An expansion card having docking well regions, contact pads, and backup contact pads is inserted in the receiving slot. The connector pins are connected to the docking well regions on the expansion card. The expansion card is coupled to a servomechanical device that can slide the expansion card to connect the connector pins with the contact pads. Connector pins and contact pads are coated with an interface material that is subject to wearing. Worn interface material can cause weak electrical connections between connector pins and contact pads. Thus, a card connector with a servomechanical device is provided to slide an expansion card within a receiving slot of the card connector for an improved electrical connection between connector pins and contact pads.

Abstract: A suspension board with circuit includes a conductive pattern. The conductive pattern includes a first terminal provided on the front face of the suspension board with circuit and electrically connected with a magnetic head; and a second terminal provided on the back face of the suspension board with circuit and electrically connected with an electronic device.

Abstract: On a multilayer wiring board which has a plurality of wiring pattern stacked in sequence separately from one another, insulating members each positioned between the plurality of wiring patterns, and interlayer connection bodies electrically connecting the plurality of wiring patterns and in which a voltage conversion IC is built in, a first capacitor, a second capacitor, and an inductor are mounted, the other of electrode portions in the first capacitor or one of electrode portions in the second capacitor is positioned between an input section of the first capacitor and the inductor, and the other of the electrode portions or the one of the electrode portions is electrically set to ground.

Abstract: A compact driver device for driving an LED lighting device is provided. The driver device includes a substrate, power capacitor that provides LED driving current to drive the LED lighting device, and a power resistor. Advantageously, the power capacitor and the power resistor are attached to the substrate and are solderlessly connected to each other to provide a very compact driver device.

Abstract: A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.

Abstract: A component for mounting on a PCB, intended to support an electronics component, with an extension in the longitudinal, lateral and vertical directions. The component has a first and a second main surface, the second main surface being intended for mounting on the PCB. The component is made in a non conducting material, with a first layer of conducting material arranged on its first main surface, the conducting layer being connected to a conducting layer on the second main surface of the component by electrically conducting means. The component's extension in the vertical direction is smaller than its extension in either the longitudinal or lateral direction.

Abstract: A high-voltage power supply device includes a circuit board having a piezoelectric transformer; a frequency-controlled oscillator for generating a frequency signal that drives the piezoelectric transformer in accordance with a control signal; a switching element connected to a primary side of the piezoelectric transformer for performing a switching operation in accordance with the frequency signal; a capacitor and inductor forming a parallel resonance circuit for performing a resonating operation owing to switching by the switching element; and a capacitance element connected across ground and the power-supply side of the inductor. The capacitance element and the inductor are arranged on the circuit board in such a manner that when the circuit board undergoes solder-mounting, the capacitance element and the inductor are immersed in a solder bath before the piezoelectric transformer.

Abstract: An improved MEMS transducer apparatus and method is provided. The apparatus includes a movable base structure having a base surface region. An anchor structure is disposed within a substantially circular portion of the surface region typically at or near the center of the surface region. A spring structure is coupled to the anchor structure and at least one portion of the base surface region. A capacitor, having a fixed capacitor element and a movable capacitor element, are disposed near the base surface region. The fixed capacitor element can be coupled to the anchor structure and the movable capacitor element can be spatially disposed on a portion of the base surface region near the anchor structure.

Abstract: A package structure having an embedded electronic element includes: a substrate having two opposite surfaces and a cavity penetrating the two opposite surfaces; at least a metal layer disposed on the sidewall of the cavity and extending to the surfaces of the substrate; an electronic element disposed in the cavity and having a plurality of electrode pads disposed on side surfaces thereof; and a solder material electrically connecting the electrode pads of the electronic element and the metal layer, thereby effectively alleviating the problems of alignment difficulty and high fabrication cost as encountered in the prior art.

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract: A component assembly that can be easily built in a main substrate with high accuracy is formed such that a glass transition temperature of a built-in-component layer of an assembly substrate in which multiple capacitors are embedded is higher than a glass transition temperature of a built-in-component layer of a built-in-component substrate. Thus, thermal deformation of the component assembly is prevented when the built-in-component substrate in which the component assembly is built is heated during reflow, for example. The component assembly can thus be highly accurately built in the built-in-component substrate. Moreover, when the component assembly in which the multiple capacitors are embedded is built in the built-in-component substrate, electrode pads of the component assembly in which the multiple capacitors are embedded can be electrically connected to wiring layers of the built-in-component substrate by soldering despite the variation in height among the capacitors.

Abstract: A first insulated planar metallic surface is formed under a surface of a substrate which is orientated a first way to an edge of the substrate. A Faraday shield is formed when a second insulated planar metallic surface is juxtaposed to and segregates the first insulated planar metallic surface from the remained of the substrate. The first way can be parallel or perpendicular forming either an edge or surface Coulomb island, respectively. Both planar surfaces can be charged either by mechanical contact or induced charging, Fowler-Nordheim and ion implantation. A Coulomb force is generated between two charged Coulomb islands each located on a different substrate. In addition, these Coulomb islands can also be used as capacitors to transfer signals between the substrates. The Faraday shield can be used to increase the Coulomb force while the potential applied to the shield can alter the Coulomb force.

Abstract: A printed wiring board has a core base having an opening portion, an inductor component accommodated in the opening portion, and a filler resin filling gap between the component and a side wall of the opening portion. The component has a support layer, a first conductive pattern on the support, an interlayer insulation layer on the support and first pattern, a second conductive pattern on the insulation layer, and a via conductor in the insulation layer and connecting the first and second patterns, the insulation layer includes a magnetic layer and a resin layer covering the magnetic layer, the magnetic layer includes magnetic material and resin material and has a first hole, the insulation layer has a second hole penetrating through the resin layer such that the second hole passes through the first hole and extends to the first pattern, and the via conductor is formed in the second hole.

Abstract: An electronics module has a flexible substrate having conductors, an array of functional components on the substrate, the functional components arranged to contact at least one conductor, and perforations in the flexible substrate, the perforations arranged to increase stretchability of the flexible substrate, the conductor arranged around the perforation and the functional components arranged to one of reside between the perforations or partially cover the perforations. A method of manufacturing a flexible electronics module involves mounting at least two functional components onto a flexible substrate, forming electrical interconnects configured to provide connection between the two functional components, and perforating the flexible substrate with cuts configured to increase stretchability of the substrate.

Abstract: A circuit board having a cavity is provided. The circuit board includes a first core layer, a second core layer, and a central dielectric layer. The first core layer includes a core dielectric layer and a core circuit layer, wherein the core circuit layer is disposed on the core dielectric layer. The second core layer is disposed on the first core layer. The central dielectric layer is disposed between the first core layer and the second core layer. The cavity runs through the second core layer and the central dielectric layer and exposes a portion of the core circuit layer.

Abstract: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

Abstract: A solid state storage device includes a printed circuit board assembly, a memory arranged on the printed circuit board assembly, and a storage medium arranged on the printed circuit board assembly. The storage device further includes a processor arranged on the printed circuit board assembly, wherein the processor is coupled to the memory and to the storage medium via the printed circuit board assembly, and wherein the processor is configured to store data in the memory and the storage medium and to read data from the memory and the storage medium. The storage device further includes a removable power pack comprising a plurality of capacitors serially arranged in a housing, wherein the plurality of capacitors is detachably connected to the printed circuit board assembly to supply backup power to the processor, the memory, and the storage medium when the removable power pack is mounted in the solid state storage device.

Abstract: A method for laying out a printed circuit board for use in a gigabit-capable passive optical network includes the steps of providing a printed circuit board and laying out an analog circuit module, an analog-to-digital conversion module, a signal processing module, an optoelectronic transmitting and receiving module, and a power module on the printed circuit board. The printed circuit board has a first periphery and an opposing second periphery. The analog circuit module and the optoelectronic transmitting and receiving module are laid out at the first periphery of the printed circuit board. The power module is laid out at the second periphery of the printed circuit board. Electromagnectic wave generated by a power IC inserted in the power module does not interfere with data transmission taking place at the optoelectronic transmitting and receiving module. Furthermore, a printed circuit board for use with the method is proposed.

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract: An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and achieves better operating performance. In a preferred embodiment, the ratio of power supply pins to input/output (I/O) pins is in the range of approximately 1 to 24 to approximately 1 to 52. In this embodiment, the integrated circuit package comprises a substrate, an integrated circuit mounted on the substrate, a first decoupling capacitor mounted on the substrate, and a second decoupling capacitor formed in the integrated circuit. The package is formed by coupling a power supply pin to both the first and second capacitors by a low frequency path and a DC path, respectively, and the first and second capacitors are coupled by a high frequency path.

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.

Abstract: In a circuit module, a chip element is mounted on a mount electrode, with an outer electrode interposed therebetween. The chip element is arranged such that a cut surface thereof is oriented toward a side of a circuit module that is adjacent to the mount electrode. A gap that is observable from outside of the circuit module is provided between a bottom surface of a base of the chip element and a top surface of a circuit board.

Abstract: An improved MEMS transducer apparatus and method is provided. The apparatus has a movable base structure including an outer surface region and at least one portion removed to form at least one inner surface region. At least one intermediate anchor structure is disposed within the inner surface region. The apparatus includes an intermediate spring structure operably coupled to the central anchor structure, and at least one portion of the inner surface region. A capacitor element is disposed within the inner surface region.

Abstract: A multilayer printed wiring board includes a core substrate, a resin insulation layer laminated on the core substrate and a capacitor section coupled to the resin insulating layer. The capacitor section includes a first electrode including a first metal and configured to be charged by a negative charge, and a second electrode including a second metal and opposing the first electrode, the second electrode configured to be charged by a positive charge. A dielectric layer is interposed between the first electrode and second electrode, and an ionization tendency of the first metal is larger than and ionization tendency of the second metal.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract: A composite module is obtained which enables high-density mounting of components without increasing its size. A composite module includes a main substrate which is a multilayer circuit board, a sub-substrate mounted on a lower surface of the main substrate, a sealing layer arranged on the lower surface of the main substrate to cover the sub-substrate, the sealing layer defining a mount surface arranged to be mounted on a mount board, and terminal electrodes disposed on the mount surface. The terminal electrodes include at least one first terminal electrode drawn directly from the main substrate and at least one second terminal electrode drawn directly from the sub-substrate.

Abstract: A printed circuit board includes a first to a fifth connector pads, a first to an eighth coupling capacitor pads, a first to a tenth transmission lines, a first via and a second via, a first to a fourth sharing pads, and a voltage converting circuit. The printed circuit board is operable to selectively support different types of connectors.

Abstract: An integrated circuit board includes a bridging filtering capacitor, a bypass capacitor, a thermistor, and a varistor. The integrated circuit board further includes an electrolytic capacitor set having a plurality of electrolytic capacitors, which are arranged in parallel and adjacent to each other, and a mounting frame for grouping the electrolytic capacitors. The present invention uses the above elements to reduce the vertical height, the horizontal width, and the occupied area. Therefore, the overall dimension of the circuit board can be reduced to make the electronic devices smaller, especially for thin electronic devices such as LCD TVs and screens.

Abstract: According to one embodiment, an electronic apparatus includes a housing, a wiring pattern, a recess, a pad portion, and an electronic component. The wiring pattern is formed on an inner surface of the housing from an electrically conductive adhesive. The recess is in the inner surface of the housing. The pad portion is formed in the recess from the conductive adhesive and connected to an end portion of the wiring pattern. The electronic component includes a terminal which contacts the pad portion.

Abstract: In a circuit module, a chip element is mounted on a mount electrode, with an outer electrode interposed therebetween. The chip element is arranged such that a cut surface thereof is oriented toward a side of a circuit module that is adjacent to the mount electrode. A gap that is observable from outside of the circuit module is provided between a bottom surface of a base of the chip element and a top surface of a circuit board.

Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.

Abstract: An electronic circuit is obtained that has reduced EMI levels. The circuit includes an integrated circuit, which is a source of noise, a bypass capacitor, and a circuit substrate on which they are mounted. An electronic circuit one electrode terminal of the bypass capacitor and one connecting electrode of the integrated circuit are connected through a first wire interconnect formed in the circuit substrate, and, additionally, another electrode terminal of the bypass capacitor and another connecting electrode of the integrated circuit are connected through a second wire interconnect, and the gap between the first wire interconnect and the second wire interconnect is made smaller than either the gap between the one connecting electrode and the other connecting electrode on the integrated circuit or the gap between the one electrode terminal and the other electrode terminal of the bypass capacitor.

Abstract: A method for controlling an electronic device is provided. The electronic device includes a housing, a keypad, a first conductive surface, and a second conductive surface. The keypad is rotatable and includes buttons. The first conductive surface is attached to the bottom of the keypad, rotatable with the keypad, and includes first contact portions. The second conductive surface is fixed in the housing, arranged below the first conductive surface, spaced apart from the first conductive surface, and includes second contact portions. The method includes determining which of the buttons is pressed. Determining whether an activation signal is received, wherein when the first contact portion contacts one of the second contact portions which shape is the same as the first contact portion, the activation signal is generated. Determining the pressed button is activated if the activation signal is received, and executing a function corresponding to the activated button.

Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

Abstract: A printed circuit board and an electronic product are disclosed. In accordance with an embodiment of the present invention, the printed circuit board includes a first board, which has an electronic component mounted thereon, and a second board, which is positioned on an upper side of the first board and covers at least a portion of an upper surface of the first board and in which an EBG structure is inserted into the second board such that a noise radiating upwards from the first board is shielded. Thus, the printed circuit board can readily absorb various frequencies, be easily applied without any antenna effect and be cost-effective in manufacturing.

Abstract: A power semiconductor module in which a substrate is provided with at least one power semiconductor and has first and second contact areas, wherein a first load connection element with first contact elements provided thereon is supported on the first contact areas and a second load connection element with second contact elements provided thereon is supported on the second contact areas. Wherein at least one spring element is provided for producing a pressure contact between the contact elements and the contact areas. To reduce the structural size of the module, the pressure contact between the contact elements and the contact areas is exerted by at least one electrical component arranged between the spring element and one of the load connection elements.

Abstract: A capacitor module in which the structure of a connecting portion is highly resistant against vibration and has a low inductance. The capacitor module includes a plurality of capacitors and a laminate made up of a first wide conductor and a second wide conductor joined in a layered form with an insulation sheet interposed between the first and second wide conductors. The laminate comprises a first flat portion including the plurality of capacitors which are supported thereon and electrically connected thereto, a second flat portion continuously extending from the first flat portion while being bent, and connecting portions formed at ends of the first flat portion and the second flat portion and electrically connected to the exterior.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.