Abstract: Disclosed herein is a semiconductor light emitting device module comprising: a substrate; at least one support disposed on a surface of the substrate; a heat transfer member disposed on the substrate and the support, the heating transfer member having a cavity formed in at least a portion of the heat transfer member; first conductive layer and second conductive layer contacting the heat transfer member via an insulating layer, the first conductive layer and the second conductive layer being electrically isolated from each other in accordance with exposure of the insulating layer or exposure of the heat transfer member; and at least one semiconductor light emitting device electrically connected to the first conductive layer and the second conductive layer, the at least one semiconductor light emitting device is thermally contacted an exposed portion of the heat transfer member.

Abstract: A mobile terminal including a case that forms at least a portion of a terminal body of the mobile terminal. The case may include a case body, a different material portion attached to the case body and composed of a plateable material that is different from a material composing the case body, and an antenna coil formed on the different material portion via plating and configured to detect a change in magnetic flux occurring at a periphery of the terminal body.

Abstract: A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

Abstract: A method includes forming a slot in a sheet through a conductive layer thereof, the slot having width in a first direction between first and second edges and length in a second, transverse direction between first and second ends, providing a non-conductive layer on the sheet, the non-conductive layer having at least one window including a first window with length greater than the slot length and width less than the slot width, the first window positioned with respect to the slot such that edges of the first window are inside the edges of the slot and ends of the first window are outside the ends of the slot, placing a component on the conductive layer within the first window so as to bridge the slot and cutting through the sheet and the non-conductive layer along first and second lines outside sides of the component and within the edges the slot.

Abstract: There is provided a wiring board capable of strengthening the bonding between an external terminal and a wiring of an external circuit board. A wiring board includes an insulating substrate having two main surfaces facing each other, side surfaces connecting to the two main surfaces and concave portions concave from the side surfaces and connecting to at least one of the two main surfaces; and external terminals disposed from one of the main surfaces to inner surfaces of the respective concave portions, each of the external terminals having a convex-shaped section disposed on one main surface side along each of the concave portions.

Abstract: The present invention relates to a method for forming solder resist and a substrate for a package. The method for forming solder resist including: forming a first solder resist inner region by primarily coating, exposing, and developing a solder resist on a substrate on which an outer PoP pad and an inner chip pad are formed, and removing the solder resist's outer portion on the substrate's outer region and curing the solder resist's inner portion on the substrate's inner region; forming a plugged SR region which does not expose the substrate; changing a surface roughness by performing a desmear process on a surface of the first solder resist inner region in which the plugged SR region is formed; and forming a second solder resist SMD region which covers an edge of the PoP pad, exposing, and developing the solder resist on the substrate after the desmear process is provided.

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a base substrate; an outer circuit layer formed on an upper portion of the base substrate and including a connection pad; a first solder resist formed on the upper portion of the base substrate so that the connection pad of the outer circuit layer is exposed; and a second solder resist formed on an upper portion of an outer circuit layer and formed so that the connection pad is exposed.

Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad and defines at least one via under the at least one first signal pad. The daughterboard includes at least one second signal pad and defines at least one via under the at least one second signal pad. The at least one first signal pad and the at least one second signal pad are sucked into the respective vias on the motherboard and the daughterboard according to siphon principle to allow each of the first signal pads and the second signal pads to form uneven top surfaces, the uneven top surfaces of the at least one first signal pads and the at least one second signal pads are connected to each other for electronically connecting the daughterboard to the motherboard.

Abstract: An electronic component includes an interposer, and a multilayer ceramic capacitor. The interposer includes a substrate including front and back surfaces that are parallel or substantially parallel to each other. Two first mounting electrodes and two second mounting electrodes are located on the front surface of the substrate, on opposite end portions in the longitudinal direction. Recesses are located in the longitudinal side surface of the insulating substrate. Connecting conductors are each provided in the side wall surface of each of the recesses. The connecting conductors connect a first external connection electrode and a second external connection electrode that are located on the back surface of the substrate, and first mounting electrodes and second mounting electrodes.

Abstract: A method of soldering can include: providing a first electronic component having a first buttoned soldering pad including a first soldering pad and one or more first button heads protruding from a first surface of the soldering pad; providing a second electronic component having a soldering pad; and soldering the first buttoned soldering pad to the soldering pad. The method includes introducing solder to spaces around the one or more first buttons of the first buttoned soldering pad. The method includes introducing a first solder to spaces around the one or more first buttons of the first buttoned soldering pad; introducing a second solder to spaces around one or more second buttons of a second buttoned soldering pad of the first electronic component; and forming spaces between the first and second solder that electronically insulate the first solder from the second solder.

Abstract: The terminal unit includes a main board, electronic components implemented on the main board, a sub-board covering above the electronic components and a frame member so disposed between the main board and the sub-board as to surround the electronic components. A flexible printed circuit covers an outer side of a wall portion of the frame member and is so wound around the frame member from upper and lower sides of the wall portion as to cover at least part of an inner side of the wall portion. A wiring pattern formed on the flexible printed circuit is electrically connected to the electronic components, and information to be protected that is stored on the electronic components becomes unreadable if the wiring pattern is cut off or short-circuited.

Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.

Abstract: Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.

Abstract: A method includes fabricating a printed circuit board. The fabricating includes forming at least one conductive layer on top a first dielectric layer. The fabricating includes forming a second dielectric layer on top of the at least one conductive layer. The fabricating includes forming a thermal pad on top of the second dielectric layer. The fabricating includes forming a first through hole through the thermal pad, the second dielectric layer, the at least one conductive layer, and the first dielectric layer. The fabricating includes filling the first through hole with a conductive material to form a plated through hole. The fabricating includes topdrilling the plated through hole to remove a top portion of the conductive material from a top of the plated through hole, wherein a bottom portion of the conductive material remains in the plated through hole after removal of the top portion.

Abstract: This process for manufacturing an electrically conductive member for an electronic component comprises the following steps: providing a structure comprising at least one blind hole having a bottom and at least one internal lateral flank connected to said bottom via a base of said lateral flank; forming the member, this forming step comprising a step of growing an electrically conductive material in order to form at least one portion of the member in the blind hole, said growth being faster at the base of the lateral flank of the blind hole than on the rest of said lateral flank, said member when formed comprising a cavity arranged at that end of said member which is located opposite the bottom of the blind hole, said cavity being entirely or partially bordered by a rim.

Abstract: A board for mechanically supporting and electrically connecting electronic components includes a non-conductive substrate, a plurality of electrically conductive traces and pads disposed on the non-conductive substrate, and a solder mask applied to the non-conductive substrate and covering the traces. Metal lines are disposed on the non-conductive substrate under the solder mask and along at least two sides of the pads disposed in corners of the non-conductive substrate, so that a metal line is interposed between the pads in the corners of the non-conductive substrate and each adjacent pad. The metal lines form a raised region in the solder mask along the metal lines which prevents solder bridging in the corners of the non-conductive substrate during solder reflow. A corresponding semiconductor package and semiconductor assembly with such solder bridging prevention structures are also provided.

Abstract: A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad.

Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.

Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.

Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

Abstract: A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc.

Abstract: Provided is a wiring board including: an insulating board having a mounting portion configured such that a semiconductor element is mounted on an upper surface thereof; a semiconductor element connection pad formed on the mounting portion; a conductor pillar formed on the semiconductor element connection pad; and a solder resist layer adhered on the insulating board. The solder resist layer has a first region with a thickness such that the semiconductor element connection pad and a lower end portion of the conductor pillar are embedded while an upper end portion of the conductor pillar protrudes, and a second region having a thickness larger than that of the first region and surrounding the first region.

Abstract: There is provided a composite electronic component including a composite body having a capacitor and an inductor coupled to each other, the capacitor including a ceramic body in which a plurality of dielectric layers and first and second internal electrodes facing each other with the dielectric layers interposed therebetween are stacked, and the inductor including a magnetic body including a coil part; a first input terminal; an output terminal; and a ground terminal.

Abstract: A printed circuit board includes: a substrate; a land that is disposed on a surface of the substrate, and includes a central portion and a plurality of extended portions, the central portion having the same shape and the same size as a land of a surface mount device, and the extended portions being up-and-down symmetry and right-and-left symmetry with respect to a straight line which passes through the center of the central portion; gaps that are disposed on the surface of the substrate, each of the gaps being disposed on a periphery of the central portion and between the extended portions; and a resist that is disposed on the surface of the substrate, and has an opening portion formed at a position corresponding to the central portion and the gaps.

Abstract: A device is described for contacting a direction-dependent electrical and/or electronic component that includes a predetermined first number of functions to be contacted, having a basic body and having a predetermined first number of first contact elements that are respectively assigned, according to a predetermined connection assignment, to a function to be contacted, and are situated on the basic body with a predetermined positioning, as well as an associated component system having such a contacting device. The positioning of the first contact elements on the basic body is made rotationally symmetrical about an angle of 90°, so that when there is a rotation of the direction-dependent electrical and/or electronic component by 90°, no different component-based functions lie against one another.

Abstract: An electronic device includes a substrate wafer made of an insulating material and having an electrical connection network. An integrated circuit chip is mounted to a top side of the substrate wafer. The substrate wafer contains an internal duct. The duct is formed by a covered trench located in the top side of the substrate wafer. The trench contains a thermally conductive material, for example being a fluid. Openings in the top side of the substrate wafer that are offset from the trench permit the making of an electrical connection between the integrated circuit and the electrical connection network.

Abstract: A method for manufacturing a printed wiring board includes forming a resin layer on an interlayer layer such that the resin layer has first openings exposing circuits in central portion and second openings exposing circuits in peripheral portion of the interlayer layer, forming solder bumps on the circuits in the first openings, forming a plating resist over the bumps and resin layer such that the resist has openings having diameters greater than the second openings and exposing the second openings, forming a seed layer on the resist, in the openings and on the circuits through the second openings, applying electrolytic plating on the resist such that electrolytic plating fills the openings and forms a plated film on the resist and metal posts in the openings, etching the plating such that the plated film is removed and recesses are formed on end surfaces of the posts, and removing the resist.

Abstract: Electronic devices may be provided with printed circuits to which integrated circuits and other electrical components may be mounted. A first printed circuit may have a first surface with an array of contact pads arranged in rows and columns. Each column of contact pads may have a series of contact pads separated by gaps. The contact pads in each column may be staggered with respect to the contact pads in adjacent columns such that each contact pad in a given column is horizontally adjacent to associated gaps in the adjacent columns. A component may be mounted to an opposing surface of the printed circuit such that it overlaps one of the gaps between the staggered contact pads. By mounting the component to portions of the first printed circuit that do not overlap the staggered contact pads, the risk of damaging the electrical component during solder reflow operations may be minimized.

Abstract: An assembly including: a first substrate having a first surface and housing a first electrical-interconnection element and a second electrical-interconnection element in a position corresponding to the first surface; a second substrate having a second surface, housing a third electrical-interconnection element and a fourth electrical-interconnection element in a position corresponding to the second surface, and provided with a dielectric layer extending on top of the third interconnection element; and a first bump and a second bump made of conductive material, extending between the first electrical-interconnection element and the third electrical-interconnection element and, respectively, between the second electrical-interconnection element and the fourth electrical-interconnection element, at least partially aligned to the respective electrical-interconnection elements, the first bump being ohmically coupled to the first interconnection element and capacitively coupled to the third interconnection element,

Abstract: An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.

Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.

Abstract: According to various embodiments, a contact pad structure may be provided, the contact pad structure may include: a dielectric layer structure; at least one contact pad being in physical contact with the dielectric layer structure; the at least one contact pad including a metal structure and a liner structure, wherein the liner structure is disposed between the metal structure of the at least one contact pad and the dielectric layer structure, and wherein a surface of the at least one contact pad is at least partially free from the liner structure, and a contact structure including an electrically conductive material; the contact structure completely covering at least the surface being at least partially free from the liner structure of the at least one contact pad, wherein the liner structure and the contact structure form a diffusion barrier for a material of the metal structure of the at least one contact pad.

Abstract: A method includes fabricating a printed circuit board. The fabricating includes forming at least one conductive layer on top a first dielectric layer, wherein the at least one conductive layer comprises at least one of a ground plane and a power plane. The fabricating includes forming a second dielectric layer on top of the at least one conductive layer. The fabricating includes forming a thermal pad on top of the second dielectric layer. The fabricating includes forming at least one plated through hole for electrically coupling the thermal pad to the at least one conductive layer. The fabricating includes backdrilling the at least one plated through hole to remove a portion of the conductive material, wherein subsequent to the backdrilling the conductive material remaining in the at least one plated through hole electrically couples one or more of the at least one conductive layer to the thermal pad.

Abstract: Various exemplary embodiments relate to a printed circuit board (PCB) comprising a ball grid array (BGA) of BGA pads on one side of the PCB, arranged in a grid pattern; through-hole vias, including a via pad, arranged in said grid pattern electrically connected to said BGA pads; a solder mask covering the via pad with an opening; a solder pad within said opening electrically connected to said via pad; and a two-lead component attached to said solder pad.

Abstract: Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.

Abstract: A display device including a substrate, a display unit on the substrate, a sealing substrate coupled to the display unit, a plurality of power pads on the sealing substrate and electrically coupled to the display unit, and a connector including a housing unit, a power connection unit electrically coupled to the plurality of power pads, and a power contact unit for maintaining contact between the plurality of power pads and the power connection unit.

Abstract: An electrical connector for electrically connecting a first electronic element having protruding conductive portions in the bottom thereof to a second electronic element, includes an insulating body located below the first and above the second electronic element, a conductor, a solder pad disposed on the lower surface of the insulating body, and a conducting line disposed in the insulating body and conducting the conductor and the solder pad. Upper surface of the insulating body has accommodation holes. Aperture of the accommodation hole is greater than outer diameter of the conductive portion. Wall and bottom of the accommodation holes form the conductor. The accommodation hole has low-melting point liquid metal conductor. When the conductive portion enters the accommodation hole, the liquid metal adheres to the conductive portion, and forms a conductive path between the conductive portion and the conductor. A manufacturing method of the electrical connector.

Abstract: An imprinted multi-level micro-wire structure includes a substrate and a first layer formed over the substrate. The first layer includes first micro-wires formed in first micro-channels imprinted in the first layer. A second layer is formed in contact with the first layer. The second layer includes second micro-wires formed in second micro-channels imprinted in the second layer. At least one of the second micro-wires is in electrical contact with at least one of the first micro-wires.

Abstract: A liquid crystal display device is provided with: a liquid crystal panel capable of displaying an image; a backlight unit including cold cathode tubes and a chassis housing the cold cathode tubes and supplying light to the liquid crystal panel; and a second exterior member housing the liquid crystal panel and the backlight unit and including a bottom portion facing the chassis. On a surface of the chassis facing the bottom portion, a plurality of fixing members capable of fixing the bottom portion is provided. The fixing members include inverter covers disposed with a gap from the bottom portion, and reinforcing members abutting on the bottom portion. Between the inverter covers and the bottom portion, spacers with the function of damping vibration are interposed.

Abstract: Contactless differential coupling structures can be used to communicate signals between circuits located on separate chips or from one chip to a probing device. The contactless coupling structures avoid problems (breaks, erosion, corrosion) that can degrade the performance of ohmic-type contact pads. The contactless coupling structures comprise pairs of conductive pads placed in close proximity. Differential signals are applied across a first pair of differential pads, and the signals are coupled wirelessly to a mating pair of conductive pads. Circuitry for generating and receiving differential signals is described.

Abstract: An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).

Abstract: Disclosed herein is a printed circuit board, including a base substrate; and a circuit pattern formed on the base substrate and including a first metal layer having an inclined surface on both upper sides thereof and a second metal layer formed on the inclined part.

Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.

Abstract: An electronic device includes a wiring board including a first electrode and a second electrode, a semiconductor device mounted on the wiring board and including a first terminal and a second terminal, an interposer provided between the wiring board and the semiconductor device, the interposer including a conductive pad and a sheet supporting the conductive pad, the conductive pad having a first surface on a side of the wiring board and a second surface on a side of the semiconductor device, a first solder connecting the first electrode positioned outside of an area in which the interposer is disposed with the first terminal positioned outside of the area, a second solder connecting the second electrode positioned inside of the area with the first surface of the conductive pad, and a third solder connecting the second terminal positioned inside of the area with the second surface of the conductive pad.

Abstract: According to one embodiment, a semiconductor device includes a board, a controller, a first line, a second line, and a pad. The board includes a first external terminal and a second external terminal. The controller is on the board. The first line extends between the first external terminal and the controller. The second line extends between the second external terminal and the controller. The pad is to be electrically connected to the second line and to be a part of a waveform adjustment circuit that makes a waveform of a signal flowing through the second line more similar to a waveform of a signal flowing through the first line.

Abstract: An electronic device includes an electronic component including a plurality of terminals and a circuit board on which the electronic component is mounted. The circuit board includes a board body, a plurality of electrode pads arranged on the board body, each of the electrode pads being connected to each of the terminals by solder, a first solder resist formed on the board body and having a plurality of first openings, each of the first openings accommodating each of the electrode pads, and a second solder resist formed on the first solder resist and having a plurality of second openings, each of the second openings being larger than each of the first openings and communicating with each of the first openings.

Abstract: A transceiver comprising a CMOS chip and a laser coupled to the chip may be operable to communicate an optical source signal from a semiconductor laser into the CMOS chip. The optical source signal may be used to generate first optical signals that are transmitted from the CMOS chip to optical fibers coupled to the CMOS chip. Second optical signals may be received from the optical fibers and converted to electrical signals via photodetectors in the CMOS chip. The optical source signal may be communicated from the semiconductor laser into the CMOS chip via optical fibers in to a top surface and the first optical signals may be communicated out of a top surface of the CMOS chip. The optical source signal may be communicated into the CMOS chip and the first optical signals may be communicated from the CMOS chip via optical couplers, which may comprise grating couplers.