Abstract: According to one embodiment, an electronic device includes a housing, a circuit board in the housing, a plurality of surface-mountable electronic components, and a reinforcing frame. The circuit board has a first surface and a second surface on a reverse side of the first surface. The surface-mountable electronic components, each having a surface on which bumps are arranged, are mounted on the first surface via the bumps. The reinforcing frame is arranged on the second surface such that it passes through portions corresponding to positions of bumps located at at least four corners of the bumps arranged on the surface of each of the surface-mountable electronic components mounted on the first surface.

Abstract: An electronic circuit board includes a substrate, a plurality of devices mounted on the substrate, and a pattern part disposed on a surface of the substrate. The devices include a surface mount device having a heat capacity higher than other device. The surface mount device includes a terminal part. The pattern part has an area larger than a pattern area determined in accordance with a current capacity for securing a required current value to be supplied to the surface mount device. The pattern part includes a land part to which the terminal part of the surface mount device is coupled with a solder melted by heating in a reflow furnace.

Abstract: A standoff contact array is disposed between a mounting substrate of a flip-chip package and a board. The standoff contact array is formable by mating a low-profile solder bump on the mounting substrate with a low-profile solder paste on the board. Thereafter, the standoff contact array is formed by reflowing the low-profile solder paste on the board against the low-profile solder bump on the mounting substrate.

Abstract: Disclosed is a portable terminal, including a first circuit board coupled to a main body and having a first connection terminal mounted on a surface thereof; a second circuit board coupled to the main body so as to cover at least a portion of the first circuit board, having a first area where an intermediate connection terminal contacting the first connection terminal is mounted on a surface thereof, and a second area where a second connection terminal electrically connected to the intermediate connection terminal is mounted on a surface thereof; and an electronic component having at least a portion thereof contacted by the second connection terminal, and for being electrically connected to the first circuit board.

Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.

Abstract: This invention provides a multilayer printed wiring board in which electric connectivity and functionality are obtained by improving reliability and particularly, reliability to the drop test can be improved. No corrosion resistant layer is formed on a solder pad 60B on which a component is to be mounted so as to obtain flexibility. Thus, if an impact is received from outside when a related product is dropped, the impact can be buffered so as to protect any mounted component from being removed. On the other hand, land 60A in which the corrosion resistant layer is formed is unlikely to occur contact failure even if a carbon pillar constituting an operation key makes repeated contacts.

Abstract: The present invention is directed to a surface mount circuit board indicator. In one embodiment the surface mount circuit board indicator includes a printed circuit board (PCB) having at least one light emitting diode (LED) die, one or more traces and at least one lens, a housing comprising at least one opening on a side along a perimeter of the housing, wherein the PCB is coupled to the housing such that a light output surface of the at least one LED die faces a same direction as the at least one opening and at least one alignment pin coupled to the housing.

Abstract: An electronic module in which an installation base is used, which includes an insulating-material layer (1) and a conductive layer on the surface of the insulating-material layer. The conductive layer also covers the installation cavity of a component (6). The component (6) is set in the installation cavity, in such a way that the contact zones face towards the conductive layer and electrical contacts are formed between the contact zones of the component (6) and the conductive layer. After this, conductive patterns (14) are formed from the conductive layer, to which the component (6) is attached.

Abstract: A method (10) for manufacturing a monolithic molded electronic assembly (12). A mold (14) having first and second mold potions (14a-b) that mate to form an interior chamber (16) is provided. The mold has an injection port (22) and channel (24) connecting into the chamber. Electronic parts (30) having electronic contacts (32) are populated onto the second mold portion, to be substantially contained in the chamber. The mold potions are mated together and a liquid insulating molding material (36) is injected through the injection port channel to fill the chamber. The molding material is hardened to a solid, thereby embedding the electronic parts in the molding material as a monolithic sub-assembly (40). The monolithic sub-assembly is removed from the mold and one or more solderless conductive circuits (50) are applied to the electronic contacts of the electronic parts, thereby providing the electronic assembly.

Abstract: The printed wiring board includes: a conductive wiring which is formed on a surface of a board and has a plurality of solder lands, to which components to be mounted are electrically connected by solder; and first and second electrically insulating layers formed on the conductive wiring, wherein the first insulating layer is formed on the conductive wiring in such a manner that the first insulating layer covers a portion of a peripheral part of one solder land and a central part of the one solder land is exposed, the portion of the peripheral part being situated on the side of another solder land, wherein the second insulating layer is piled up on the first insulating layer which covers the portion of the peripheral part of the one solder land.

Abstract: An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a fourth sidewall of each of the two bond pads. The first sidewall and the fourth sidewall are both perpendicular to an alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 ?m greater than a distance between the fourth sidewall of the at least one bond pad and a corresponding side of the corresponding opening.

Abstract: A switch matrix assembly provides for excellent frequency performance while maintaining good isolation, insertion loss, and crosstalk performance. The switch matrix assembly can include an internal bus connector card that helps eliminate or reduce stubs on a matrix star card that is part of the switch matrix. A stack bus connector card can be added in order to allow for identical busbars on other matrix star cards to be connected “stubless.” The switch matrix can also include bus stub isolator card(s) in order for busbar stubs to be broken-off reasonably close to final termination points. The stackable design of the switch matrix assembly allows for a fairly dense design which helps save space, improves serviceability, and improves overall switching performance.

Abstract: A wiring board according to the present invention includes a wiring part formed of one or more layers, a first terminal area disposed on one side of the wiring part in a projecting manner, and a second terminal area disposed on the other side of the wiring part. A resist having an opening for a first terminal area is formed on a surface of a composite made of a plurality of metal layers. A part of a first metal layer of the composite is etched through the opening for a first terminal area to form a hole. The hole is subjected to an electroless plating through the opening of the resist. Thus, the hole is filled with an electroplated layer to form a first terminal area. Then, the resist is removed from the composite, and a wiring layer is formed thereon. Subsequently, a solder resist having an opening for a second terminal area is disposed on the wiring layer. The opening of a second terminal area of the solder resist is subjected to an electroplating so as to form a second terminal area.

Abstract: Conductors of a printed circuit board have conductive flanges between pads and traces. In one embodiment, the flange has a maximum width at least one half the maximum width of the pad. It is believed that such an arrangement can significantly reduce fractures or other damage to the conductors of the printed circuit board that may result from stress applied to the board during testing or further assembly operations. Other embodiments are described and claimed.

Abstract: An electronic device assembly includes an electronic device, a transfer card configured for connecting the electronic device to another electronic device, and a fixing board for mounting the transfer card to the electronic device. The electronic device includes a front wall defining a port. The transfer card is coupled to the electronic device. The transfer card comprises a printed circuit board perpendicular to the front wall, a first connector arranged on the elongated printed circuit board and protruding beyond a first longitudinal edge thereof for engagement in the port in the front wall of the electronic device, and a second connector arranged on the printed circuit board and protruding beyond an opposite second longitudinal edge thereof.

Abstract: A circuit module includes connection electrodes on a plate-shaped board and connection electrodes on a frame-shaped board that are bonded together with conductive bonding materials there between. Circuit components are provided in portions of a surface of the plate-shaped board, the portions being located inward relative to the frame-shaped board. A sealing resin is filled and cured in a cavity, which is defined by the frame-shaped board and the plate-shaped board. Since the center of each of the connection electrodes on the frame-shaped board is inwardly displaced relative to the center of a corresponding one of the connection electrodes on the plate-shaped board by ?, a curing contraction stress of the sealing resin is mitigated by a curing contraction stress of the conductive bonding materials. Thus, deformation of the frame-shaped board is suppressed.

Abstract: A flip chip mounting method for improving the accuracy of positioning of a semiconductor chip and avoiding a short circuit between protruding electrodes even when the protruding electrodes are formed at smaller spacings. The method comprises: placing a semiconductor chip on a wiring board, the semiconductor chip having protruding electrodes formed at a relatively small spacing and at a relatively large spacing, the wiring board having electrode pads corresponding to the respective protruding electrodes and solder pieces formed on the respective pads; heating the semiconductor chip and the wiring board to a temperature at which only the solder pieces on the electrode pads of greater spacing melt; performing self alignment of the semiconductor chip by the melted solder pieces; and heating the semiconductor chip and the wiring board further to a temperature at which the protruding electrodes and the solder pieces on the electrode pads of smaller spacing melt.

Abstract: A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.

Abstract: Provided is a semiconductor package, which may include a plurality of semiconductor chips to form a multi-stack semiconductor package (MSP), a method of fabricating the semiconductor package and the MSP, and a semiconductor package mold for fabricating the semiconductor package. The semiconductor package may include a first semiconductor chip package having a first substrate including a first surface having a center portion on which a first semiconductor chip is mounted, and at least one first boundary portion on which a plurality of conductive connection pad groups are formed, and a molding member including a body that covers the first semiconductor chip, and at least one extension that extends from the body towards a corner portion of the first surface of the first substrate, wherein the extension extends while avoiding the conductive connection pad group.

Abstract: A printed circuit board is provided which is capable of shortening intervals among core layer vias and suppressing high impedance. After the core layer vias each having a cylindrical conducting layer are formed so that conducting portions come into contact with one another, a punching process is performed along a symmetric axis of each of four core layer vias so that a through-hole of a specified diameter passes through a core board to form the core layer vias separated from one another and the through-hole is filled with an insulator and a punching process is performed along a central axis of the through-hole filled with the insulator so as to pass through the core board to form the through-hole having a diameter being shorter than that of the through-hole and the conducting layer is formed on an inside wall of the through-hole to form the core layer via.

Abstract: An electronic component contained substrate in which an electronic component is mounted between a pair of wiring substrates, wherein the wiring substrates are connected electrically via solder balls, an opening portion opened larger than a planar shape of the electronic component is formed in the other wiring substrate, which faces to one wiring substrate on which the electronic component is mounted, in a position that opposes the electronic component, and a space between a pair of wiring substrates is sealed with a sealing resin.

Abstract: A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

Abstract: A spacer block that provides for a method of rebuilding an electrically operated automatic transmission controller assembly is disclosed. The block allows for offsetting and stabilizing or securing a printed circuit (PC) board to a manifold block, in which several solenoid assemblies reside within the span of the spacer block. The spacer block includes a first means for connecting to the manifold block and a second means for connecting to the PC board. The rebuilt solenoid module preferably includes at least one new solenoid.

Abstract: An electronic component and a circuit formation article are bonded together with a bonding material containing resin interposed therebetween. In a state that bumps of an electronic-component bonding region and electrodes of the circuit formation article are in mutual electrical contact, the electronic component and the circuit formation article are thermocompression-bonded to each other upon curing of the bonding material. A bonding-material flow regulating member of the electronic-component bonding region regulates flow of the bonding material toward a peripheral portion of the electronic-component bonding region during bonding of the circuit formation article to the electronic component.

Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.

Abstract: There is proposed a mounting structure including a plurality of components each having a plurality of solder bumps, a substrate having a plurality of lands, and a solder connecting portion for connecting the solder bump and the land, wherein the land provided in an outer peripheral portion of the substrate is smaller than that of the land in a central portion of the substrate.

Abstract: Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the substrate. The face of the die is aligned with at least a portion of the component layer, and terminals of the die are connected to the substrate.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port.

Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

Abstract: A signal transmission structure suitable for a multi-layer circuit substrate comprising a core layer and at least a dielectric layer is provided. The signal transmission structure according to the present invention comprises a first via landing pad and a reference plane. The first via landing pad is disposed on a first surface of the core layer, and covering one end of the through hole of the core layer. The dielectric layer covers the first via landing pad and the first surface of the core layer. And the first reference plane is disposed above the dielectric layer, having a first opening disposed above one end of the through hole. Wherein, the area where the first reference plane is projected on the first surface of the core layer does not overlap with the area where the first via landing pad is projected on the first surface of the core layer.

Abstract: A self supported underfill film (18) adhesively bonds surface mount integrated circuit packages (14) to a printed circuit board (10). The printed circuit board has conductive traces (12) and exposed conductive pads (13) on the surface. A film adhesive is strategically positioned on the printed circuit board near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads (16) on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints.

Abstract: An apparatus and method to provide a micro-electromechanical systems (MEMS) radio frequency (RF) switch module with a vertical via. The MEMS RF switch module includes a MEMS die coupled to a cap section. The vertical via passes through the cap section to electrically couple an RF switch array of the MEMS die to a printed circuit board (PCB). In one embodiment, the MEMS die includes a trace ring surrounding at least a portion of the RF switch array so that a signal may enter or exit the MEMS RF switch module using the vertical via without crossing the trace ring.

Abstract: A populated printed wiring board (PWB) (100) and method of manufacturing the populated PWB are taught. The populated PWB is manufactured by fabricating a PWB (102, 402) with exposed copper pads (302), coating the copper pads with an organic solderability preservative (OSP) (404), depositing a solder paste that includes lead-free solder on the OSP covered copper pads (406), placing components (408) and heating the PWB above a liquidous temperature of the lead-free solder in an air atmosphere (410). The process allows very close spacing of components and component leads while forming reliable solder joints to components that are mechanically stressed and components that have non-negligible planarity or coplanarity tolerances.

Abstract: Electronic devices packaged with arrayed solder balls, leads, or pads, such as Ball Grid Array (BGA) devices, are stacked together. Each stack has a bottom adapter card with metal contacts on a top surface in an array to match the array of solder balls of a lower BGA package, and final bonding pads on a bottom surface that are soldered to an underlying motherboard or printed-circuit board (PCB). An upper BGA package has its solder balls connected to a matching array of metal contacts on a top surface of an intermediate adapter card. Metal traces on the intermediate adapter card connect to lead frame pins that wrap around the edge of the intermediate adapter card and make contact with peripheral pads on the top surface of the bottom adapter card. Lead frame pins and peripheral pads can connect several intermediate adapter cards together with one bottom adapter card.

Abstract: A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.

Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. Vias in the package substrate provide electrical connection between the top and bottom sides. The vias have a via capture pad to which a wire may be wire bonded so that the wires from the IC to the substrate top side directly contact the vias at their capture pads without the need for traces from a top side bond pad to a via. The via capture pad is shaped to include at least one sharp edge to improve the ability of a wirebonder with pattern recognition software to locate the capture pad and place the wire.

Abstract: A semiconductor chip package that includes a DC—DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC—DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array.

Abstract: An apparatus in one example includes a compliant component for supporting an electrical interface component that serves to electrically and mechanically couple a die with a separate layer. In one example, the compliant component, upon relative movement between the die and the separate layer, serves to promote a decrease in stress in one or more of the die and the separate layer. The apparatus in another example includes a compliant component for supporting an electrical interface component that serves to create an electrical connection between a die and a separate layer. The compliant component, upon relative movement between the die and the separate layer, serves to promote maintenance of the electrical connection.

Abstract: A flip chip package, apparatus and technique in which a ball grid array composed of a doped eutectic Pb/Sn solder composition is used. The dopant in the Pb/Sn solder forms a compound or complex with the phosphorous residue from the electroless nickel plating process that is mixable with the Pb/Sn solder. The phosphorous containing compound or complex prevents degradation of the solder/under bump metallization bond associated with phosphorus residue. The interfacial solder/under bump metallization bond is thereby strengthened. This results in fewer fractured solder bonds and greater package reliability.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a conductor attached to a carrier to bridge a contact field defined by a circuit that can be mounted to a circuit board.

Abstract: A lockable retractable locating frame of a BGA on-top test socket includes a push-and-lock mechanism that further comprises an accommodation room, a slider, and a sliding slot for riding the slider. The slider further includes a driving portion for receiving foreign input, a tongue portion nested in the accommodation room for protruding into a stroke space formed between the retractable locating frame and a base of the test socket, and a connection portion bridging the driving portion and the tongue portion for forming a slide pair with the sliding slot. By protruding the tongue portion into the stroke space to form a stop for avoiding movement of the retractable locating frame with respect to the base, the spacing between the base and the retractable locating frame can be thus kept and the electronic device mounted on the test socket can be secured.

Abstract: In a high-frequency module mounting structure according to the present invention, a circuit board includes a reinforcing electrode on the lower surface thereof for increasing a mounting strength of the first and second electrode groups in a state of being in close proximity, a motherboard includes a reinforcing lands corresponding to the reinforcing electrodes in a state of being in close proximity to the lands, and the electrodes and the lands, and the reinforcing electrodes and the reinforcing lands are soldered. Therefore, soldering of the high-frequency module with respect to the motherboard is enhanced, and thus a reliable high-frequency module mounting structure is provided.

Abstract: A ball grid array electronic package is attached to a substrate by means of solder balls and solder paste. Connection is made between a contact on the ball grid array and a solder ball by means of a first joining medium, such as a solder paste. Connection is made between a solder ball and a contact arranged on the substrate by means of a second joining medium. The contact arranged on the substrate is substantially quadrilateral in shape, and preferably substantially square in shape. Connection to the substrate, e.g., using round solder balls, is much more easily detected, e.g., by x-ray, than when using round pads, especially those having a smaller diameter than the balls.

Abstract: A semiconductor chip package that includes a DC—DC converter implemented with a land grid array (LGA) package for interconnection and surface mounting to a printed circuit board. The LGA package integrates all required active components of the DC—DC power converter, including a synchronous buck PWM controller, driver circuits, and MOSFET devices. In particular, the LGA package comprises a substrate having a top surface and a bottom surface, with a DC—DC converter provided on the substrate. The DC—DC converter including at least one power silicon die disposed on the top surface of the substrate. A plurality of electrically and thermally conductive pads are provided on the bottom surface of the substrate in electrical communication with the DC—DC converter through respective conductive vias. The plurality of pads include first pads having a first surface area and second pads having a second surface area, the second surface area being substantially larger than the first surface area.

Abstract: The providing of an array interface of conductive joint members for use in forming interconnections between mating surfaces such as a pad on a surface mount electronic device and contacts on a circuit card where one portion of the conductive joint members are of a relatively elongated or oval outline and are oriented with the longer dimension in one direction to accommodate wiring spacing and another portion oriented in a different direction for accommodating expansion stress. In manufacturing when the relatively elongated shape is oriented with the longer dimension along the wiping motion direction in a screen type forming of the conductive joint members the slurry of material that is to be the conductive joint members fills the openings in the screen more reliably and the areas of the conductive members are more uniform.

Abstract: A noncontact ID card composed by laminating an antenna circuit board where an antenna is formed and an interposer board formed by connecting an enlarged electrode to an electrode of a mounted IC chip and bonding between an antenna electrode of the antenna circuit board and the enlarged electrode of the interposer board with electroconductive adhesive material, wherein a substrate of the antenna circuit board and a substrate of the interposer board are bonded. In addition, in another composition, at least one local deformation is applied to a boding face of the electrodes each other in a direction crossing the bonding face.

Abstract: A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.

Abstract: An adapter for a surface mount device, the adapter including an insulating body having offset first and second surfaces; a pattern of surface mount solder pads formed on the first surface; a pattern of signal carriers communicating between the first and second surfaces, each of the signal carriers being at least partially exposed in an area between the first and second surfaces and adjacent to the second surface; and a plurality of signal lines electrically coupling one or more of the surface mount solder pads with predetermined ones of the signal carriers.

Abstract: A miniaturized microelectronic, hybrid circuit package having either a single or a multi-layer, flexible, printed circuit substrate with printed conductors interconnecting a plurality of integrated circuit (IC) dies with a ball grid array (BGA) of contacts. The IC dies are arranged on parallel strips defined between preferential fold zones formed in the substrate. The dies are over molded with plastic that is shaped to facilitate the substrate being folded to form a polyhedron. When so folded, the over molded IC dies face inward and BGA is exposed on an outwardly facing surface to facilitate attachment of the folded package to a motherboard.

Abstract: To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate.