Having Spacer Patents (Class 361/770)
  • Patent number: 6559390
    Abstract: A solder connecter assembly having a printed wiring board, an electrode formed on the printed wiring board, a semiconductor package, a pad formed on the semiconductor package, a resist formed on the printed wiring board and having an opening of the resist around the electrode, a solder ball disposed between the electrode and the pad, and a resin fillet formed in the opening and in a vicinity of a connecting part between the solder ball and the electrode.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: May 6, 2003
    Assignee: NEC Corporation
    Inventor: Kei Tanaka
  • Patent number: 6542372
    Abstract: An spacer assembly for spacing a circuit board from a chassis includes a plug that is adapted to extend through a mounting aperture in the chassis and a cap that is adapted to receive the plug in locking engagement for sandwiching the chassis therebetween. The cap has an upper wall that supports the circuit board and a skirt that extends from the upper wall to form a hollow interior that is sized to receive the plug. First cooperating structure on the plug and cap hold the plug within the hollow interior of the cap, while second cooperating structure on the plug and cap hold the chassis therebetween.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: April 1, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David M. Paquin, David A. Selvidge
  • Patent number: 6541710
    Abstract: A column grid array integrated circuit package has a substrate. The substrate has a solder column array having a plurality of solder columns and a plurality of rigid columns interspersed with the solder columns at no-connect locations. The rigid columns contact a circuit board to which the column grid array integrated circuit package is mounted and support the column grid array integrated circuit package against compressive force.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: April 1, 2003
    Assignee: Hewlett-Packard Company
    Inventors: Jeffrey L. Deeney, David W. Mayer
  • Patent number: 6535394
    Abstract: Electronic apparatus is described comprising a printed circuit board mounted on a support structure. The printed circuit board has at least one keyhole shaped fixing hole, the support structure being provided with at least one electrically conducting fixing post having an at least partially circumferential slot for engaging the fixing hole. The printed circuit board has a conducting surface adjacent said fixing hole that is disposed to provide an electrical contact with said post so as to establish an electrical circuit between at least one component mounted on the printed circuit board and the support structure. The arrangement is particularly suitable for securely coupling a computer's motherboard to its casing or chassis.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: March 18, 2003
    Assignee: Hewlett-Packard Company
    Inventor: Claus Hirzmann
  • Publication number: 20020196614
    Abstract: A microprocessor packaging architecture using a modular circuit board assembly that provides power to a microprocessor while also providing for integrated thermal and electromagnetic interference (EMI) is disclosed. The modular circuit board assembly comprises a substrate, having a component mounted thereon, a circuit board, including a circuit for supplying power to the component, and at least one conductive interconnect device disposed between the substrate and the circuit board, the conductive interconnect device configured to electrically couple the circuit to the component.
    Type: Application
    Filed: July 23, 2002
    Publication date: December 26, 2002
    Applicant: INCEP Technologies, Inc.
    Inventors: Joseph T. DiBene, David H. Hartke, James J. Hjerpe Kaskade, Carl E. Hoge
  • Patent number: 6493240
    Abstract: The present invention is an interposer for electrically coupling a microcard with a mother board. The interposer includes a frame which is interposed between the microcard and the motherboard, electrically connecting the microcard and the motherboard by means of plated via-holes. The substrate is organic and a plurality of chips are mounted on both sides of the substrate. On the opposite sides of the interposer are pluralities of metal pads which are coupled by metallized via holes, the pads in turn connected to the chips, thereby coupling chips or cards on one side of the interposer to chips or boards on the other side. Electrical connection between the chips on the top side of the substrate and the metal pads on the lower side of the substrate is provided by the metallized via holes.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Patrizio Broglia, Francesco Garbelli, Alberto Monti
  • Patent number: 6486406
    Abstract: An apparatus and method for providing radial alignment of a housing mounted on a circuit board is provided. A mounting leg portion extends outward from a mounting surface of the housing. The mounting leg portion has a body portion, an end portion, and a radial alignment portion. The radial alignment portion extends outward from the mounting surface. The radial alignment portion has a circumference, and is adapted to be received in a mounting opening formed in the circuit board. The radial alignment portion prevents radial movement of the mounting leg portion with respect to the circuit board. The end portion of the mounting leg portion includes a snap portion for engaging the circuit board and securing the mounting leg portion to the circuit board.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: November 26, 2002
    Assignee: 3Com Corporation
    Inventors: Gerald A. Greco, Kenneth S. Laughlin, Philip A. Ravlin
  • Patent number: 6467185
    Abstract: A potted timer and circuit board assembly for use in a regenerative desiccant air dryer. The potted timer and circuit board assembly comprise a support member of a predetermined size and shape having a first surface and a second surface. A conductive pattern of a predetermined material and thickness is disposed on at least one of the first surface and the second surface of the support member. A predetermined quantity and arrangement of electronic components of a predetermined voltage is disposed on at least one of the first surface and the second surface of the support member for providing a timed electronic signal to a solenoid valve that pneumatically operates an air dryer. A non-conductive material of a predetermined composition encases the electronic components on the support member for insulating the electronic components from environmental elements.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: October 22, 2002
    Assignee: Westinghouse Air Brake Technologies Corporation
    Inventors: Matthew D. Mitsch, James Varney
  • Patent number: 6437990
    Abstract: The specification describes a high density IC BGA package in which one or more IC chips are wire bonded to a BGA substrate in a conventional fashion and the BGA substrate is solder ball bonded to a printed wiring board. The standoff between the BGA substrate and the printed wiring board to which it is attached provides a BGA gap which, according to the invention, accommodates one or more IC chips flip-chip bonded to the underside of the BGA substrate. The recognition that state of the art IC chips, especially chips that are thinned, can easily fit into the BGA gap makes practical this efficient use of the BGA gap. The approach of the invention also marries wire bond technology with high packing density flip-chip assembly to produce a low cost, high reliability, state of the art IC package.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: August 20, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, King Lien Tai
  • Patent number: 6410366
    Abstract: A semiconductor device comprising: a semiconductor chip (10) which is subjected to face-down bonding, having a plurality of electrodes (12) aligned on a straight line (L); a substrate (20) on which is formed an interconnect pattern (22) having bonding portions (24) to which the electrodes (12) of the semiconductor chip (10) are connected and lands (26) electrically connected to the bonding portions (24); external electrodes (30) passing through the substrate (20) and connected to the lands (26); and a support formed from bumps (11, 21) provided between the semiconductor chip (10) and substrate (20), wherein the connected electrodes (12) and bonding portions (24) and the support formed by the bumps (11, 21) maintain the semiconductor chip (10) and substrate (20) substantially parallel.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: June 25, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 6404646
    Abstract: A PC board support is disclosed to include a hollow support shell adapted to support a PC board above a frame, a spring mounted inside the support shell, the support shell having a top opening, a top neck, and a retainer head at the top of the top neck, and a slide supported on the spring inside the support shell and moved along a vertical sliding groove at the retainer head and top neck of the support shell in and out of the top opening to unlock/lock the PC board.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: June 11, 2002
    Assignee: Enlight Corporation
    Inventors: Hsiang-Hsiang Tsai, Chao-Kun Chan
  • Patent number: 6399895
    Abstract: System of components for hybridization including a first component (410) with a first set of hybridization studs (414), and at least a second component (412) with second hybridization studs (450), the first and second studs being respectively associated in pairs of studs, one of the first and one of the second studs, with at least one pair of studs, equipped with a projection (418) of meltable material and the other aforesaid first and second studs of the pair of studs, referred to as contact studs (450, 450a, 450b), having a surface wettable by the meltable material. According to the invention at least one part of the contact stud (450) forms a protuberance (452). Application to manufacturing of electronic, electro-optic and mechanical components.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: June 4, 2002
    Assignee: Commissariat a L'Energie Atomique
    Inventors: François Marion, Dominique Marion, Jean-Louis Ouvrier-Buffet
  • Patent number: 6384343
    Abstract: The present invention provides a semiconductor device of the BGA (ball grid array) package type comprising: a semiconductor chip 1; a plurality of wiring layers 1B arranged on the semiconductor chip via an insulation layer 1A, each of the wiring layers having a chip-side land block 1C as a signal I/O region; a circuit substrate having a plurality of wiring lines; and a plurality of solder balls 2 each to be arranged on the chip-side land block for connecting the wiring layers to corresponding wiring lines on the circuit substrate; wherein each of the chip-side land blocks 1C has a land protrusion block 3 extending into the solder ball 2. The land protrusion block 3 increases the attachment strength between the chip-side land block 1C and the solder ball 2 and suppresses growth of a crack generated in the solder ball 2 due to a thermal stress.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: May 7, 2002
    Assignee: NEC Corporation
    Inventor: Kazuyoshi Furusawa
  • Patent number: 6370030
    Abstract: The present invention relates to a device and a method at a printed board for obtaining good transmission qualities in transmission conductors on a predetermined area (10) of the printed board (11). A separate component (1) for signal transmission comprises a conductor (5). The component (1) is mounted, with the conductor facing the printed board (11), over the area (10) of the printd board, which requires good transmissions qualities, whereby an air gap (L) is obtained between the conductor (5) and the printed board (11). Soldering joints (21) connect each one of the outer parts (7a, 7b) of the conductor (5) of the component (1) to corresponding pattern conductors (17a, 17b) on the printed board (11). The thickness of the soldering connections and the thickness of the pattern conductors form the air gap (L) be the conductor (5) and the printed board (11).
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: April 9, 2002
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Leif Roland Bergstedt, Bo Roland Carlberg
  • Publication number: 20020006033
    Abstract: A method of improving the life expectancy of surface mount components is electronic assemblies wherein a distance between the printed circuit board and the surface mount component is held to a predetermined distance defined as the stand-off height. The relationship between the stand-off height and the life expectancy of the component is directly proportional. A larger stand-off height translates into a longer life expectancy. The stand-off height is limited only by manufacturing constraints, such as process limitations and cost concerns. The stand-off height is set to a predetermined dimension by way of a spacer positioned between the surface mount component and the printed circuit board.
    Type: Application
    Filed: July 29, 1999
    Publication date: January 17, 2002
    Inventor: MAHESH K. CHENGALVA
  • Patent number: 6329609
    Abstract: An electronic component structure assembly comprising a thin film structure bonded to a multilayer ceramic substrate (MLC) using solder connections and wherein a non-conductive, compliant spacer preferably with a layer of thermoplastic adhesive on each surface thereof is interposed between the underlying MLC carrier and overlying thin film structure. The spacer includes a pattern of through-holes which corresponds to opposing contact pads of the thin film structure and MLC. The contact pads of at least one of the thin film structure or MLC have posts (e.g., metallic) thereon and the posts extend partly into the spacer through-holes whereby the height of the posts are greater than the thickness of the adhesive. The posts of the MLC have solder bumps thereon. After reflow under pressure the thin film structure is electrically and mechanically connected to the MLC and the join method has been found to provide a reliable and cost-effective process. The joined components also have enhanced operating life.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: December 11, 2001
    Assignee: International Business Machines Corporation
    Inventors: Suryanarayana Kaja, Chandrika Prasad, RongQing Yu
  • Patent number: 6330164
    Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: December 11, 2001
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, David V. Pedersen, Benjamin N. Eldridge, Richard S. Roy, Gaetan Mathieu
  • Patent number: 6313998
    Abstract: A circuit board assembly having integrated circuit packages vertically arranged three dimensionally is used to increase electronic component density without increasing the size of the circuit board. For a preferred embodiment of the circuit board assembly, the printed circuit board has at least one primary mounting pad array affixed thereto, each pad of the array having first and second portions. Each lead of a first integrated circuit package is conductively bonded to the first portion of a different mounting pad of said primary array. A package carrier having a plurality of carrier leads attached thereto and a secondary mounting pad array on an upper surface thereof, covers the first package. Each lead of the carrier is coupled to a different pad of the secondary array and is also conductively bonded to the second portion of a different mounting pad of the primary array. Each lead of a second integrated circuit package is conductively bonded to a different mounting pad of the secondary mounting pad array.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: November 6, 2001
    Assignee: Legacy Electronics, Inc.
    Inventors: Kenneth J. Kledzik, Jason C. Engle
  • Publication number: 20010032738
    Abstract: A microprocessor packaging architecture using a modular circuit board assembly that provides power to a microprocessor while also providing for integrated thermal and electromagnetic interference (EMI) is disclosed. The modular circuit board assembly comprises a substrate, having a component mounted thereon, a circuit board, including a circuit for supplying power to the component, and at least one conductive interconnect device disposed between the substrate and the circuit board, the conductive interconnect device configured to electrically couple the circuit to the component.
    Type: Application
    Filed: February 16, 2001
    Publication date: October 25, 2001
    Inventors: Joseph Ted Dibene, David Hartke, Kaskade James Hjerpe, Carl E. Hoge
  • Patent number: 6288904
    Abstract: The chip module is particularly suitable for implanting in a smart card body. The module has a carrier and a chip fitted on the carrier. A pedestal or base-type elevation formed on the carrier laterally surrounds the chip completely or partly.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: September 11, 2001
    Assignee: Infineon Technologies AG
    Inventors: Detlef Houdeau, Peter Stampka, Michael Huber, Josef Heitzer
  • Patent number: 6278066
    Abstract: A spacer (100 or 600/1000A/1000B) situated between a faceplate structure (301) and a backplate structure (302) of a flat panel display is configured to be self standing. In one implementation, a pair of spacer feet (111 or 113 and 112 or 114) are located over the same face surface, or over opposite face surfaces, of a spacer wall (101) near opposite ends of the wall. An edge electrode (121 or 122) is located over an edge surface of the spacer adjacent to the faceplate structure or the backplate structure. In another implementation, a spacer clip (1000A or 1000B) clamps opposite face surfaces of a spacer wall (600) largely at one end of the wall.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: August 21, 2001
    Assignee: Candescent Technologies Corporation
    Inventors: Theodore S. Fahlen, Alfred S. Conte, Robert M. Duboc, Jr., George B. Hopple, John K. O'Reilly, Vasil M. Chakarov, Robert L. Marion, Steve T. Cho, Robert G. Neimeyer, Jennifer Y. Sun, David L. Morris, Christopher J. Spindt, Kollengode S. Narayanan
  • Patent number: 6249440
    Abstract: The contact arrangement is a connector block for detachably fastening an electrical component, particularly an integrated circuit having a plurality of terminal contacts disposed in a ball grid array (BGA), in a column grid array (CGA), in a land grid array (LGA) or of the flip-chip type to a printed circuit board. In a support part, a number of contact pins are disposed in a grid in bores. The contact pins project from the bore on the side facing the printed circuit board and are surface-mounted together with contact areas of the printed circuit board. A free end region of each bore is intended for guiding the substantially dome-shaped terminal contacts. Between the end of a contact pin and a terminal contact there is a space bridged for establishing an electrical connection with a contact element, for example an axially compressible coil spring. By means of several holding-down elements disposed peripherally to the integrated circuit, the integrated circuit is pressed down upon the support part.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 19, 2001
    Assignee: E-TEC AG
    Inventor: Hugo Affolter
  • Patent number: 6225566
    Abstract: A screw retaining spacer includes an outer rigid plastic core and a softer elastic inner core defining a through-hole. The inner core has a plurality of ridges that resiliently grasp the shaft of a screw inserted into the through-hole. Accordingly, screws assembled with these spacers remain assembled. The spacer can be standardized and inventoried in large quantities to meet a variety of screw sizes and tolerance.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: May 1, 2001
    Assignee: Bivar
    Inventor: Richard L. Dienst
  • Patent number: 6181567
    Abstract: A method of securing an electronic package to a circuit board includes the step of providing a retainer having a locating cavity defined therein. The method further includes the step of positioning the electronic package within the locating cavity so that the electronic package is fixed in relationship to the retainer. Moreover, the method includes the step of securing the retainer in fixed relationship to the circuit board so as to sandwich the electronic package between the retainer and the circuit board. The securing step is performed after the positioning step. An apparatus for securing an electronic package to a circuit board is also disclosed.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: January 30, 2001
    Assignee: NCR Corporation
    Inventors: Robert W. Roemer, Eddie V. Williams
  • Patent number: 6156408
    Abstract: The method (400, 500) and device (200) for reworkable direct chip attachment include a thermal-mechanical and mechanical stable solder joint for arranging connection pads on a top surface of the circuit board to facilitate connection for electronic elements, and affixing a reinforcement having apertures to accommodate solder joints to the top surface of the circuit board to facilitate solder attachment of the connection pads to the electronic elements wherein the reinforcement constrains deformation of the circuit board to provide reliable solder joints and facilitates attachment and removal of electronic elements from the circuit board.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: December 5, 2000
    Assignee: Motorola, Inc.
    Inventors: Wen Xu Zhou, Daniel Roman Gamota, Sean Xin Wu, Chao-pin Yeh, Karl W. Wyatt, Chowdary Ramesh Koripella
  • Patent number: 6147310
    Abstract: A holder (200) for holding an electronic component (100), which can be inserted into and removed from the holder (200), is formed to be both electrically and thermally insulative. The holder (200) is formed from an insulative body molded to form a cavity (205) into which the electronic component (100) can be inserted. The insulative body includes sidewalls (210) formed to partially enclose the electronic component (100) when it is inserted into the holder (200) and a bottom surface (250) formed perpendicularly with the sidewalls (210). The bottom surface (250) defines at least two apertures (225) through which terminals (110) of the electronic component (100) can extend.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: November 14, 2000
    Assignee: Scientific-Atlanta, Inc.
    Inventor: William G. Mahoney
  • Patent number: 6137164
    Abstract: A thin, stacked face-to-face integrated circuit packaging structure includes a chips attached to both major surfaces of a rigid interposer, and interconnected by printed wiring traces and vias to external solder ball contacts attached to the interposer.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: October 24, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Chee Klang Yew, Siu Waf Low, Min Yu Chan
  • Patent number: 6124546
    Abstract: A semiconductor integrated circuit chip package includes top and bottom interposers 2 and 4, a semiconductor die 14 attached to the top interposer 2, a wirebond 18 or a flipchip connector 52 connected between the die 14 and the top interposer 2, and a tab bond 22 providing an electrical connection from the wirebond 18 or the flipchip connector 52 to outside the bottom interposer 4. A method of making the chip package includes providing top and bottom interposers 2 and 4, attaching a semiconductor die 14 to the top interposer 2, providing a wirebond 18 or a flipchip connector 52 between the die 14 and the top interposer 2, providing a tab bond 22 between the top and bottom interposers 2 and 4, and providing an encapsulant 16 to fill the intermediate volume 40 between the top and bottom interposers 2 and 4.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: September 26, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Hayward, Quang Nguyen
  • Patent number: 6097099
    Abstract: A design having a semiconductor microchip bonded to a circuit board is described. This design may include: a printed circuit board (58); a semiconductor microchip (56) bonded to the circuit board (58) by means of an adhesive layer placed between the bonding surface of the microchip (56) and the desired bonding site on the circuit board (58); the adhesive layer providing for thermal relief as well as electrical contact between the microchip (56) and circuit board (58), and consisting of two or more concentric regions that adjoin but do not overlap one another; one being a center core region (50) of thermally and electrically conductive material; the other being a perimeter region (54) of thermally conductive and electrically nonconductive material surrounding the center core region (50) such that the perimeter region's (54) inner boundary completely bounds the center core region (50); and such that the perimeter region's (54) outer boundary extends to a lead on the microchip (56).
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: August 1, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Prosenjit Ghosh, Sunil Thomas
  • Patent number: 6020809
    Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: February 1, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Michio Miyazaki, Haruyuki Takeuchi, Tadao Bekku
  • Patent number: 6008991
    Abstract: An electronic system such as a Board-Level-Product (BLP) includes at least one integrated circuit device which is mounted on a circuit board. Each integrated circuit device includes a thin dielectric substrate bearing a plurality of conductive leads and has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on the circuit board.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: December 28, 1999
    Assignee: LSI Logic Corporation
    Inventors: Emily Hawthorne, John McCormick
  • Patent number: 6005778
    Abstract: Chip stacking and capacitor mounting arrangement including a planar spacer separating a first die and a second die. A conductive spacer provides for backside chip grounding in one application and provides for capacitor mounting in another application.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: December 21, 1999
    Assignee: Honeywell Inc.
    Inventors: Richard K. Spielberger, Ronald J. Jensen, Charles J. Speerschneider
  • Patent number: 5986890
    Abstract: A semifinished product for an electronic module includes an integrated circuit and a coil electrically connected with the circuit, the coil being disposed between two carrier layers and the integrated circuit being disposed in a specially provided cavity in the two carrier layers. To achieve plane surfaces of the semifinished product, the remaining cavity between the carrier layers and the integrated circuit is filled with a filling material in such a way that plane surfaces of the semifinished product result in the area of the cavity which are flush with the surfaces of the carrier layers.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: November 16, 1999
    Assignee: Giesecke & Devrient GmbH
    Inventors: Joachim Hoppe, Arno Hohmann
  • Patent number: 5969952
    Abstract: In order to provide an improved hybrid IC having a high density, compact in size, capable of being manufactured with a reduced cost, a hybrid IC of the present invention, comprises: a circuit board 2 having formed on the surface thereof a plurality of electrode patterns, and mounting on the same surface a plurality of electronic elements 3; a plurality of connection terminals 4 each formed into a generally rectangular frame structure including mutually facing first and second lateral plates, and mutually facing first and second longitudinal plates. In particular, one of the first and second lateral plates of each connection terminal 4 is fixedly connected to a connection electrode 2a on the circuit board 2. With the use of such structure, it is allowed to dispense with a process of solely connecting the connection terminals, thereby reducing the time and hence the cost for manufacturing a hybrid IC.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: October 19, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masanobu Hayashi, Masao Yonezawa
  • Patent number: 5939783
    Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: August 17, 1999
    Assignee: International Business Machines Corporation
    Inventors: Eric Herman Laine, James Warren Wilson
  • Patent number: 5936846
    Abstract: There is disclosed herein a surface mount printed circuit board having a substrate, at least one surface mount device, at least two mounting pads per device, solder joints connecting the terminations of the device to their respective mounting pads, at least one rectangular lifter pad on the substrate amid the mounting pads, and a solder mass on each lifter pad in contact with the bottom surface of the device. The inner and outer extensions of the mounting pads, the size, number, and shape of the lifter pads, and the amounts of solder deposited on the mounting and lifter pads are designed such that the solder joint has preferably convex outer fillets, the device is maintained at a predetermined height above the mounting pads, the inner fillet angle is maintained above a predetermined minimum angle to increase solder joint crack initiation time, and the overall solder joint crack propagation length is increased.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: August 10, 1999
    Assignee: Ford Global Technologies
    Inventors: Vivek Amir Jairazbhoy, Richard Keith McMillan, II, Yi-Hsin Pao
  • Patent number: 5936847
    Abstract: An improved circuit module construction for mounting and interconnecting electronic components to substrates, which is applicable to mounting a wide variety of electronic components and conductors, including inverted or `flip chip` mounted integrated circuits. The components are mounted to the substrate with a sandwiched non-conductive polymer layer which acts as the bonding agent and underfill. The substrate and underfill have apertures aligned with signal traces on the substrate and the contacts of the component and conductive polymer is injected through the apertures to fill the area between the substrate contacts and the component contacts, to secure good electrical connection. In one embodiment the non-conductive polymer is printed on the contact side of the substrate with gaps for the contacts. In another embodiment B-staged non-conductive polymer is coated on the non-contact side of the substrate, prior to forming contact apertures and mounting of components.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: August 10, 1999
    Assignee: HEI, Inc.
    Inventor: Scott J. Kazle
  • Patent number: 5931371
    Abstract: A method for joining a component to a substrate applies a base solder portion to the substrate and provides a standoff solder portion in the base solder portion. The standoff solder portion has a higher melting temperature than the base solder portion and a height which substantially corresponds to a desired standoff height between the component and the substrate. The component is positioned on the standoff solder portion and the base solder portion is melted under reflow conditions to form a solder joint between the component and the substrate. This joint substantially encapsulates the standoff solder portion, wherein the reflow conditions create a dendritic structure between the base solder portion and the standoff solder portion.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: August 3, 1999
    Assignee: Ford Motor Company
    Inventors: Yi-Hsin Pao, Chan-Jiun Jih, Jun Ming Hu, Vivek Amir Jairazbhoy, Richard Keith McMillan, II, Xu Song
  • Patent number: 5929743
    Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: July 27, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Michio Miyazaki, Haruyuki Takeuchi, Tadao Bekku
  • Patent number: 5903439
    Abstract: A mezzanine connector assembly includes connectors engageable to a mating connector assembly such as a motherboard. It includes a circuit card having a surface on which a connector is mounted as well as a mezzanine card having a surface on which another connector is mounted. A mounting member is attached for connection between the cards in order to establish relative positions of the card surfaces. The distance between the card surfaces is set at least in part by the distance between end portions of the mounting member. The distance between the card surfaces is independent of the thickness of the cards so that a variation of the thickness of the cards will not result in a variation of the distance between the card surfaces.
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: May 11, 1999
    Assignee: Unisys Corporation
    Inventor: Vladimir K. Tamarkin
  • Patent number: 5901047
    Abstract: The disclosed invention relates to the employment of a spacer element for mounting, aligning and spacing a computer chip relative to a PCB. The spacer element is formed and dimensioned to engage the chip in a manner to assure that the pins of the chip are properly aligned relative to openings in the PCB and to assure that the chip is centered and maintained parallel to the PCB and each of its pins maintained equal distance from the underneath side of the PCB during the wave soldering process for electrically connecting the chip and PCB.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: May 4, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel D. Gonsalves, Paul D. Welch, Lance E. Terry, Leonardo Sandman, Kia-Pin A. May
  • Patent number: 5886878
    Abstract: The present application describes a through-hole component insulator and assembly process which has the advantages of preventing solder from contacting the metal case of a through-hole component without an addition step or additional material from the standard fabrication process for a printed circuit board. The printed circuit board of the present invention includes a printed ink spacer disposed beneath the through-hole component wherein the printed ink spacer is included with a standard silk-screen artwork layer in the printed circuit board design stage. The printed ink spacer raises the through-hole component from the printed circuit board surface to prevent solder from contacting the metal case of the through-hole component during the printed circuit board soldering stage. Using a silk-screen artwork layer which includes at least one printed ink spacer in the artwork, the printed ink spacer is deposited during deposition of a standard printed design on the printed circuit board fabrication.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: March 23, 1999
    Assignee: Dell USA, L.P.
    Inventors: Gita P. Khadem, Darrell J. Slupek
  • Patent number: 5805427
    Abstract: A surface mount package to encapsulate one or more semiconductor devices has a standoff that maintains the thickness of solder columns bonding the package to an external circuit. The standoff either extends over or circumscribes a central portion of the package base. To enhance the thermal performance of the standoff, a solderable layer enhances soldering of the standoff to the external circuit.In alternative embodiments, the standoff contains a flange having a plurality of apertures useful for either mechanically locking an adhesive or for enabling irradiation of an adhesive by a light source. The standoff may contain protrusions for alignment, strength or circuit routing.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: September 8, 1998
    Assignee: Olin Corporation
    Inventor: Paul R. Hoffman
  • Patent number: 5801923
    Abstract: A multichip module is attached to a printed wire circuit board using three conductive mounting feet that are vapor phase soldered to conductive feet on the module's substrate and to conductive feet on the printed wiring circuit board that are connected to a ground plane on the board.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: September 1, 1998
    Assignee: Honeywell Inc.
    Inventor: Randolph G. Nichols
  • Patent number: 5754404
    Abstract: A frameless IC card is provided, with front and rear support structures that each includes an electrical connector, with a sheet metal cover mounted on the front and rear board supports without requiring a separate plastic frame to tie the components together. The rear support structure includes at least one rear connector (11', 12', FIG. 3) fixed to the circuit board rear end (104') and an end cap (16') at the rear of the IC card. The end cap has upper and lower flanges (126T, 126B) that form a recess therebetween that closely receives the rear of the rear connector housing to fix their relative vertical positions. The rear end cap has forwardly-extending legs (47, 48) at opposite sides, with each leg having a lug (51, 52) forming a rearwardly-facing shoulder (150) that fits into a cutout (53) at a side of the circuit board, to prevent forward movement of the connector and circuit board out of the rear end cap.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: May 19, 1998
    Assignee: ITT Cannon GmbH
    Inventors: Werner Biermann, Jan Zeyfang, Gary Cain Bethurum
  • Patent number: 5751556
    Abstract: A method and apparatus for reducing warpage of an assembly substrate and providing registration between a surface mount technology (SMT) component and the assembly substrate. The SMT component includes mounting pins extending from the component and capable of engaging corresponding apertures in the assembly substrate. Each mounting pin is registrable with a corresponding aperture in the assembly substrate. The mounting pins are capable of providing an interference fit between the SMT component and the assembly substrate.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: May 12, 1998
    Assignee: Intel Corporation
    Inventors: Peter O. Butler, Ricardo E. Suarez-Gartner
  • Patent number: 5745985
    Abstract: A method of attaching a microchip onto a circuit board is described. The method may include: forming a core portion of thermally conductive and electrically conductive material 50; forming a perimeter portion of thermally conductive and electrically nonconductive material 54; placing the core portion of thermally conductive and electrically conductive material 50 at a site on a circuit board 58 where the microchip 56 will be bonded; placing the perimeter portion of thermally conductive and electrically non-conductive material 54 around the core portion 50 on the circuit board; and attaching microchip component 56 to the core portion 50 and the perimeter portion 54. The method may also include applying a catalyst on the circuit board before attaching the core and perimeter portions. The method may also include curing the core portion and the perimeter portion at 90 degrees C. for 10 minutes and then applying a catalyst on the core portion and the perimeter portion.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: May 5, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Prosenjit Ghosh, Sunil Thomas
  • Patent number: 5720843
    Abstract: An electrical interconnection method, where two substrates are interconnected by an electrical connection medium, includes the steps of: depositing conductive particles on the connection surface of one of two substrates which are to be interconnected; depositing paste on the connection surface of another substrate; and interconnecting the connection surfaces of the two substrates. Also, the interconnection method according to another embodiment embodiment includes the steps of: depositing conductive particles on the connection surface of one of two substrates which are to be interconnected; contacting the connection surfaces of the two substrates; and injecting paste into a gap between the two substrates to interconnect the two substrates.
    Type: Grant
    Filed: November 8, 1995
    Date of Patent: February 24, 1998
    Assignee: Samsung Display Devices Co., Ltd.
    Inventor: Chang-hoon Lee
  • Patent number: 5684677
    Abstract: An electronic circuit device comprising a printed wiring board having a major surface and pads provided on the major surface of the printed wiring board, a plurality of electrodes provided partly on at least one major surface of the leadless component and partly on sides of the leadless component, a plurality of bumps provided on the pads, providing a gap between the major surface of the printed wiring board and the major surface of the leadless component, and electrically connecting those parts of the electrodes which are provided on the major surface of the leadless component to the pads, and a plurality of electrically conductive members integral with the bumps, extending from the bumps to those parts of the electrodes which are provided on the sides of the leadless component.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: November 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Uchida, Takashi Yebisuya, Miki Mori, Masayuki Saito, Takasi Togasaki, Yukio Kizaki
  • Patent number: 5650919
    Abstract: An apparatus, comprising a first member, including two conductive paths, a conductive adhesive, a second member, including two conductive paths, each of the two conductive paths of the second member being connected to a corresponding one of the two conductive paths of the first member via the conductive adhesive, to form two electrical connections, and a peak-shaped dielectric dam, formed on the second member between the two electrical connections.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: July 22, 1997
    Assignees: Zymet, Inc., Samsung Display Devices Co., Ltd.
    Inventors: Karl I. Loh, Chang Hoon Lee