Having Particular Material Patents (Class 361/771)
  • Patent number: 8248814
    Abstract: A PCB includes an outer layer and an inner layer. An electronic component is mounted on the outer layer. The outer layer further defines a first pad, a second pad, a third pad, a fourth pad, and a number of via holes. The electrical performances of the first pad and the second pad are the same to that of the inner layer. The first pad and the second pad are conducted to the electronic component. The third pad and the fourth pad are respectively conducted to the first pad and the second pad through the electronic component. The electrical performances of the third pad and the fourth pad are different from that of the inner layer. The via holes are respectively electrically connected to the third pad and the fourth pad.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: August 21, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chun-Po Chen, Chi-Wen Chen
  • Patent number: 8242378
    Abstract: A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Ahmed Amin, Frank Baiocchi, John Delucca, John Osenbach, Brian T. Vaccaro
  • Patent number: 8241760
    Abstract: A joint structure of the present invention includes a conductive member containing copper as a major component thereof, an electrode member containing copper as a major component thereof, and a joint portion formed by fusion welding the conductive member and the electrode member with a brazing material containing tin as a major component thereof and containing substantially no copper, wherein the amount of copper atoms contained in the alloy in the central part of the joint portion is higher than that in the outer circumference part.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: August 14, 2012
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventor: Toshiaki Chuma
  • Patent number: 8207453
    Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Patent number: 8184449
    Abstract: An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: May 22, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Do Lee, Hak-Kyoon Byun, Tae-Hun Kim, Sang-Uk Han, Seon-Hyang You
  • Publication number: 20120106109
    Abstract: Disclosed herein are a power module using sintering die attach and a manufacturing method of the same. The power module includes: a substrate having an insulating layer formed on a surface of a metal plate; a circuit layer formed on the substrate and including a wiring pattern and an electrode pattern; a device mounted on the wiring pattern; a sintering die attach layer applying a metal paste between the wiring pattern and the device and sintering the metal paste to bond the wiring pattern to the device; and a lead frame electrically connecting the device to the electrode pattern, whereby making it possible to to simplify and facilitate the process, increase electrical efficiency and improve radiation characteristics, and manufacture firm and reliable power module.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 3, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Hyun KIM, Yong Hui Joo, Seog Moon CHOI
  • Publication number: 20120092844
    Abstract: A method of fabricating packaging for a product comprises forming a plurality of conductive tracks on a sheet of material and forming a physical barrier, such as a hole, for impeding fluid flow between adjacent conductive tracks. The method may further comprise depositing first and second regions conductive fluid onto adjacent first and second conductive tracks either side of the physical barrier and mounting an electronic device having first and second terminals such that the electronic device forms a bridge over the physical barrier and the first ands second terminals contact the first and second conductive adjacent tracks.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 19, 2012
    Applicant: NOVALIA LTD
    Inventor: Kate Stone
  • Patent number: 8134083
    Abstract: A circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the dielectric layer having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 13, 2012
    Assignee: AB Mikroelektronik Gesselschaft mit beschrankter Haftung
    Inventor: Bernd Haegele
  • Publication number: 20120033394
    Abstract: The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 9, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Bernd Karl Appelt, Ming-Chiang Lee
  • Publication number: 20110317385
    Abstract: WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper posts formed on the integrated circuit chips of the WLP devices. Barrier layers formed of a metal such as nickel (Ni) are provided on the outer surface of the copper posts to inhibit electromigration in the bump assembly. Oxidation prevention caps formed of a metal such as tin (Sn) are provided over the barrier layer. Solder bumps are formed over the oxidation prevention caps. The oxidation prevention caps inhibit oxidation of the barrier layer during fabrication of the bump assemblies.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Tiao Zhou, Arkadii V. Samoilov
  • Patent number: 8085550
    Abstract: A method and a surface mount technology (SMT) pad structure are provided for implementing enhanced solder joint robustness. The SMT pad structure includes a base SMT pad. The base SMT pad receives a connector for soldering to the SMT pad structure. A standoff structure having a selected geometry is defined on the base SMT pad to increase thickness of the solder joint for the connector.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mark Kenneth Hoffmeyer, Steven Paul Ostrander, Sri M. Sri-Jayantha
  • Patent number: 8054640
    Abstract: An electronic apparatus includes: a circuit board that is disposed inside a case that is formed by coupling first and second case halves, the circuit board being interposed between first and second boss portions; first and second conductive members that are disposed between a gap formed between the first boss portion and the circuit board; a third conductive member that is disposed between the first boss portion and the first conductive member and between the first boss portion and the second conductive member to electrically connect the first conductive member to the second conductive member; and a measurement circuit that is electrically connected to a first wiring and a second wiring, which are respectively connected to the first conductive member and the second conductive member, and measures an electrical characteristic value of at least one of the first conductive member and the second conductive member.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: November 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Monda, Minoru Mukai
  • Patent number: 8035979
    Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: October 11, 2011
    Assignees: CMK Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Yutaka Yoshino, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
  • Publication number: 20110235290
    Abstract: The invention relates to an electrical circuit assembly (1), particularly for a control device of a motor vehicle, having a first circuit board (2), at least one second circuit board (3) and at least one holder (4) for holding the second circuit board (3) on the first circuit board (2), producing an electrical contact (6) between the first (2) and the second (3) circuit boards. According to the invention, the second circuit board (3) is preassembled on the holder (4) and the preassembled unit (5), comprising the second circuit board (3) and holder (4), is connected to the first circuit board (2), wherein the holder (4) and the second circuit board (3) are arranged crosswise, particularly at a right angle, to the first circuit board (2). The invention furthermore relates to a control device and to a method for producing an electrical circuit assembly (1).
    Type: Application
    Filed: November 25, 2009
    Publication date: September 29, 2011
    Applicant: ROBERT BOSCH GMBH
    Inventors: Volker Luhr, Markus-Alexander Schweiker, Rene Kloetzig, Andrea Voeth
  • Patent number: 7974104
    Abstract: A printed wiring board having an insulating base material; a wiring formed on at least one surface of the insulating base material, the wiring forming a predetermined circuit pattern; a first connection terminal portion formed on the surface and electrically connected to the wiring, the first connection terminal portion having a first width; a second connection terminal portion formed on the surface and electrically connected to the wiring, the second connection terminal portion having a second width; and a cover layer configured to cover the wiring and expose the first and the second connection terminal portion.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: July 5, 2011
    Assignee: Fujikura Ltd.
    Inventors: Tomofumi Kitada, Hiroki Maruo
  • Patent number: 7946869
    Abstract: The present disclosure is directed to conductive connector attachments for use in electrically connecting printed circuit boards to absorbent products such as diapers, training pants, incontinence products, feminine hygiene products, and the like. Specifically, various configurations and methods of securely attaching conventional conductive hook and loop attachments to printed circuit boards are disclosed.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: May 24, 2011
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Thomas Michael Ales, Davis-Dang Hoang Nhan
  • Patent number: 7937832
    Abstract: A wired circuit board having improved adhesion between the conductive pattern and an insulating layer to prevent a plating solution from remaining between a metal plating layer and the insulating layer. The invention prevents ionic impurities in the plating solution from remaining as residual or ionic contamination, thereby preventing a short circuit from developing when electric current flows through the circuit under a high temperature and high humidity environment. Lower end portions of the terminal portions that are formed on an insulating base layer and lower end portions of side surfaces and metal plating layers that cover the terminal portions are embedded in the insulating base layer in a flexible wired circuit board.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: May 10, 2011
    Assignee: Nitto Denko Corporation
    Inventors: Takashi Oda, Yasufumi Miyake, Tadao Ohkawa
  • Patent number: 7911343
    Abstract: A method for mounting multiple small RFID chips onto larger antenna. The chips are mechanically aligned with an interdigitated gap at the feed point of the antenna by electrostatic or magnetic techniques. In an alternate embodiment RF field coupling between the chips and the antenna is employed.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: March 22, 2011
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Court E. Rossman, Zane Lo, Roland A. Gilbert, John A. Windyka
  • Patent number: 7912520
    Abstract: A mobile phone having a body including a ground portion, a cover of a metallic material coupled to the body, the cover forming an exterior surface of the mobile phone, and a grounding unit electrically connecting the ground portion of the body to the cover, the grounding unit being disposed on one of facing surfaces of the body and the cover. Since the body and the metallic cover are electrically and stably connected with each other, a wireless communication characteristic of the mobile phone is prevented from being lowered.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: March 22, 2011
    Assignee: LG Electronics Inc.
    Inventors: Byung-Sung Choi, Sang-Ki Hong, Sung-Min Kim
  • Publication number: 20110044017
    Abstract: An electronic component has a printed substrate having a die bonding portion, a semiconductor element rigidly bonded to the die bonding portion of the printed substrate by a die bonding resin, and a wire bonding terminal formed by a conductor pattern on the printed substrate that is connected to the semiconductor element by a bonding wire. A groove portion located at a level lower than the conductor pattern of the printed substrate is formed in a region located on at least a die bonding portion side in a region surrounding the wire bonding terminal.
    Type: Application
    Filed: February 18, 2009
    Publication date: February 24, 2011
    Applicant: OMRON CORPORATION
    Inventors: Kazuyuki Ono, Yoshio Tanaka, Kiyoshi Nakajima, Naoto Kuratani, Tomofumi Maekawa
  • Patent number: 7894200
    Abstract: The present invention provides a printed wiring board with a built-in semiconductor element in which an insufficient or excessive amount of filled sealing material does not affect excellent adhesion of the printed wiring board to an overlying wiring board. The printed wiring board with a built-in semiconductor element comprises a built-in semiconductor element, in which at least the lower surface, the upper surface, or the side surface of the semiconductor element is covered with an insulating film, and an insulating layer is provided in the side and upper portions of the semiconductor element.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: February 22, 2011
    Assignees: CMK Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Yutaka Yoshino, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
  • Patent number: 7889514
    Abstract: A semiconductor device comprising a flat wiring board, a first LSI disposed on one surface of the wiring board, a sealing resin for covering the one surface and a side face of the first semiconductor element, and a second LSI disposed on another surface of the wiring board. The wiring board has conductive wiring as a wiring layer, an insulation resin as a support layer for the wiring layer, and a conductive through-hole that passes through the wiring layer and the support layer. Connection points between lands disposed in positions in which the external peripheral edges of the semiconductor elements transverse the interior of the lands as viewed vertically from above, which lands are selected from land portions on which the external connection terminals are formed, and the wiring board formed in the same plane as the lands, are unevenly distributed toward one side of the wiring board.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: February 15, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Yoichiro Kurita, Koji Soejima
  • Publication number: 20100321908
    Abstract: The present invention provides an electronic circuit device that can be downsized, a production method thereof, and a display device. The present invention is an electronic circuit device including: an electronic first component; an electronic second component; an electronic third component; an anisotropic first conductive layer; and an anisotropic second conductive layer, wherein the electronic first component is connected to the electronic third component via the anisotropic first conductive layer, and the electronic second component is connected to the electronic third component via the anisotropic first conductive layer and the anisotropic second conductive layer, the anisotropic first conductive layer and the anisotropic second conductive layer being stacked in this order on the electronic third component.
    Type: Application
    Filed: October 19, 2007
    Publication date: December 23, 2010
    Inventor: Motoji Shiota
  • Patent number: 7829793
    Abstract: An additive process disk drive suspension interconnect, and method therefor is provided. The interconnect has a metal grounding layer of typically stainless steel or copper metallized stainless steel, a metal conductive layer and an insulative layer between the metal grounding layer and the conductive metal layer. A circuit component such as a slider is electrically connected to the conductive layer along a grounding path from the circuit component and the conductive layer to the metal grounding layer through an aperture in the insulative layer. For improved electrical connection a tie layer is provided through the insulative layer onto the grounding layer in bonding relation with the ground layer. A conductor is deposited onto both the conductive metal layer and the tie layer in conductive metal layer and tie layer bonding relation, and the circuit component is thus bonded to the grounding layer by the conductor.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: November 9, 2010
    Assignee: Magnecomp Corporation
    Inventors: Christopher Schreiber, Christopher Dunn
  • Patent number: 7817441
    Abstract: Provided is a circuit board including: a circuit board body with at least one surface having a plurality of electrically connecting pads; an insulating protection layer formed on the circuit board body and formed with an opening corresponding in position to one of the electrically connecting pads, being larger than the electrically connecting pad, and not being in contact with the periphery of the electrically connecting pad; and a soldering material formed on, and confined to, the electrically connecting pad; thus allowing an electrically conductive element limited in the opening formed in the insulating protection layer to be fabricated from the soldering material by a reflow process with a view to forming a fine-pitch electrically connecting structure.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: October 19, 2010
    Assignee: Unimicron Technology Corp.
    Inventor: Shih-Ping Hsu
  • Patent number: 7796401
    Abstract: A chip element according to this invention can reduce the influence of parasitic capacitance and parasitic inductance when used in a GHz band. A substrate is formed of a low permittivity material having a permittivity low enough to reduce parasitic capacitance in a GHz band. Parasitic capacitance inherent to the chip element is reduced.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: September 14, 2010
    Assignee: Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akihiro Morimoto
  • Patent number: 7781679
    Abstract: A disk drive suspension interconnect, and method therefor. The interconnect has a metal grounding layer, a metal conductive layer and an insulative layer between the metal grounding layer and the conductive metal layer. A circuit component such as a slider is electrically connected to the conductive layer along a grounding path from the circuit component and the conductive layer to the metal grounding layer through an aperture in the insulative layer. For improved electrical connection a tie layer is provided through the insulative layer onto the grounding layer in bonding relation with the ground layer. A conductor is deposited onto both the conductive metal layer and the tie layer in conductive metal layer and tie layer bonding relation, and the circuit component is thus bonded to the grounding layer by the conductor.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: August 24, 2010
    Assignee: Magnecomp Corporation
    Inventors: Christopher Schreiber, Christopher Dunn
  • Patent number: 7660129
    Abstract: There is provided a printed circuit board in which a PCB and an FPC can be readily located, a solder connection structure and method between a printed circuit board and a flexible printed circuit board. The printed circuit board 1 includes a plurality of pads 2 for mounting a flexible printed circuit board, wherein a solder resist 3 is formed on the surface of the printed circuit board so as to expose the pads 2 and convex portions are formed by insulation print layers 4 around the pads 2.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: February 9, 2010
    Inventors: Yuuji Minota, Yasuhiro Fukutomi, Motonobu Koike
  • Patent number: 7626829
    Abstract: This invention provides a multilayer printed wiring board in which electric connectivity and functionality are obtained by improving reliability and particularly, reliability to the drop test can be improved. No corrosion resistant layer is formed on a solder pad 60B on which a component is to be mounted so as to obtain flexibility. Thus, if an impact is received from outside when a related product is dropped, the impact can be buffered so as to protect any mounted component from being removed. On the other hand, land 60A in which the corrosion resistant layer is formed is unlikely to occur contact failure even if a carbon pillar constituting an operation key makes repeated contacts.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: December 1, 2009
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasuhiro Watanabe, Michimasa Takahashi, Masakazu Aoyama, Takenobu Nakamura, Hiroyuki Yanagisawa
  • Patent number: 7622184
    Abstract: A stack of 50 layers of a first pitch-base carbon fiber sheet is formed, two sets of stack each having two second pitch-base carbon fiber sheets stacked therein are fabricated. At this time, the second carbon fiber sheets have a thermal expansion coefficient larger than that of the first carbon fiber sheet. Next, the stack of the first carbon fiber sheet is then held between two sets of stack of the second carbon fiber sheets. The stack of the first and second carbon fiber sheets are then impregnated with an epoxy-base resin composition and the resin is solidified. As a result a prepreg composed of the first and second carbon fiber sheets and the resin component composed of the epoxy-base resin composition is obtained. Thereafter, interconnections and the like are then formed on the prepreg, to thereby complete a multilevel interconnection board.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: November 24, 2009
    Assignee: Fujitsu Limited
    Inventors: Keishiro Okamoto, Mamoru Kurashina, Tomoyuki Abe
  • Patent number: 7602613
    Abstract: A flexible circuit has contacts for mounting in a socket or card edge connector. The flexible circuit includes integrated circuit devices mounted on both sides of the edge connector contacts. Preferably, the flexible circuit is wrapped about an edge of a rigid substrate and presents contacts on both sides of the substrate for mounting in a socket. Multiple flexible circuits may be overlaid with the same strategy. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: October 13, 2009
    Assignee: Entorian Technologies, LP
    Inventors: Paul Goodwin, James W. Cady, Douglas Wehrly
  • Publication number: 20090224397
    Abstract: A substrate with reduced substrate warpage and a semiconductor package utilizing the substrate are revealed. The substrate primarily comprises a core where a wiring layer and a first solder mask are formed on one surface of the core, and a second solder mask and a die-attaching layer are formed on the other surface of the core. The first solder mask has a thickness difference with respect to the second solder mask in a manner to reduce the warpage of the substrate caused by thermal stresses due to temperature differences can be well under control. Therefore, the manufacturing cost of the substrate can be lower without adding extra stiffeners to achieve substrate warpage control during semiconductor packaging processes.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Inventor: Wen-Jeng FAN
  • Patent number: 7532481
    Abstract: A base plate for a power module includes: a metal plate, a ceramic base plate joined to the metal plate, and a release agent which includes boron provided in a joint surface between the metal plate and the ceramic base plate. A remaining amount of the release agent is less than 5, as an amount of boron measured by fluorescence X-ray analysis, where the amount of boron is defined as a value obtained by an expression: (a peak height of B-K?/a peak height of X-K?) x 100000 and a crystal grain straining region in the joint surface is equal to or less than 40%, or an amount of crystal grain straining in the joint surface is equal to or less than 0.03%.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: May 12, 2009
    Assignee: Mitsubishi Materials Corporation
    Inventors: Toshiyuki Nagase, Yoshiyuki Nagatomo, Kazuaki Kubo, Takeshi Negishi
  • Patent number: 7522425
    Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: April 21, 2009
    Assignee: Entorian Technologies, LP
    Inventor: Paul Goodwin
  • Patent number: 7511966
    Abstract: According to one embodiment, first to fourth pads are arranged on a surface mounting area of a printed circuit board along one side of the mounting area, with a preset gap defined between each pair of adjacent ones of the pads. The first to third pads form a first land, and the second to fourth pads form a second land. When a first three-terminal regulator IC is mounted on the first land, a radiator-side terminal pin incorporated in the regulator IC is connected to a first radiator pad and a common radiator pad. When a second three-terminal regulator IC is mounted on the second land, a radiator-side terminal pin incorporated in the regulator IC is connected to a second radiator pad and the common radiator pad.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 31, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Norikuni Noguchi
  • Publication number: 20090015778
    Abstract: The present invention is related to a liquid crystal display (“LCD”) and a method thereof. The LCD includes a liquid crystal (“LC”) panel assembly including a plurality of pixels, a backlight unit providing light to the LC panel assembly, a printed circuit board (“PCB”) mounted with a plurality of circuit elements that control the backlight unit and includes a plurality of pads connected to the backlight unit, and a plurality of metal pieces attached to the pads. The metal pieces are attached when mounting the circuit elements.
    Type: Application
    Filed: January 3, 2008
    Publication date: January 15, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Ju-Sung CHO, Moon-Shik KANG
  • Publication number: 20090002963
    Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Inventors: Robert C. Cooney, Joseph M. Wilkinson
  • Patent number: 7455915
    Abstract: Application of a conductive material with a compliant underlayer onto selected pads of a substrate, includes forming at least one padstack, by patterning a sheet including a stack of material layers. Padstacks may include a first conductive top layer, one or more underlying layers, and a bottom attachment layer, such as a solder layer. At least one flexible, or compliant, layer is disposed in the sheet between the top and attachment layers. The compliant layer may be a conductive elastomer. The top layer of the padstacks are adhered to a soluble tape, and this composite structure is moved into place over the circuit board by means of a pick and place operation. The placement of the padstacks is followed by a solder reflow to adhere the padstacks to the contact pads of the substrate, and by a wash cycle with a solvent to remove the soluble tape.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: November 25, 2008
    Inventor: Morgan T. Johnson
  • Publication number: 20080253098
    Abstract: An assembly. The assembly reduces damage to a related electronic package during attachment to a related electronic interconnect structure. The assembly includes an interposer. The interposer has a first side and an opposing second side and has multiple holes formed in the interposer that extend from the first side to the second side. The electronic package is configurable to comprise one or more electronic structures; the interposer is configured for placement between the electronic package and the electronic interconnect structure; the locus of a wall of each of the holes is configured to facilitate insertion of a matching coupling component configured for electrically coupling the electronic package to the electronic interconnect structure; the wall of each hole is configured to provide complete encirclement of that hole; and the interposer mechanically inhibits physical contact between the electronic package and the electronic interconnect structure.
    Type: Application
    Filed: April 13, 2007
    Publication date: October 16, 2008
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Weifeng Liu
  • Patent number: 7417197
    Abstract: A power transfer pad, having: a non-conductive board having a top and a bottom; a plurality of conductive substrate sections disposed across the top of the non-conductive board; at least one conducting element disposed on each of the conductive substrate sections; a plurality of electrical contacts on the bottom of the non-conductive board, wherein each of the electrical contacts on the bottom of the non-conductive board are in electrical communication with one of the conductive substrate sections on the top of the non-conductive board.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: August 26, 2008
    Assignee: Medconx, Inc.
    Inventors: Harold B. Kent, James J. Levante
  • Publication number: 20080144299
    Abstract: A printed circuit board having only one circuit element, said circuit element having one or more leads and each lead being in electrical communication to one end of a trace on the printed circuit board, wherein said trace has a second end terminating at a pad, wherein said pad is in electrical communication with a receptacle capable of receiving and retaining a wire.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 19, 2008
    Inventor: Frank E. Redmond
  • Publication number: 20080137315
    Abstract: An electronic component device includes a wiring substrate having a wiring pattern, an electronic component mounted on the wiring pattern of the wiring substrate and provided with an electrode arranged on a side surface thereof, and a gold bump provided on the wiring pattern in side neighborhood of the electrode of the electronic component and bonded to the electrode of the electronic component and the wiring pattern, and the electrode of the electronic component is electrically connected to the wiring pattern through the gold bump, and the gold bump is formed by a wire bump method.
    Type: Application
    Filed: November 13, 2007
    Publication date: June 12, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Eiji Takaike
  • Publication number: 20080130255
    Abstract: According to one embodiment, first to fourth pads are arranged on a surface mounting area of a printed circuit board along one side of the mounting area, with a preset gap defined between each pair of adjacent ones of the pads. The first to third pads form a first land, and the second to fourth pads form a second land. When a first three-terminal regulator IC is mounted on the first land, a radiator-side terminal pin incorporated in the regulator IC is connected to a first radiator pad and a common radiator pad. When a second three-terminal regulator IC is mounted on the second land, a radiator-side terminal pin incorporated in the regulator IC is connected to a second radiator pad and the common radiator pad.
    Type: Application
    Filed: October 22, 2007
    Publication date: June 5, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Norikuni Noguchi
  • Patent number: 7349223
    Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: March 25, 2008
    Assignee: Nanonexus, Inc.
    Inventors: Joseph Michael Haemer, Fu Chiung Chong, Douglas N. Modlin
  • Publication number: 20080068814
    Abstract: An electronic equipment is provided with a housing which is assembled by combining first and second cases. The first and second cases are provided with first and second projections on inner surfaces of the first and second cases. A circuit board is located in the housing, which has a hole having a diameter larger than those of the first and second projections. The first and second projections are so engaged with each other as to be inserted in the hole. Stoppers are provided around the first and second projections so as to form gaps between first and second projections and the circuit board.
    Type: Application
    Filed: September 7, 2007
    Publication date: March 20, 2008
    Inventors: Tomoko Monda, Minoru Mukai
  • Patent number: 7294928
    Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: November 13, 2007
    Assignee: Tessera, Inc.
    Inventors: Kyong-Mo Bang, David Gibson, Young-Gon Kim, John B. Riley
  • Patent number: 7265994
    Abstract: A self supported underfill film (18) adhesively bonds surface mount integrated circuit packages (14) to a printed circuit board (10). The printed circuit board has conductive traces (12) and exposed conductive pads (13) on the surface. A film adhesive is strategically positioned on the printed circuit board near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads (16) on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: September 4, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Janice Danvir, Katherine Devanie, Nadia Yala
  • Publication number: 20070195512
    Abstract: Provided is a connector sheet exhibiting requisite conduction property for removal of electromagnetic wave noise and static electricity, allowing ground connection between a metal portion of a casing and a circuit board through a simple mounting operation, and capable of meeting requirement for a reduction in electronic apparatus size, and a portable electronic apparatus equipped with the same. The connector sheet is conductively connected to a metal casing and a ground-connecting portion of a circuit board through a conducting portion of a connector portion in which conductive particles are serially oriented. Further, the connector portion and a resin sheet are integrated with each other.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 23, 2007
    Applicant: Polymatech Co., Ltd.
    Inventor: Hideaki Konno
  • Patent number: 7180181
    Abstract: A substrate is provided for carrying at least a semiconductor device. The substrate mainly includes a carrier body, a plurality of contact pads, a solder mask and a plurality of dams of a mesh. The contact pads are disposed on a surface of the carrier body and each has a bonding surface exposed out of the solder mask for connecting with the external terminals of the semiconductor device. The dams are disposed above the surface of the carrier body. The dams protrude from and located between the bonding surfaces of the contact pads to prevent solder paste, flux or the external terminals of the semiconductor device from bridging.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: February 20, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pai-Chou Liu, Sheng-Tsung Liu, Wei-Chang Tai
  • Patent number: 7038142
    Abstract: The circuit board for mounting semiconductor elements comprises a core substrate 10 formed of a fiber reinforced metal, an insulating layer 14 formed on the core substrate 10, and an interconnection layer 20 formed on the insulating layer 14, whereby the circuit board for mounting semiconductor elements can have a thermal expansion coefficient approximate to that of silicon, and light and thin but has high rigidity.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: May 2, 2006
    Assignee: Fujitsu Limited
    Inventor: Tomoyuki Abe