Shaped Lead On Components Patents (Class 361/773)
  • Patent number: 8379402
    Abstract: A wiring board having a lead pin is provided. The wiring board having the lead pin includes a connecting pad which is formed on the wiring board, and to which the lead pin is bonded through a conductive material. The lead pin includes: a shaft portion; a head portion which is provided on one end of the shaft portion; a protruded portion which is formed on a surface side of the head portion opposed to the connection pad; and a first taper portion which is formed between the head portion and a base part of the shaft portion.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: February 19, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiro Oshima, Yoshikazu Hirabayashi, Shigeo Nakajima, Yoshitaka Matsushita
  • Patent number: 8355262
    Abstract: An electronic component is provided between at least two wiring boards. An electrode of the electronic component is electrically connected to at least one of the wiring boards. Also, the wiring boards and are electrically connected to each other. Additionally, the gap between the wiring boards and is sealed with a resin. The electronic component built-in substrate is featured in that a bonding pad formed on one of the wiring boards and is electrically connected to an electrode of the electronic component by a bonding wire, and that at least a connection portion between the electrode of the electronic component and the bonding wire is coated with a protection material.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: January 15, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akinobu Inoue, Haruo Sorimachi
  • Patent number: 8345441
    Abstract: A microelectronic assembly can include first and second microelectronic packages mounted to respective first and second opposed surfaces of a circuit panel. Each microelectronic package can include a substrate having first and second apertures extending between first and second surfaces thereof, first and second microelectronic elements each having a surface facing the first surface of the substrate and a plurality of contacts at the surface of the respective microelectronic element aligned with at least one of the apertures, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between the contacts of each microelectronic element and the terminals. The apertures of each substrate can have first and second parallel axes extending in directions of the lengths of the respective apertures. The terminals of each microelectronic package can be configured to carry all of the address signals transferred to the respective microelectronic package.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: January 1, 2013
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8315065
    Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. For example, the positive features on one of the surfaces may include pairs of counterposed micro-springs, and the negative features may include pits or grooves on the other surface. When the substrates are mechanically coupled, a given pair of positive features may provide a force in a plane of the other surface. Furthermore, by compressing the MCM so that the surfaces of the substrates are pushed toward each other, the mechanical coupling may be released.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: November 20, 2012
    Assignee: Oracle America, Inc.
    Inventors: Jing Shi, Hiren D. Thacker, Ashok V. Krishnamoorthy
  • Patent number: 8310838
    Abstract: An electric drive (1) with a circuit board (2), having conductor tracks (3) and contact openings (4) with plated through-holes (5) and equipped with electronic components (6), the circuit board (2) being coated with a protective layer (7) of insulating material, and press-fit contacts (8) are inserted into the contact openings (4) and in electrical contact areas (9) within the contact openings (4) electrical contact exists between a press-fit contact (8) and the plated through-hole (5) of the contact opening (4). The task of the invention is to reliably protect circuit boards of electric drives exposed to moisture and other chemical environmental effects and contact them economically.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 13, 2012
    Assignee: Bühler Motor GmbH
    Inventor: Helmut Kellermann
  • Patent number: 8304665
    Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 6, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Yen-Ping Wang, Don-Son Jiang, Jeng-Yuan Lai, Yu-Po Wang
  • Publication number: 20120262931
    Abstract: An anisotropic conductive adhesive including conductive particles dispersed in an epoxy-based adhesive containing an epoxy compound and a curing agent gives a cured product having the elastic modulus satisfying the expressions (1) to (5), in which EM35, EM55, EM95, and EM150 are values of the elastic modulus of the cured product at 35° C., 55° C., 95° C., and 150° C., respectively, ?EM55-95 is the rate of change in the elastic modulus between 55° C. and 95° C., and ?EM95-150 is the rate of change in the elastic modulus between 95° C. and 150° C., 700 MPa?EM35?3000 MPa??(1) EM150<EM95<EM55<EM35??(2) ?EM55-95<?EM95-150??(3) 20%??EM55-95??(4) 40%??EM95-150??(5).
    Type: Application
    Filed: January 15, 2010
    Publication date: October 18, 2012
    Applicant: SONY CHEMICAL & INFORMATION DEVICE CORPORATION
    Inventors: Hidetsugu Namiki, Shiyuki Kanisawa, Genki Katayanagi
  • Patent number: 8279028
    Abstract: An electromagnetic relay including a body, a plurality of first surface-mount terminals projecting from the body, and at least one second terminal projecting from the body. Each first terminal includes a distal end portion adapted to be mounted on a surface of a circuit board. The second terminal includes a distal end portion adapted to be inserted into a through-hole of a circuit board. The distal end portion of the second terminal is positioned farther away from the body than the distal end portion of the first terminal.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: October 2, 2012
    Assignee: Fujitsu Component Limited
    Inventors: Kenichi Yokoyama, Shigemitsu Aoki
  • Patent number: 8274798
    Abstract: A carrier substrate includes a substrate having a chip side and a PCB side, a plurality of bond pads disposed on the chip side for bonding a chip, a plurality of land grid array (LGA) pads disposed on the PCB side, and a plurality of resilient flanges installed on the PCB side in an array manner. The plurality of resilient flanges electrically connects with the LGA pads correspondingly.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: September 25, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Shih-Jung Huang, Wen-Fang Liu, Ling-Kai Su
  • Publication number: 20120182705
    Abstract: A printed circuit board according to one example embodiment includes a Z-directed component mounted in a mounting hole in the printed circuit board. The Z-directed component includes a body having a top surface, a bottom surface and a side surface. A portion of the body is composed of an insulator. The Z-directed component has at least one conductive channel therethrough. An integrated circuit is mounted on a surface of the printed circuit board. The integrated circuit is positioned directly above the Z-directed component and is electrically connected to the at least one conductive channel of the Z-directed component.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 19, 2012
    Inventor: Keith Bryan Hardin
  • Publication number: 20120170237
    Abstract: An assembly including: a first substrate having a first surface and housing a first electrical-interconnection element and a second electrical-interconnection element in a position corresponding to the first surface; a second substrate having a second surface, housing a third electrical-interconnection element and a fourth electrical-interconnection element in a position corresponding to the second surface, and provided with a dielectric layer extending on top of the third interconnection element; and a first bump and a second bump made of conductive material, extending between the first electrical-interconnection element and the third electrical-interconnection element and, respectively, between the second electrical-interconnection element and the fourth electrical-interconnection element, at least partially aligned to the respective electrical-interconnection elements, the first bump being ohmically coupled to the first interconnection element and capacitively coupled to the third interconnection element,
    Type: Application
    Filed: December 22, 2011
    Publication date: July 5, 2012
    Applicant: STMicroelectronics S.r.l.
    Inventors: Roberto Canegallo, Mauro Scandiuzzo
  • Patent number: 8212156
    Abstract: An enhanced contact metallurgy construction for plastic land grid array (PLGA) modules and printed wiring boards (PWBs). The PWB may, for example, have subcomposite laminate construction and/or a double-sided LGA site. A plurality of preform contacts are each respectively soldered to one of a plurality of metal pads on a PLGA module carrier and/or a PWB. Each of the preform contacts comprises a metal preform base (e.g., copper, nickel) soldered to one of the plurality of metal pads and an electrolytic noble metal plating (e.g., gold) over the metal preform base. An electrolytic non-noble metal underplating (e.g., nickel) may be interposed between the metal preform base and the electrolytic noble metal plating. In one embodiment, the electrolytic non-noble metal underplating is 80-400 microinches thick to provide an enhanced diffusion barrier, and the electrolytic noble metal plating is 30-60 microinches thick and incorporates one or more hardening agents to provide enhanced wear and corrosion resistance.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: William Louis Brodsky, Mark Kenneth Hoffmeyer
  • Patent number: 8183607
    Abstract: A semiconductor device features a semiconductor chip including a MOSFET, a first electrode of the MOSFET disposed on an obverse surface of the chip, a second, control electrode of the MOSFET disposed on the obverse surface, a third electrode of the MOSFET disposed on a second, opposing surface of the chip, first, second, and third conductive members, each having top surface and opposing bottom surface, the first, second, and third conductive members connecting with the first, second, and third electrodes electrically, respectively, a sealing body having top and bottom surfaces and sealing parts of the first, second, and third conductive members, the first conductive member having first, second, and third contiguous portions, the first portion is positioned over the first electrode, the second is positioned between the first and second portions and the third portion is positioned under the obverse surface of the chip.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: May 22, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20120113610
    Abstract: A circuit board includes a first circuit area, a first processing unit and a conductive pattern. The first circuit area includes a plurality of first electrically contacts. The first processing unit, which includes a ball grid array (BGA) substrate, is disposed on the first circuit area and is electrically connected to the first electrically contacts. The BGA substrate has a plurality of solder balls and a bypass circuit. The conductive pattern is electrically connected to the first electrically contacts.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 10, 2012
    Inventors: Chia-Chan HU, Yuan-Ming Hsu
  • Patent number: 8159827
    Abstract: When U-shape formed electronic components having an axial lead shape are mounted upright on a printed board, two U-shape formed electronic components having an axial lead shape are arranged so as not to be in the same straight line, and a wiring pattern is formed in a state where bent-side lead wires have the same electric potential, and the electronic components are inclined so as to place the bent-side lead wires close to each other, whereby the electronic components that tend to fall in the inclined direction can be mutually supported by the bent-side lead wires. Thus, the electronic components can be prevented from falling without spoiling a heat dissipation performance of the electronic component and the board, and without greatly deteriorating an assembly performance of the board.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: April 17, 2012
    Assignee: Mitsubishi Electric Company
    Inventor: Hitoshi Kidokoro
  • Patent number: 8159825
    Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.
    Type: Grant
    Filed: August 18, 2007
    Date of Patent: April 17, 2012
    Assignee: Hypres Inc.
    Inventor: Vladimir V. Dotsenko
  • Patent number: 8125058
    Abstract: An apparatus and method uses a first Faraday cage portion and a second Faraday cage portion to provide a Faraday cage enclosure surrounding at least one circuit device. For example, the first Faraday cage portion may include a first conductive portion of a Faraday cage enclosure surrounding the at least one circuit device, and a second Faraday cage portion may include a second conductive portion of the Faraday cage enclosure surrounding the at least one circuit device. Further, for example, the first Faraday cage portion may include a connection surface having one or more conductive contact portions terminating the first conductive portion of the Faraday cage enclosure the second Faraday cage portion may include a connection surface having one or more conductive contact portions terminating the second conductive portion of the Faraday cage enclosure. An electrical connection may be provided between the conductive contact portions of the first and second Faraday cage portions.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: February 28, 2012
    Assignee: Medtronic, Inc.
    Inventors: Tyler Mueller, Larry E. Tyler, Geoffrey Batchelder, Paul F. Gerrish, Michael F. Mattes, Anna J. Malin
  • Patent number: 8116089
    Abstract: A magnetic device surface mounting assembly includes a specially designed printed circuit board and magnetic device. The circuit board has first and second sets of channels, the first channels having a first end of a first size, a second end of a second size, and first and second sides at least one of which taper inward between the two ends to define an opening smaller than either size. The magnetic device includes a plurality of pins extending transversely with respect to the circuit board, and a plurality of legs extending parallel with the pins and sized to pass transversely through the first end of the first set of channels and to slide laterally through and resiliently engage the opening, but to prevent transverse movement with respect to the second end of the first set of channels.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: February 14, 2012
    Assignee: Universal Lighting Technologies, Inc.
    Inventors: Donald Folker, Mike LeBlanc
  • Patent number: 8081485
    Abstract: A component assembly includes an electric component with a body and a carrier substrate on which the component is fixed by means of a conductive adhesive layer. External electrical contacts that have a planar surface are arranged on the lower side of the body. The conductive adhesive acts upon the body in at least one contact region that is devoid of the external electrical contacts.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: December 20, 2011
    Assignee: EPCOS AG
    Inventor: Volker Wischnat
  • Patent number: 8067779
    Abstract: A light emitting device includes: a light emitting element; a first lead including a recess in one end portion, the recess including a first bottom surface with the light emitting element bonded thereto, at least one of a through hole and a notch, and a light shielding portion capable of suppressing leakage of emitted light from the light emitting element from the one of the through hole and the notch; a second lead opposed to the first lead; and a molded body filling the one of the through hole and the notch, covering the light emitting element, embedding at least part of the first lead and at least part of the second lead, and made of a translucent resin.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: November 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Muranaka, Masaki Adachi, Iwao Matsumoto, Kenji Naito, Toshiaki Hosoya
  • Patent number: 8058720
    Abstract: A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane between the leads and the die pad; a plurality of downset tie bars connecting the ground bar with the die pad; a plurality of ground wires bonding to both of the ground bar and the die pad; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: November 15, 2011
    Assignee: Mediatek Inc.
    Inventors: Nan-Jang Chen, Yau-Wai Wong
  • Patent number: 8059420
    Abstract: A surface mountable device includes a ceramic substrate including a first principal surface, a second principal surface, and a side surface connecting the first principal surface to the second principal surface, a terminal electrode disposed on the first principal surface, and a first conductor for appearance inspection extending continuously from the terminal electrode to the side surface and having a width smaller than the width of the terminal electrode.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: November 15, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yoshihiko Nishizawa
  • Patent number: 7989945
    Abstract: A connector for electrically connecting to pads formed on a semiconductor device includes a substrate and an array of contact elements of conductive material formed on the substrate. Each contact element includes a base portion attached to the top surface of the substrate and a curved spring portion extending from the base portion and having a distal end projecting above the substrate. The curved spring portion is formed to curve away from a plane of contact and has a curvature disposed to provide a controlled wiping action when engaging a respective pad of the semiconductor device.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: August 2, 2011
    Assignee: Neoconix, Inc.
    Inventors: John David Williams, Eric Michael Radza
  • Patent number: 7985991
    Abstract: A semiconductor device features a semiconductor substrate with a MOSFET, an electrode for main current of the MOSFET disposed on a first major surface of the substrate, an electrode for control of the MOSFET disposed on the first major surface, a rear plane electrode of the MOSFET disposed on a second, opposing surface of the substrate, and an external connection terminal electrically connected to the rear plane electrode, the external electrode contains a first part, a second part and a third part, the first part is positioned over the rear plane electrode, the third part is positioned below the second major surface and the third part is connected via the second part to the first part.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: July 26, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Patent number: 7978479
    Abstract: The present invention provides a SiP module for wireless local area network comprising a base. A control unit is formed on a first surface of the base and a RF front end components is formed on a second surface of the base and coupled to the control unit through the base. A plurality of group of bumps is arranged on the first surface and coupled to the control unit, and separated with one another to reduce the interference.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: July 12, 2011
    Assignee: Accton Technology Corporation
    Inventors: I-Ru Liu, Ting-Yi Tsai, Wen-Bing Luo
  • Patent number: 7944710
    Abstract: The disclosure involves the efficient termination of a winding PCB of a planar inductive component to a main PCB, using relatively little space and providing a low-resistance connection. The disclosed methods are especially suitable for planar structures where several winding PCBs, and/or winding PCBs and a main PCB, are all enclosed by the magnetic path components. The methods allow for a winding PCB to simply rest on the main PCB, or other winding PCBs, without any clearance. The disclosure employs mating sets of conductive annular rings with an optional interlocking terminal pin that allows two PCBs to be fixedly coupled together, while preserving a minimum distance between the solder-mask layers of the two PCBs in order to prevent the formation of unwanted electrical connections between the two PCBs. Solder is used to ensure effective coupling in each assembly of mating annular rings and optional terminal pin.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: May 17, 2011
    Assignee: Battery-Biz Inc.
    Inventors: Victor Marten, Aakar Patel, Mark Vanstone
  • Patent number: 7916496
    Abstract: According to an aspect of the present invention, there is provided a printed circuit board including: a semiconductor package including a parallelepiped body, and solder balls provided on a face of the parallelepiped body; a printed wiring board including a mounting face, the mounting face configured to mount the plurality of solder balls; a first bonding member including a first glass transition temperature, the first bonding member disposed around the parallelepiped body and configured to bond the semiconductor package and the printed wiring board; an electronic component mounted on the mounting face on an opposite side to the semiconductor package with respect to the first bonding member; and a second bonding member including a second glass transition temperature that is higher than the first glass transition temperature, the second bonding member disposed onto the mounting face to cover the electronic component.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: March 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takahiro Sugai
  • Patent number: 7902658
    Abstract: A semiconductor integrated circuit device described herein includes a semiconductor chip and a package on which the semiconductor chip is disposed. The semiconductor chip includes first electrode pads, and the package includes second electrode pads connected to the first electrode pads. The second electrode pads include signal pads and power supply pads, and are arranged in rows along the semiconductor chip. All the power supply pads of the second electrode pads are for supplying power to the semiconductor chip and are disposed in a row positioned farther from the semiconductor chip than another row. Each power supply line that leads out from a second power supply pad has a width not less than a width of the second power supply pad.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: March 8, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideho Inagawa
  • Patent number: 7885083
    Abstract: A circuit board assembly which includes an electrically insulating layer, a conductive printed wiring layer formed on the surface of the electrically insulating layer and includes a plurality of conductive paths, a conductive trace on the electrically insulating layer and apparatus for dissipating a transient in addition to a surface mount resistor fixed in relation to the trace. In some forms of the invention the surface mount resistor has opposed generally planar lips. The trace may also be generally planar. In some cases the lower lips and the trace are generally parallel. The generally planar lips of the surface mount resistor may be closer to the trace than the thickness of the surface mount resistor. A single geometric plane may extend through substantially all of the lips and all of the trace. In some cases the lower surface of the lips and the lower surface of the trace are substantially coplanar.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: February 8, 2011
    Assignee: Honeywell International, Inc.
    Inventors: Lance Weston, Edward L. Fontana, Larry A. Sternstein
  • Patent number: 7884288
    Abstract: A screened housing (1) with press-fit pins (2) for electrical contacting on an electrical support component, in particular for automobile application, is composed of two housing sections (14,15) each including a housing base (3) each with two housing edges (4) with press-fit pins (2). Above all a screened housing is achieved by the invention with press-fit pins around all four circumferential sides which can be produced simply and economically in a follow-on composite tool. Such screened housings are particularly suitable for automobile applications for screening electrical components from incoming or emitting electromagnetic radiation.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: February 8, 2011
    Assignee: Continental Automotive GmbH
    Inventors: Frank Meyer, Wolfgang Puscher
  • Patent number: 7821115
    Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Chihiro Sasaki, Yasuaki Iwata
  • Patent number: 7813142
    Abstract: A portable electronic device (20) includes a circuit board (21) and at least one conducting pole (22). The conducting pole is mounted on the circuit board and includes a breakable portion (2224), the breakable portion is configured to be the part that breaks when the conducting pole is crumpled.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: October 12, 2010
    Assignee: Chi Mei Communication Systems, Inc.
    Inventors: Kuan-Chang Lin, Ting-Chang Chang
  • Publication number: 20100214752
    Abstract: A wiring board has a substrate, a conductive pattern formed over the substrate, and an electronic component mounted to the substrate and having an electrode. The electrode of the electronic component is connected to the conductive pattern through a via hole. The thickness of the electrode of the electronic component is made less than the thickness of the conductive pattern.
    Type: Application
    Filed: August 19, 2009
    Publication date: August 26, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Keisuke Shimizu, Yoichiro Kawamura
  • Patent number: 7777309
    Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: August 17, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Tsutomu Tsuchiya
  • Publication number: 20100193948
    Abstract: The present invention relates to a connecting structure between semiconductor device 1 of a BGA type which has external electrode terminals 9 including column-like electrode 17, insulating layer 16 formed around the column-like electrode 17 and annular electrode 15 formed around the insulating layer 16, and a printed wiring board capable of mounting the semiconductor device 1 and including lower-layer electrode 28 to be soldered to column-like electrode 17 of the aforementioned external electrode terminal 9 and upper-layer electrode 27 to be soldered to annular electrode 15 of the aforementioned external electrode terminal 9. Column-like electrode 17 of semiconductor device 1 is soldered to lower-layer electrode 28 of printed wiring board 2. Annular electrode 15 of semiconductor device 1 is soldered to upper-layer electrode 27 of printed wiring board 2.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 5, 2010
    Applicant: NEC CORPORATION
    Inventor: Hironori Ohta
  • Patent number: 7766499
    Abstract: A light source unit including light emitting diodes mounted on a printed circuit board by not using a soldering method but a fitting method, and a backlight unit and liquid crystal display including the light source unit. The light source unit includes light emitting diodes including lead terminals and a printed circuit board including a fitting hole. Each of the lead terminals includes a base part and a fitting part protruding from the base part. The fitting part of the light emitting diode is fitted into the fitting hole of the printed circuit board and so that the light emitting diode is mounted on the printed circuit board.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: August 3, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Hee Park, Jung Tae Kang, Jin Ho Ha, Hyun Chul Bae, Joo Young Kim
  • Patent number: 7755911
    Abstract: A printed wiring board which can certainly prevent damage of conductive pattern caused by the terminal. The printed wiring board has a board, a conductive pattern, a through-hole and a non-conductive area. A lead wire of resistance mounted on the printed wiring board is inserted into the through-hole 4. The lead wire projects from a surface of the board, and is bent close to the surface. The non-conductive area is formed into a fan-shaped shape enlarging toward a tip of the lead wire from a center of the through-hole. Because the bent lead wire is arranged on the non-conductive area, the non-conductive area can prevent damage of the conductive pattern which is caused by touching the lead wire to the conductive pattern.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: July 13, 2010
    Assignee: Yazaki Corporation
    Inventors: Masaoki Yoshida, Takuya Nakayama, Koji Ueyama
  • Patent number: 7742313
    Abstract: Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: June 22, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mung Suan Heng, Kok Chua Tan, Vince Chan Seng Leong, Mark S. Johnson
  • Patent number: 7718902
    Abstract: The current invention provides a method of attaching a plurality of cores wherein a core has a via with a conductive surface to be electrically connected to a conductive surface on another core. The method provides for applying a metallurgical paste to a conductive surface, removing a portion of the flux from the paste and joining the two cores. The current invention also provides a structure including a plurality of cores wherein a metallurgical paste electrically connects a via with a conductive surface on a core to a conductive surface on another core.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Lisa J. Jimarez, Mark V. Pierson
  • Patent number: 7684205
    Abstract: The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: March 23, 2010
    Assignee: General Dynamics Advanced Information Systems, Inc.
    Inventor: Deepak K. Pai
  • Publication number: 20100014263
    Abstract: The present invention provides a liquid resin composition for electronic part sealing that is good in fluidity in a narrow gap, being free from void generation, and that excels in fillet formation; and an electronic part apparatus sealed thereby of high reliability (moisture resistance and thermal shock resistance). The liquid resin composition for electronic part sealing is characterized by comprising (A) an epoxy resin including a liquid epoxy resin, (B) a hardening agent including a liquid aromatic amine, (C) a hydrazide compound having an average particle diameter of less than 2 ?m, and (D) an inorganic filler having an average particle diameter of less than 2 ?m.
    Type: Application
    Filed: September 28, 2007
    Publication date: January 21, 2010
    Inventors: Satoru Tsuchida, Shinsuke Hagiwara, Kazuyoshi Tendou
  • Patent number: 7642467
    Abstract: An improved method for manufacturing a matching pair of electrodes comprises the steps of: fabricating a first electrode with a substantially flat surface; depositing islands of an oxidizable material over regions of the surface; depositing a layer of a third material over the surface of the first electrode to form a second electrode; separating the first electrode from the second electrode; oxidizing the islands of oxidizable material, which causes the islands to expand; bringing the upper electrode and the lower electrode into close proximity, whereupon the expanded island of oxidizable material touches the upper surface and creates an insulating gap between the two surfaces, thereby forming a matching pair of electrodes.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: January 5, 2010
    Assignee: Borealis Technical Limited
    Inventor: Avto Tavkhelidze
  • Patent number: 7629677
    Abstract: Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are electrically connected to the semiconductor chip. The encapsulant covers the semiconductor chip and the plurality of inner leads. The upper surfaces of the plurality of inner leads are fixed to the encapsulant, portions of the bottom surfaces of the plurality of inner leads are exposed from the encapsulant, and the bottom surfaces of the plurality of inner leads are disposed at a different height from a bottom surface of the encapsulant.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: December 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Pil Youn, Jong-Woo Ko, Jeong-Jin Lee
  • Patent number: 7618165
    Abstract: There is provided an LED lamp unit comprising an LED lamp, a protective component for an LED lighting circuit, a circuit section and a case part, characterized in that the circuit section has a metal plate which is embedded in the case part with its surface partially exposed, a lead of the LED lamp is electrically connected to the exposed surface of the metal plate, and the protective component for the LED lighting circuit is connected to the metal plate at an opposite side to a side where the lead of the LED lamp is connected.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: November 17, 2009
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takayuki Kamiya, Hideki Kokubu
  • Patent number: 7538441
    Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: May 26, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideho Inagawa
  • Patent number: 7532484
    Abstract: An electronic component assembly includes an electrical component assembled to a base and mounted to a support. The component electrical leads protrude through holes, along a channel, and make contact with connectors on the base. The base is formed of a polymeric material and contains protrusions for mechanically supporting the electrical component. When the base is mounted to the support, the connectors complete the electrical connection between the electrical component and the support.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: May 12, 2009
    Assignee: Delphi Technologies, Inc.
    Inventors: Steven L. Sailor, Hugh R. Hunkeler, Lee R. Hinze
  • Patent number: 7449370
    Abstract: In a semiconductor package including at least one plate-like mount, a semiconductor chip has at least one electrode formed on a top surface thereof, and is mounted on the plate-like mount such that a bottom surface of the semiconductor chip is in contact with the plate-like mount. The semiconductor package also includes at least one lead element having an outer portion arranged to be flush with the plate-like mount, and an inner portion deformed and shaped to overhang the semiconductor chip such that an inner end of the lead element is spaced apart from the top surface of the semiconductor chip. The semiconductor package further includes a bonding-wire element bonded at ends thereof to the electrode of the semiconductor chip and the inner end of the lead element, an enveloper sealing and encapsulating the plate-like mount, the semiconductor chip, the inner portion of the lead element, and the bonding-wire element.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: November 11, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Takekazu Tanaka
  • Patent number: 7425756
    Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: September 16, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Tsutomu Tsuchiya
  • Patent number: 7400002
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: July 15, 2008
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Patent number: 7394146
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: July 1, 2008
    Assignees: Renesas Tehcnology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa