Shaped Lead On Components Patents (Class 361/773)
  • Patent number: 6252178
    Abstract: A semiconductor device and method that provides for the manufacture of semiconductor devices using high temperature wire bonding in combination with build-up layers having a low glass transition temperature. Anchors are created to serve as thermal gateways, during wire bonding, for bonding pads located on the upper surface of the build-up layers. The anchors pass through the thickness of the build-up layers and contact the PCB core layer.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: June 26, 2001
    Assignee: Conexant Systems, Inc.
    Inventor: Hassan S. Hashemi
  • Patent number: 6246587
    Abstract: Surface mount device packages with increased mounting strength and a method therefor. In one embodiment, an electronic device is made up of a device package and one or more electrically conductive terminals. For surface mounting, the device terminals are each provided with a mounting surface which is bonded using a conductive adhesive to a corresponding contact pad on a circuit board. The terminals are further provided with at least one groove across the mounting surface. When conductive adhesive is used to mount the device on a circuit board, this groove serves to form the conductive adhesive into a ridge or “dam” over the contact pad. This provides increased mounting strength which may eliminate the need for additional adhesive material to provide side reinforcement of the device, and thereby allow an increase in the packing density of devices on the circuit board.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: June 12, 2001
    Assignee: Intermedics Inc.
    Inventor: Philip H. Chen
  • Patent number: 6239012
    Abstract: A vertically mountable semiconductor device including a plurality of bond pads disposed proximate to a single edge thereof. The bond pads are bumped with an electrically conductive material. The semiconductor device may also include a support member. Alternatively, the semiconductor device may be laminated to one or more adjacent semiconductor devices. The present invention also includes a method of attaching the semiconductor device to a carrier substrate. Preferably, solder paste is applied to terminals on the carrier substrate. The semiconductor device is oriented vertically over the carrier substrate, such that the bumped bond pads align with their corresponding terminals. The bumps are placed into contact with the solder paste. The bumps an older paste are then fused to form a joint between the each of the bond pads and their respective terminal, establishing an electrically conductive connection therebetween and imparting structural stability to the semiconductor device.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: May 29, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Larry D. Kinsman
  • Patent number: 6219247
    Abstract: A control unit for a motor vehicle has a base plate with press-fit openings. A conductor track carrier is mounted on the base plate. The conductor-track carrier has electrical contacting tabs in the area of the press-fit openings. An electrical contact pin that projects from a supporting body is inserted into a press-fit opening in the base plate and there contacts the contacting tab. By virtue of a reserve of material which is reduced (used) as the contact pin is pressed in, the contacting tab is anchored in the press-fit opening in an essentially tension-less manner.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: April 17, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Detlef Haupt, Frank Franzen
  • Patent number: 6215670
    Abstract: An electronic assembly. The electronic assembly includes a first substrate which has a first set of contact pads and a second substrate which has a second set of contact pads. A plurality of elongate, springable interconnection elements are located between the first substrate and the second substrate. Each of the plurality of elongate, springable interconnect elements is free standing and has a portion permanently attached to a respective contact pad of the first set of contact pads and has a second portion contacting a respective contact pad of the second set of contact pads. The first and the second substrates are brought into a fixed relationship relative to one another.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: April 10, 2001
    Assignee: FormFactor, Inc.
    Inventor: Igor Y. Khandros
  • Patent number: 6194656
    Abstract: In a mounting structure for a relay arranged on a printed circuit board, a resin block having at least one insert-molded bus bar is fixed on the printed circuit board. One end of the bus bar held by the resin block is joined together with a terminal of the relay by welding, while the other end of the bus bar is soldered to a printed wiring pattern formed on the printed circuit board. Therefore, a heat (temperature) of the terminal of the relay can be absorbed through the bus bar and the resin block.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: February 27, 2001
    Assignee: Yazaki Corporation
    Inventors: Youichi Kondo, Masataka Suzuki, Yasuyuki Watanabe
  • Patent number: 6163461
    Abstract: A terminal mounting structure for a printed circuit board according to the present invention comprises a printed circuit board having a wiring pattern and a slit formed in an end face of the board and a terminal connected to the wiring pattern on the board, the terminal being provided with a holding portion having first and second clamp pieces and a connection piece for connection between both clamp pieces, the connection piece being inserted into the slit formed in the printed circuit board to position the terminal with respect to the printed circuit board, and the first and second clamp pieces being connected to the wiring pattern.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: December 19, 2000
    Assignee: Alps Electric Co., Ltd.
    Inventor: Yoshikiyo Watanabe
  • Patent number: 6163460
    Abstract: An arrangement of electronic components in a housing includes a housing, at least one circuit board arranged in the housing with electronic components of a first type (such as SMDs) mounted thereon, at least one electronic component of a second type (such as a non-SMD coil or capacitor) that is not arranged on the circuit board but rather is mounted on a mounting surface in the housing, and an electrical connection established between the second electronic component and the circuit board. The electrical connection may be established by a connector member having two connecting shanks connected to the wires of the second component and two mounting shanks that are press-fit into contact holes of the circuit board. Alternatively, the electrical connection may be established by respective contact clips electrically and mechanically clamped onto the wires of the second component, whereby the contact clips have contact pins that plug into contact holes in the circuit board.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: December 19, 2000
    Assignee: Temic Telefunken microelectronic GmbH
    Inventors: Richard Baur, Guenter Fendt, Engelbert Woerle, Juergen Ryll
  • Patent number: 6163463
    Abstract: An interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate are formed. To form the interconnection, a metallization is formed on each of the substrate bonding contacts. Metal ball bond bumps are formed on selective ones of the bonding pads and then coined. The substrate and integrated circuit chip are heated. The coined ball bond bumps are then placed into contact with the corresponding metallizations, pressure and ultrasonic energy are applied, and a metal-to-metal bond is formed between each coined ball bond bump and the corresponding metallization.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: December 19, 2000
    Assignee: Amkor Technology, Inc.
    Inventor: Robert C. Marrs
  • Patent number: 6151220
    Abstract: Leads 106 provided at an electronic part connectors 110 of an electronic part 100, which are electrically connected to a surface of a substrate 120 are structured in such a manner that they are directly connected to a substrate connector formed at the surface of the substrate 120 through a pressing force or a bonding force applied to the electronic part 100. This lead structure makes it possible to preclude the use of connectors including additional members such as contact pins, to achieve a reduction in the length of the communicating path of the electrical signals, and in addition, since electrical connection is achieved at one location, i.e., between the leads 106 and the substrate connector at the substrate 120, the contact resistance is minimized.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: November 21, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Akira Sakamoto, Kazuhiko Sera, Kazunari Oyama
  • Patent number: 6137063
    Abstract: The present invention includes electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive. In one embodiment, an electrical interconnection configured to electrically couple a first substrate and a second substrate includes: a bond pad of the first substrate having a male configuration; and a bond pad of the second substrate having a female configuration, the bond pad of the second substrate being configured to mate with the bond pad of the first substrate during electrical connection of the bond pads of the first substrate and the second substrate. A method of conducting electricity according to the present invention includes providing first and second bond pads individually defining a planar dimension; coupling the first and second bond pads at an interface having a surface area greater than the area of the planar dimension; and conducting electricity between the first and second bond pads following the coupling.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: October 24, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Tongbi Jiang
  • Patent number: 6115254
    Abstract: A high density vertical surface mount package and thermal carrier therefor including a heat sink.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: September 5, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Jerry M. Brooks, Walter L. Moden
  • Patent number: 6101099
    Abstract: The present invention relates to a device and a method for electrical and mechanical connection of an electric high-power component (111) which transmits high-frequency electrical signals to conductors (120) on a circuit board (119). The component comprises connections (114) projecting over the circuit board and which are soldered to the conductors (120) on the circuit board (119) with a solder material (112) which essentially lacks grain growth. The component is subject to repeated temperature changes which leads to stresses on the connection between the connections (114) and the conductors (120). The length of the connections is selected depending on a predetermined threshold value for the highest acceptable attenuation which the high-frequency electrical signal is subject to when passing through the electrical high-power component via the connections. The connections can be shaped so that they comprise a bent part with a bending which is determined in dependence of said threshold value.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: August 8, 2000
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Christer Olsson
  • Patent number: 6093036
    Abstract: In a terminal connection device for a power supply circuit, a connecting lead member (4) has a straight bridge portion (4C) which includes a generally ring-like spin loop portion (5), and has an attachment terminal portion (4B) extending in a hook-shaped manner. The attachment terminal portion (4B) is inserted into a through hole (6) formed in a substrate (1) and fixedly connected by solder (7B) while the ring-like spin loop portion (5) is inserted into a corresponding slot (3) formed in the substrate (1) and securely held therein. The length (L) of the slot (3) is equal to or smaller than the outer diameter (D) of the spin loop portion (5) and the outermost of the spin loop portion comes into close contact with the inner side wall (3a) of the slot (3), and thus the finished terminal connection device can be made thin and small in size.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: July 25, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidenori Tohgo, Kazuya Chiba
  • Patent number: 6094356
    Abstract: A semiconductor device including a semiconductor chip, connection parts arranged along one end of the semiconductor chip, and external connection terminals connected to the connection parts.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: July 25, 2000
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Kazuhiko Mitobe, Katsuhiro Hayashida, Masaaki Seki, Seiichi Orimo, Toshio Hamano
  • Patent number: 6088236
    Abstract: A semiconductor unit including a circuit board having terminal electrodes on a surface thereof and a semiconductor device having an electrode pad on a first surface, where the semiconductor device is mounted face down on the surface of the circuit board. The semiconductor device has a plurality of bumps formed on the electrode pad, for electrically connecting the electrode pad to the terminal electrodes of the circuit board. Each bump includes a first bump portion and a smaller second bump portion formed on the first bump portion, and each second bump portion has a plurality of irregularities having concave portions extending in various directions. The bonding layer is formed between the second bump portion and the terminal electrode, and includes conductive particles which along with a portion of the bonding layer enter the concave portions of the plurality of irregularities of the bumps.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: July 11, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Tomura, Yoshihiro Bessho
  • Patent number: 6061247
    Abstract: The present invention includes a motor body and provided to this motor body a motor with attached control device having a control device which drives this motor body, wherein the capacitor attached to the control device of this motor with attached control device is provided with a freely attachable and removable mounting device. According to the present invention, the attachment and removal of the capacitor of the control device which requires relatively frequent replacement can be performed freely, enabling the replacement to be performed simply.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Nishizawa, Motoyasu Mochizuki, Yoshinobu Nakamura, Youichi Morishima, Yasuo Hirano
  • Patent number: 6061242
    Abstract: A semiconductor device having a die paddle and a die disposed on the die paddle. The die paddle serves as a heat dissipation device and the die paddle is partially and/or fully encapsulated by a package body. Thermal posts extend from the die paddle to direct heat from the semiconductor device to a printed circuit board and further provide stability and alignment during placement of the semiconductor device on the printed circuit board.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: May 9, 2000
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Walter L. Moden
  • Patent number: 6058020
    Abstract: A component housing for surface mounting of a semiconductor component on a component-mounting surface of a printed circuit board. The component housing including a chip carrier made of an electrically insulating material and having an approximately planar chip carrier area, a semiconductor chip, preferably having an integrated electronic circuit, secured on the chip carrier area, and electrode terminals having a surface-mountable configuration. The electrode terminals penetrating through the chip carrier and electrically connected to the semiconductor chip. A distance between the component-mounting surface of the printed circuit board and outer delimiting areas of the chip carrier which face the component-mounting surface of the printed circuit board increases continuously from an edge region to a central region of the chip carrier.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: May 2, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Jurgen Winterer, Gottfried Beer, Bernd Stadler
  • Patent number: 6054652
    Abstract: The thin-film multi-layer substrate includes an insulating substrate base plate, and a thin-film structure including a plurality of conducting layers and a plurality of insulating layers formed on the substrate base plate. A via structure is formed in the thin-film structure and connected to one of the conducting layers of the thin-layer structure. Pins are connected to the via structure, such that the bottom of the via structure is directly laminated on the substrate base plate, and the pins are secured onto the via structure.
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: April 25, 2000
    Assignee: Fujitsu Limited
    Inventors: Kiyokazu Moriizumi, Shunichi Kikuchi, Kazuhiro Nitta, Naomi Fukunaga, Mitsuo Suehiro
  • Patent number: 6055154
    Abstract: An integrated circuit chip cooling system includes a thermally conductive block on which the chip is directly mounted. The block is secured to a printed circuit board and is suspended into flowing coolant, with the chip being maintained out of contact with the coolant. The coolant is circulated to remove heat from the block.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: April 25, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: Kaveh Azar
  • Patent number: 6018285
    Abstract: A wire-wound component to be mounted on a printed circuit board. The wire-wound component is formed by winding a wire on the body of the wire-wound component and by winding both end portions of the wire on terminals. The terminals and the body of the wire-wound component are formed as one unit by molding same from a heat-resistant resin material. The molded terminals, on which both end portions of the wire are wound, are inserted into the printed circuit board, and then connected to a circuit pattern on the printed circuit board by soldering.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: January 25, 2000
    Assignee: Funai Electric Co., Ltd.
    Inventor: Osamu Maeda
  • Patent number: 6005777
    Abstract: A ball grid array capacitor has a substrate with a top and bottom surface and a via extending through the substrate. Several capacitors are located on the bottom surface. The capacitors include a top electrode connected to the via, a dielectric layer connected to the top electrode, and a bottom electrode that is connected to the dielectric layer and a ball pad over the bottom electrode. A passivation layer is located between the capacitors. Several solder spheres are electrically and mechanically connected to the bottom electrode. A resistor can be mounted on the top surface and connected to the via to form a filter.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: December 21, 1999
    Assignee: CTS Corporation
    Inventors: Terry R. Bloom, Richard O. Cooper, Robert L. Reinhard
  • Patent number: 5994648
    Abstract: An electrical circuit assembly which requires no solder processing, including an electronic component having terminations arranged on at least one of its surfaces, and a molded curviplanar substrate having circuit traces thereon and a cavity formed therein, wherein the cavity substantially conforms in shape with the electronic component. Proximate the cavity is a plurality of electrical contacts, arranged in matched relation with the respective terminations of the electronic component, with at least one of the electrical contacts being connected to at least one of the circuit traces on the substrate. The cavity and electrical contacts are dimensioned such that an interference fit is provided between the component's terminations and the electrical contacts, such that the component is held within the cavity when the component is placed therein. The component is disposed in the cavity such that its terminations are in physical and electrical connection with their respective electrical contacts.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: November 30, 1999
    Assignee: Ford Motor Company
    Inventors: Andrew Z. Glovatsky, Michael G. Todd, Cuong Van Pham
  • Patent number: 5982623
    Abstract: A module is provided for a packaged IC designed to radiate heat by sealing the packaged IC. At least outer lead parts the packaged IC which are mounted on an electronic circuit board are sealed by a sealing material of a high thermal conductivity to form a sealing part.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: November 9, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takahiro Matsuo, Yoshio Maruyama, Osamu Hikita, Shinji Kadoriku
  • Patent number: 5959840
    Abstract: An electrical component, mounted for example to a printed circuit board, is enclosed in a sealed chamber with an inert gas that permits the electrical leads of the electrical component to be formed from a material having high heat and electrical conductivity, such as silver, that is protected from corrosion and/or oxidation by the inert gas. The housing is fabricated from a heat conductive material, and heat is thereby drawn from the electrical leads for dissipation by the outer surface of the housing.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: September 28, 1999
    Assignee: Tandem Computers Incorporated
    Inventors: Tom W. Collins, William J. Avery, John S. Suy, David M. Tichane
  • Patent number: 5926375
    Abstract: A circuit board is provided with blind connection vias which are filled with solder. The end portions of the pins of an electronic component are inserted into the connection vias, and are connected to the connection vias by solder. The electronic component is surface mounted on the circuit board with the major portions of the pins exposed.
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: July 20, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Watanabe, Tsutomu Imai, Takeshi Yamaguchi, Tositada Netsu, Kenichi Kasai, Fumio Imahashi, Satoru Ezaki, Mitugu Shirai
  • Patent number: 5921820
    Abstract: In this Application, a description is given of a passive component comprising two electric connections with a plug-in portion for securing and electrically connecting the component to a printed circuit board, for example an electrolytic capacitor. In accordance with the invention, this component is so constructed that both plug-in portions are provided with two pins, with the plug-in portions being so positioned that the four pins do not extend in a flat plane. By virtue of the measure in accordance with the invention, resoldering of such components can be dispensed with. The use of pins whose length and width are different enables the manual installation of the components in accordance with the invention in the correct position to be simplified.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: July 13, 1999
    Assignee: BC Components Holdings B.V.
    Inventor: Ruurd Dijkstra
  • Patent number: 5917706
    Abstract: A micromodule is used as a surface-mounted package on a substrate of interconnections. In one embodiment of the invention, barriers to the expansion of solder are formed between contact zones of the micromodule and corresponding contact pads of the substrate. A mechanical stopping device is planned to keep the thickness of the interface of solder. In another embodiment of the invention, contact zones are extended by tongues. A cambering operation enables the formation of the surface-mounting pins.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: June 29, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Francis Steffen
  • Patent number: 5901442
    Abstract: A method of manufacturing an electric member having a number of leads such as in a remote-controlled light receiving module, loosening prevention kinks created on at least one of the leads are shaped such that, the shorter the distance from the loosening prevention kink to the tip of the lead the thinner the loosening prevention kink. When the electric member is mounted on a printed circuit board, the leads are inserted into wiring through-holes on the printed circuit board by pressing the electric member against the board, allowing the position and orientation of the electric member to be firmly fixed automatically by virtue of the loosening prevention kinks.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: May 11, 1999
    Assignee: Sony Corporation
    Inventor: Yoshio Harada
  • Patent number: 5901041
    Abstract: A flexible integrated circuit package for mounting on a substrate is disclosed. The package consists of a tape film having layers of dielectric and conductive material, a semiconductor die and an array of conductive leads. A molded body covers the die, and absorbs the majority of the pressure applied when compressing the package between a heatsink and a printed circuit board (PCB). Rigid removable support material surrounds the molded body to keep the package flat while it is being mounted to the PCB. The support material is removed after soldering of the package to the PCB. The invention permits the package to be tightly compressed between a heatsink and a substrate without causing degradation of the conductive connections. Reliability of the connections is further increased since the tape film is flexible enough to accommodate bending of the substrate to which the package is connected.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: May 4, 1999
    Assignee: Northern Telecom Limited
    Inventors: Bill Tempest Davies, Mark Roy Harris
  • Patent number: 5898574
    Abstract: An electrical device (400) includes a substrate (300) having solder pads (215, 220) formed thereon and a self aligning electrical component (200) mounted to the solder pads (215, 220). The self aligning electrical component (200) includes a body having a cylindrical shape, a first terminal (205) formed on an inner region of the body, and a second terminal (210) formed around outer regions of the body surrounding the first terminal (205).
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: April 27, 1999
    Inventors: Wiling Tan, Raymond Teh Wai Tiong, Lian It Song
  • Patent number: 5889655
    Abstract: A substrate for an integrated circuit package. Located on a bottom surface of the substrate are a plurality of contact pads. Solder balls are attached to the contact pads and then reflowed to mount the package to a printed circuit board. The bottom surface of the substrate has a first layer of solder mask. The first layer has a plurality of first openings which expose at least a portion of each contact pad. Adjacent to the first layer of solder mask is a second layer of solder mask which has a plurality of second openings that also expose the contact pads. The diameter of each second opening is larger than the diameter of each first opening. The openings may be created by etching the layers of solder mask. The etching process typically creates in annular lips in the solder mask openings. The larger second openings reduce the stress risers of the solder balls created by the inner lips of the solder mask.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: March 30, 1999
    Assignee: Intel Corporation
    Inventor: Michael Barrow
  • Patent number: 5889658
    Abstract: A package assembly (70) for encapsulating and vertically surface mounting a semiconductor device such as an accelerometer includes a semiconductor device (40), a package (44) enclosing the semiconductor device, and a plurality of leads (16, 18) protruding from the package. The plurality of leads are formed from a common leadframe (10) and an internal portion of a first lead of the plurality of leads is offset from a common plane corresponding to the common leadframe prior to forming any of the plurality of leads. The offset lead increases the rigidity and vibration-resistance of the package assembly.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: March 30, 1999
    Assignee: Motorola, Inc.
    Inventors: Paul L. Sullivan, Robert W. Kamb, John W. Hart, Jr., David J. Dougherty
  • Patent number: 5889657
    Abstract: A surface-mounting structure of a surface-mounting electronic device onto the surface of a circuit medium is provided. An external terminal of the device has a first mounting surface on which a first set of protrusions are formed. The first mounting surface includes a first uncovered space in the remaining area of the first set of protrusions. A mounting pad of the circuit medium has a second mounting surface on which a second set of protrusions are formed. The second mounting surface includes a second uncovered space in the remaining area of the second set of protrusions. The second mounting surface is opposite to the first mounting surface. The second set of protrusions are inserted into the first uncovered space. The first set of protrusions are inserted into the second uncovered space. A bonding material is placed between the first and second mounting surfaces.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: March 30, 1999
    Assignee: NEC Corporation
    Inventor: Takashi Kono
  • Patent number: 5880405
    Abstract: A terminal structure for a surface mount electronic part including a terminal holding member formed from a synthetic resin, and external terminal extending from the terminal holding member for soldering to soldering lands of a printed wiring board. Each of the external terminals is held on the terminal holding member such that a straight portion projects laterally from the terminal holding member and is restricted direction (i.e., in width and thickness directions). The outermost tip portion of each external terminal includes an offset portion which is stepped downwards relative to the straight portion of the external terminal includes an offset portion which is stepped downwards relative to the straight portion of the external terminal and which is formed by half punching. The offset portion is provided for soldering to a soldering land of the printed wiring board.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: March 9, 1999
    Assignee: Alps Electric Co., Ltd.
    Inventors: Hidehiro Nakamura, Yasunari Takano, Tetsuya Furusawa
  • Patent number: 5877937
    Abstract: A semiconductor device has a resin package containing a semiconductor chip, lead pins electrically connected to the chip, and a heat radiating plate for transmitting heat of the semiconductor chip to the exterior. The lead pins and the heat radiating plate protrude from a side wall of the resin package. The lead pins each have a planar end part attached by soldering to a wiring pattern on a circuit board. The heat radiating plate has a planar attachment part which is attached by soldering to a heat radiating pattern on the circuit board. The planar attachment part of the heat radiating plate is non-rectangular and is shaped such that when it is attached to a solder-coated area on a heat radiating pattern formed on a circuit board, the melted solder is more effectively prevented from flowing out.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: March 2, 1999
    Assignee: Rohm Co., Ltd.
    Inventors: Kazutaka Shibata, Tomoharu Horio
  • Patent number: 5875100
    Abstract: In a high-density mounting method for an electronic circuit board, a stud bump is formed on a connection terminal of a semiconductor chip. The semiconductor chip is buried in a printed circuit board such that the stud bump has a height almost equal to that of a surface of the printed circuit board. At least a surface of the printed circuit board where the semiconductor chip is buried is covered with a first insulating layer. A hole is formed in the first insulating layer by using a laser to expose the stud bump. A first wiring pattern is selectively formed on the first insulating layer, thereby connecting the first wiring pattern and the exposed stud bump to each other. A high-density mounting structure for an electronic circuit board is also disclosed.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: February 23, 1999
    Assignee: NEC Corporation
    Inventor: Koji Yamashita
  • Patent number: 5874780
    Abstract: A semiconductor device comprises a plurality of bump electrodes at least to one surface. A circuit substrate is formed with a laminate structure having an inner layer circuit and a mounting pad is formed on the substrate. The mounting pad has a concave portion and the bottom of the concave portion is in contact with the inner layer circuit. Further, an sealing resin is provided on the substrate. The bump electrode and the concave portion of the mounting pad are opposed, and the bump electrode is pressed to the bottom of the concave portion of the mounting pad, thereby deforming the pointed shape portion at the top end of the bump electrode. By the deformation the pointed shape portion, the contact portion between the bump electrode and the mounting pad is gradually enlarged from a point to a plane. After deforming the bump electrode by a predetermined amount, the sealing resin is hardened and the semiconductor device is mounted on a substrate.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: February 23, 1999
    Assignee: NEC Corporation
    Inventor: Tomoo Murakami
  • Patent number: 5847930
    Abstract: Improved edge terminals for electronic circuit modules such as single- or multi-chip modules and hybrid circuits, and methods of making the edge terminals are disclosed. The improved edge terminals are formed on the edges of the modules, where they do not take up appreciable surface area from the module, and are formed of heat resisting metal and are of larger size as compared to conventional surface terminal pads which simplifies making connections to the module. In one embodiment, ends of pins are inserted in holes in a substrate along lines which will be the edges of the finished modules. After encapsulating in epoxy, the substrate is cut along the lines to bisect the pins, leaving the halves of the pins as embedded terminals flush with the edge of the module. In another embodiment, terminals are formed by attaching the terminal pieces to pads on the substrate, either in the form of widened zones in a grid structure, or an array of terminal plates.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: December 8, 1998
    Assignee: HEI, Inc.
    Inventor: Scott J. Kazle
  • Patent number: 5825628
    Abstract: An electronic package (400), particularly a BGA, including a circuitized substrate (120) and one or more active devices (110) attached thereon by means of corresponding conductive pads provided on a surface of the substrate (120); each conductive pad is splitted in a plurality of parts (212-218) not in contact. Such parts (212-218) may be separated by a wireable area of the substrate (120), thereby providing one or more wiring channels. In addition, the same parts (212-218) may be connected in interfacing couples at different electrical potentials (ground and power) and decoupled to each other by means of capacitors (410); the connections to the ground and power are achieved by metallized holes provided through the substrate (120).
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: October 20, 1998
    Assignee: International Business Machines Corporation
    Inventors: Francesco Garbelli, Stefano Oggioni
  • Patent number: 5812379
    Abstract: A solder joint interface which includes a plurality of solder balls that attach an integrated circuit package to corresponding pads of a printed circuit board. The solder pads are on a 0.05 inch pitch and have a diameter of 0.02 inches so that two 0.006 inch routing traces can be routed between adjacent pads of the circuit board. The additional routing traces allow the solder pads to be arranged in a pattern that has five rows of solder pads. The solder balls have pre-assembled diameters of 0.030 inches and a final height of 0.02 inches. The relatively tall solder joints function as structural beams that undergo both shear and moment stresses when an external load is applied to the joints. The moment component produces lower solder stresses and improves the structural integrity of the solder joints.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: September 22, 1998
    Assignee: Intel Corporation
    Inventor: Michael Barrow
  • Patent number: 5812381
    Abstract: A lead frame includes a base member having a device hole for accommodating a semiconductor chip therein, a plurality of inner lead portions extended outward from respective sides of the device hole, outer lead portions electrically connected to the inner lead portions, respectively, an adhesion area to which the inner lead portions formed on the base member are adhered, and a plurality of dummy leads disposed on a portion of the adhesion area where a density of the inner lead portions is low.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: September 22, 1998
    Assignee: Sony Corporation
    Inventors: Hiroyuki Shigeta, Mutsumi Nagano
  • Patent number: 5805425
    Abstract: First and second electronic parts interconnected by a nonconductive nanoporous film having first and second parallel surfaces, said film having metal-filled pores extending through the thickness of the film, such that each of said parts is contacted by the metal in at least several pores, a number of the pores being perpendicular to the surfaces of the film, and other pores being oblique to the surfaces of the film, whereby thermal dissipation is enhanced in the plane of the film.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: September 8, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Robert K. Peterson
  • Patent number: 5801930
    Abstract: In the case of the relay, connecting elements which are anchored in the base body are passed out of the base body (1) at the side and are bent at right angles to the base plane as push-in posts (12). The push-in posts (12) are formed by sections which are rolled in in the form of sleeves or channels are bent outwards from the contour of the relay structure with an axis at right angles to the base plane and form pushing-in shoulders (14) with their respective upper edge.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: September 1, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventor: Michael Dittmann
  • Patent number: 5796588
    Abstract: An electrical apparatus houses batteries mounted on a printed circuit board (PCB) via conducting tabs with cylindrical insertion sections. The cylindrical insertion sections fit into circular holes in the PCB or into cylindrical sockets soldered into PCB holes. Battery attachment can either be permanent by soldering tabs into the holes or removable by tab insertion into sockets. Removable attachment allows easy battery recovery for recycling. Utilizing the elasticity of sheet metal and cylindrical shaped tabs provides more secure battery attachment resulting in good shock and vibration resistance, and contact over a cylindrical surface insures good electrical connection.
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: August 18, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toyoji Machida, Mitsuya Hara
  • Patent number: 5792985
    Abstract: A terminal for an electronic component having a connecting section with a rectangular shaped cross sectional for connection to the casing of the electronic component, and a taping section also with a rectangular shaped cross sectional for attachment to a tape carrying a plurality of such terminals. In between the connecting section and the taping section are a lower rod section and an upper rod section. The lower rod section facilitates the separation of the taping section from the tape. The upper section facilitates the separation of the connecting section from the remaining portion of the terminal.
    Type: Grant
    Filed: August 21, 1996
    Date of Patent: August 11, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Watanabe, Shoji Takeda, Hideki Notake
  • Patent number: 5790378
    Abstract: An integrated circuit package includes a first lead frame attached to the top surface of a substrate or interposer on which the die is mounted, and a second lead frame attached to the bottom surface of the interposer. The first lead frame is connected to bonding pads on the die by conventional means, and the second lead frame is attached to different bonding pads on the die by means of traces in the interposer and vias which extend through the interposer. The result is a package having a substantially greater lead density than packages which contain only a single lead frame.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: August 4, 1998
    Assignee: National Semiconductor Corporation
    Inventor: Satya N. Chillara
  • Patent number: 5786745
    Abstract: A package (10) has outermost surfaces (12, 13, 14, 16) that form a polygon shape. The body (11) of the package (10) has axial symmetry about an axis (21). A lead (22) exits the package along the axis (21).
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: July 28, 1998
    Assignee: Motorola, Inc.
    Inventors: Alexander J. Elliott, Lonne L. Mays
  • Patent number: RE36097
    Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: February 16, 1999
    Assignee: LG Semicon, Ltd.
    Inventor: Gi Bon Cha