Abstract: Electronic components each having a chip module with module contacts and an antenna having antenna contacts is made by securing a plurality of the chip modules the inner face of a module film strip having an outer periphery projecting past the chip module with the chip modules spaced from one another at a uniform predetermined module spacing. A plurality of the antennas are secured to an inner face of an elongated antenna strip with the antennas spaced from one another by a predetermined antenna spacing. The module strip is longitudinally subdivided into sections each of which is of a length equal to the predetermined module spacing and each of which carries a respective chip module. The module-strip sections are pressed against the antenna strip such that the module contacts of each of the chip modules engage and bear on the antenna contacts of a respective antenna.

Abstract: A method for producing an arrangement of optoelectronic components (10) is specified, comprising the following steps: producing at least two fixing regions (2) on a first connection carrier (1); introducing solder material (3) into the fixing regions (2); applying a second connection carrier (4) to the fixing regions (2); and soldering the second connection carrier (4) onto the first connection carrier (1) with the solder material (3) in the fixing regions (2).

Abstract: A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.

Abstract: A differential transmission circuit includes a pair of transmission line conductors and a ground conductor layer, wherein the pair of transmission line conductors include a first straight line region where both the pair of transmission line conductors extend in parallel to each other in a first direction with a first width in a first layer, a first cross region where one of the pair of transmission line conductors is formed in the first layer, the other thereof is formed in a second layer, and the pair of transmission line conductors cross the each other in a three-dimensional manner, the first cross region being disposed on the front side of the first straight line region, and wherein each of the widths of the pair of transmission line conductors in the first cross region is smaller than the first width.

Abstract: Aspects of the disclosure are directed to an apparatus that is used to provide a circuit layer via a supportive substrate or material layer having an upper surface and having edge surfaces configured and arranged to define patterned aperture channels. The material layer includes an array of patterned islands which provide an upper surface of the material layer for securing and supporting circuitry. The patterned islands are flexible due, for example, to patterned flexures located between and connecting the islands.

Abstract: A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract: A display device includes an array substrate, a driving film and an adhesive member. The array substrate includes a first base substrate, a plurality of first signal pads formed on the first base substrate and a first dummy pad formed adjacent to the first signal pads. The driving film includes a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals. The adhesive member adheres the first signal pads to the output terminals, and adheres the first dummy pad to the first alignment mark.

Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.

Abstract: A solder validation method for a printed circuit board (PCB) having a pin hole extending through the PCB, an electrically conductive trace on a surface of the PCB, and an electrically conductive pin inserted through the pin hole includes the following. An electrically non-conductive portion is provided on the surface of the PCB between the pin hole and the trace such that the non-conductive portion electrically isolates the pin from the trace. After a soldering process intended to solder the pin and the trace together, a soldered connection between the pin and the trace is detected as being absent when no electrical continuity is between the pin and the trace as a soldered connection between the pin and the trace has to be present to provide the electrical continuity due to the pin and the trace otherwise being electrically isolated from one another by the non-conductive portion.

Abstract: A method of making an electronic circuit device includes placing a circuit board in a cavity of a mold such that one side of the circuit board is held in close contact with an inner surface of the cavity, and encapsulating the circuit board in a casing by filling the cavity with a resin material. The one side of the circuit board is exposed to one side of an outer surface of the casing to define part of the one side of the outer surface of the casing. The method further includes thinning the casing by machining the entire one side of the outer surface of the casing.

Abstract: A submount with an electrode layer having excellent wettability in soldering and method of manufacturing the same are disclosed. A submount (1) for having a semiconductor device mounted thereon comprises a submount substrate (2), a substrate protective layer (3) formed on a surface of the submount substrate (2), an electrode layer (4) formed on the substrate protective layer (3) and a solder layer (5) formed on the electrode layer (3) wherein the electrode layer (4) is made having an average surface roughness of less than 1 ?m. The reduced average surface roughness of the electrode layer (4) improves wettability of the solder layer (5), allowing the solder layer (5) and a semiconductor device to be firmly bonded together without any flux therebetween. A submount (1) is thus obtained which with the semiconductor device mounted thereon is reduced in heat resistance, reducing its temperature rise and improving its performance and service life.

Abstract: A printed circuit includes a number of conductive wires. The conductive wires include at least one first conductive wire section, at least one second conductive wire section, and at least one first connection section. An angle between the at least one first conductive wire section and the at least one first connection section is defined as angle ?n, the angle ?n is in a range from about 90 degrees to about 180 degrees. An angle between the at least one second conductive wire section and the at least one first connection section is defined as angle ?n, the angle ?n is in a range from about 90 degrees to about 180 degrees. The angle ?n and ?n are not simultaneously be 180 degrees. ?n??n?1?0, ?n??n?1?0, wherein n is the number of the plurality of conductive wires.

Abstract: Embodiments include but are not limited to apparatuses and systems including a die package including a substrate, a die coupled with a top surface of the substrate, a package wall disposed on the top surface of the substrate and bounding the die, and a package lid coupled with the package wall, and including at least one protrusion facilitating a coupling of the package lid with the package wall. At least one edge of the top surface of the die pad may include an etched portion such that a width of the top surface is narrower than a width of the bottom surface. At least one edge of a top surface of at least one of the leads may include an etched portion such that a width of the top surface is narrower than a width of the bottom surface. Other embodiments may be described and claimed.

Abstract: This invention discloses a display device mother substrate, a display device substrate and a manufacture method of display device substrate thereof. The display device mother substrate includes a first substrate, a second substrate, a first active area circuit and a first transmission line, wherein a first cutting line is defined between the first substrate and the second substrate. The first active area circuit is disposed on the first substrate and is electrically connected to the first transmission line. The first transmission line includes a display line portion, an end line portion and a middle line portion, wherein the display line portion is electrically connected to the first active area circuit. The middle line portion is disposed on the second substrate, wherein two ends of the middle line portion are electrically connected to the display line portion and the end line portion respectively at the first cutting line.

Abstract: A wiring device includes a main conductive line, a plurality of branch conductive lines, a passivation layer, a plurality of contact holes, a plurality of conductive patterns, and a plurality of outside device bonding regions. The branch conductive lines are electrically connected to the main conductive line. The passivation layer is disposed on the branch conductive lines. Each the contact hole partially exposes one of the branch conductive lines. The conductive patterns are disposed on the passivation layer, and each of the conductive patterns is disposed respectively corresponding to each of the branch conductive lines. Each of the conductive patterns is electrically connected to the corresponding branch conductive line via the contact holes. Each of the outside device bonding regions is disposed corresponding to each of the branch conductive lines. At least one of the outside device bonding regions does not overlap the contact hole in a vertical projective direction.

Abstract: An electronic device is disclosed for coupling to a target platform, which includes a multitude of pad contacts. The electronic device includes a substrate, a multitude of pad contacts on the substrate, and a multitude of contact regions in one of the of pad contacts on the substrate. Each of the multitude of pad contacts on the substrate electrically couples to a corresponding one of the multitude of pad contacts on the target platform when the substrate and the target platform are assembled. The multitude of contact regions corresponds to one of the multitude of pad contacts on the target platform when the substrate and the target platform are assembled.

Abstract: An electronic component includes: an electronic component body; and a lead secured to the electric component and including a projection portion defined by first and second inclined portions facing each other. The solder wettability of the first inclined portion is smaller than the solder wettability of the second inclined portion.

Abstract: A sensor device includes at least one sensor device coupled to a substrate. A solder pad interface includes a plurality of steps, with at least a portion of the steps positioned at different planes, each of a step having a solder pad. A cable with a plurality of cable leads, is configured for each of a cable lead to be coupled to a solder pad.

Abstract: A package substrate including an outermost interlayer resin insulating layer, a pad structure formed on the outermost interlayer resin insulating layer, a conductive connecting pin for establishing an electrical connection with another substrate, the conductive connecting pin being secured to the pad structure via a solder, and via holes formed through the outermost interlayer resin insulating layer and for electrically connecting the pad structure to one or more conductive circuits formed below the outermost interlayer resin insulating layer, the via holes being positioned directly below the pad structure.

Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

Abstract: The invention relates to a multiple micro HF-contact arrangement with HF-connections for passing through or contacting in a housing opening or in a duct, in particular at the transition from coaxial line or microstrip line to a coplanar line. The HF-connection thus comprises at least two circuit boards arranged in a plane which may be connected to each other by means of a planar contact pin on one circuit board and at least one planar socket on the other circuit board.

Abstract: Provided is printed circuit board for minimizing dielectric losses experienced by a low-current portion of an electric circuit. The printed circuit board includes a first substrate supporting an electrically-conductive material patterned to form a conductive pathway between electric circuit components, and a surface-mount guard pad provided on a substantially-planar exposed surface of the first substrate and covering at least an area of the exposed surface including a footprint of the low-current portion on the first substrate. A second substrate is also provided with one or more electrically conductive pads that are surface mounted to the guard pad to couple the second substrate to the guard pad. The second substrate also supports a signal trace included in the low-current region for conducting a low-current signal.

Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: A package structure and an electronic apparatus of the package structure are disclosed. The package structure includes a substrate and a plurality of pins. The plurality of pins is disposed on the substrate. The plurality of pins is interlaced to each other, so that a line along a specific direction will only pass one of the plurality of pins at most.

Abstract: A card structure includes a first substrate, a second substrate, and a connector. The first substrate includes a base surface, wherein at least one electronic part region and a terminal region are disposed on the base surface. The second substrate is disposed on the base surface and is coupled to the terminal region of the first substrate. The connector is disposed on the base surface to juxtapose the second substrate. The connector includes a connecting surface, a contact unit, and a plurality of contact regions disposed on the connecting surface and coupled to the contact unit and the terminal region, such that the plurality of contact regions are coupled to the second substrate via the terminal region of the first substrate.

Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

Abstract: Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential.

Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

Abstract: Embodiments of the present invention provide a semiconductor package which includes: a semiconductor chip to which one end of each of a plurality of wires is connected; and a board on which the semiconductor chip is fixed, and a plurality of board wires to which the plurality of corresponding wires are connected are disposed, wherein the board includes: a first wiring pair that includes a first pair of wires in parallel with each other and first two board wires connected to the corresponding wires, one of the wires connected to one of the board wires crossing the other board wire without contact with the other board wire, and a second wiring pair that is provided adjacent to the first wiring pair and includes a second pair of wires in parallel with each other and second two board wires connected to the corresponding wires without a crossing.

Abstract: A structure for mounting a compound circuit on a circuit board is provided. The compound circuit includes a high voltage circuit and a low voltage circuit whose supply voltages are different from each other. The structure includes: a main circuit board on which constituents of the low voltage circuit are mounted; and a hybrid IC which includes a sub circuit board on which at least a part of constituents of the high voltage circuit is mounted and a moisture preventing agent coating the sub circuit board, and is arranged over the main circuit board. Both an insulation distance between terminals provided on the main circuit board for connecting to the hybrid IC and an insulation distance between terminals provided on the hybrid IC for connecting to the main circuit board are larger than a minimum insulation distance between terminals provided on the constituents mounted on the sub circuit board.

Abstract: Articles and methods of manufacture are provided for using laser energy in an automated bonding machine to effect laser welding of ribbons to electronic components, particularly conductive ribbons comprising titanium for microelectronic circuits. Bonding and connection of microelectronic circuits with discrete heating avoids heat damage to peripheral microelectronic components. Bonding of flexible materials and low-resistance materials are possible, and are less dependant on substrate and terminal stability in comparison to other bonding methods. The ribbon-connections can forgo the use of blocks, bond pads, and bond pad arrays for attaching ribbon to a printed wiring board. Profile height of the ribbon-connection is decreased and the density of ribbons and bonding sites can be increased compared to ribbon-connections employing bonding pads.

Abstract: A dummy memory card includes a circuit board and a golden finger board. The circuit board includes a first conductive element and a second conductive element connected to a first electrical load. The golden finger board extends from the circuit board and is inserted into a memory slot of a motherboard. The golden finger board includes a first power pin and a first ground pin. The first conductive element is electrically connected to the first power pin. The second conductive element is electrically connected to the second power pin.

Abstract: An electronic assembly (20; 30; 40; 50) for attachment to a fabric substrate (60; 82, 102) having a conductor pattern (62a-b; 85a-b; 107a-c) on a first side (63; 86; 108) thereof. The electronic assembly comprises an electronic device (23; 42; 64), and at least a first clamping member (21; 41; 65). The electronic assembly is, furthermore, adapted to clamp the electronic device (23; 42; 64) to the first side (63; 86; 108) of the fabric substrate (60; 82, 102) in such a way that the electronic device (23; 42; 64) is electrically connected to the conductor pattern (62a-b; 85a-b; 107a-c).

Abstract: An interconnect array uses repeated application of an interconnect pattern (“tile”). The tile has eight I/O signal pins forming a perimeter array, a central pin that can be either a ground pin or an I/O power pin, and an offset ground pin. The I/O signal pins are associated with the same or multiple I/O banks. If the central pin is an I/O power pin, it is optionally associated with an I/O bank associated with one or more of the I/O signal pins.

Abstract: Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.

Abstract: A delay line structure disposed on a substrate having a dielectric base layer formed with a via, a layout layer and a grounding layer with a grounding circuit, includes two parallel spiral delay lines having a first outer straight section, a first outer bent section, an inner spiral region, a second outer bent section and a second outer straight section. The inner spiral region bends reciprocally between the first and second outer straight sections to form several inner bent parts and several inner straight parts. A grounding guard trace is disposed among the first and second outer straight sections and the inner straight parts and is coupled electrically to the grounding circuit, wherein each of the first and second outer bent sections and the inner bent parts has a width smaller than each of the first and second outer straight sections and the inner straight parts.

Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.

Abstract: Consistent with an aspect of the present disclosure, a package is provided that has a carrier and first and second substrates provided on the carrier. Conductive traces are provided on the first substrate (upper traces) and below it (lower traces) to provide two levels of electrical connectivity to a photonic integrated circuit (PIC) provided on the second substrate. As a result, an increased number of connections can be made to the PIC in a relatively small package, while maintaining adequate spacing and line widths for each trace. In addition, the lower traces are connected to bonding pads on the surface of the first substrate and are thus provided in the same plane as the upper traces. Testing of and access to both upper and lower traces is thus simplified.

Abstract: A substrate includes: a base; and a plurality of bonding terminals arranged on at least one surface of the base, wherein the plurality of bonding terminals include a first bonding terminal and a second bonding terminal, the first bonding terminal and the second bonding terminal include, in plan view of the base, a circle contacting portion extending along the circumference of a circle tangent to the first bonding terminal and the second bonding terminal, all of the plurality of bonding terminals are arranged so as not to protrude from an area including the circle and the inside thereof, and the circle contacting portion includes at least a first circle contacting portion disposed in the first bonding terminal and a second circle contacting portion disposed in the second bonding terminal.

Abstract: A power converter is disclosed in which the structure of a connecting portion is highly resistant against vibration and has a low inductance. The power converter includes a plurality of capacitors and a laminate made up of a first wide conductor and a second wide conductor joined in a layered form with an insulation sheet interposed between the first and second wide conductors. The laminate comprises a first flat portion including the plurality of capacitors, which are supported thereon and electrically connected thereto, a second flat portion continuously extending from the first flat portion while being bent, and connecting portions formed at ends of the first flat portion and the second flat portion and electrically connected to the exterior.

Abstract: A filter of the present invention is a filter including a substrate and a filter element mounted on the substrate, wherein the substrate is provided with a plurality of wiring layers including a filter element wiring layer which is formed with wirings and connected with the filter element, an insulating layer interposed between the plural wiring layers and a ground pattern formed in at least a part of a wiring layer under the filter element wiring layer; and the thickness of the insulating layer interposed between the filter element wiring layer and the other wiring layer is smaller than the width of the wiring formed in the filter element wiring layer, and is larger than the thickness of the other wiring layer. By such a configuration, a thin, high-suppression and high-isolation filter can be realized.

Abstract: An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit and the plurality of electronic components, wherein the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation to provide a slope directly proportional to a data value.

Abstract: Each wiring pattern is composed of a conductor layer and a tin plating layer, and includes a tip portion, a connection portion and a signal transmission portion. The width of the tip portion is equal to the width of the signal transmission portion, and the width of the connection portion is smaller than the widths of the tip portion and the signal transmission portion. The connection portions of wiring patterns and bumps of an electronic component are connected to one another, respectively, by heat-sealing when the electronic component is mounted. Respective distances A1, A2 are set to not less than 0.5 ?m. Respective distances B1, B2 are set to not less than 20 ?m. The thickness of the tin plating layer is set to not less than 0.07 ?m and not more than 0.25 ?m.

Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

Abstract: An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages.

Abstract: A wiring board includes a metal cap pad that is arranged so as to surround a mounting position of an electronic component and is connected to an end portion of a metal cap, a power source plane that is connected to the electronic component through a connection member and has a gap, a ground plane that is connected to the electronic component through a connection member, and a plurality of conductive body elements that are repeatedly arranged so as to surround the connection members and the gap. The power source plane and the ground plane extend so as to include at least a part of an area that is surrounded by the plurality of conductive body elements and at least a part of an area facing the plurality of conductive body elements.

Abstract: A printed wiring board having an insulating base material; a wiring formed on at least one surface of the insulating base material, the wiring forming a predetermined circuit pattern; a first connection terminal portion formed on the surface and electrically connected to the wiring, the first connection terminal portion having a first width; a second connection terminal portion formed on the surface and electrically connected to the wiring, the second connection terminal portion having a second width; and a cover layer configured to cover the wiring and expose the first and the second connection terminal portion.