Abstract: An electronic device with EMI screen and packaging process thereof to provide even active EMI prevention means includes adhesion of a transit substrate to a soldering surface of the electronic device, a protection circuit layer functioning as EMI screen being paved on the bottom of the transit substrate; a packaging circuit layer being laid; protection circuit layer and the transit substrate as well as the packaging and protection circuit layers being segregated with an insulation material; and solder balls provided with electric continuity to the protection circuit layer and the packaging circuit layer being respectively implanted as soldering points respectively for EMI grounding and linkage between the electronic device and a printed circuit.

Abstract: A wiring board which includes a product portion configured with at least one layer of electrically insulating base, a wiring pattern formed on the surface or inner portion of the electrically insulating base, and a wiring protection layer which is formed on the surface of the board and has an opening. Warping over the entire wiring board can be reduced since this wiring board has a warp-correcting portion warped in a direction different from that of the product portion.

Abstract: A motor drive apparatus includes an assembly of first and second subassemblies. The first subassembly includes a first board and at least one connecting member, such as a bus bar, formed in the first board, and arranged to form a current supply path from a power source to the motor. The second subassembly includes a second board and at least one switching device mounted on the second board. The first and second subassemblies are stacked with an interspace between the first and second boards. A terminal segment of the switching device is connected with a terminal segment of the connecting member.

Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

Abstract: A power plane includes a first circuit region and a second circuit region. The length of the first circuit region or second circuit region is related to the noise frequency to be filtered out. The width of the first circuit region can be wider or narrower than the width of the second circuit region. While manufacturing the power plane, a predetermined length is decided according to the resonance frequency of an original power plane, then the proposed power plane is formed with the first circuit region and the second circuit region of a predetermined length, and making the width of the first circuit region wider or narrower than the width of the second circuit region, such that the noises with the resonance frequency can be mitigated.

Abstract: A semiconductor device includes first and second assembled bodies (12A, 12B). The first assembled body is provided with a first semiconductor chip, a high voltage bus bar (21) connected to one surface of the first semiconductor chip, a first metal wiring board (24-1) connected to the other surface of the first semiconductor chip with a bonding wire, and a third metal wiring board (24-3) connected to the first metal wiring board. The second assembled body is provided with a second semiconductor chip, a low voltage bus bar (23) connected to one surface of the second semiconductor chip with a bonding wire, a second metal wiring board (24-2) connected to the other surface of the second semiconductor chip, and a fourth metal wiring board (24-4) connected by being returned from an end portion of the second metal wiring board and arranged in parallel to the second metal wiring board.

Abstract: A multilayer printed circuit board is characterized in that circuit boards 1 and 2 and a circuit board 3 are laminated alternately to form a multilayer body using a simultaneous lamination method, the circuit boards 1 and 2 including a film-, thin plate-, or sheet-like insulating substrate 11 made of a thermosetting resin containing any one of epoxy resin, bismaleimide/triazine resin, and allylic polyphenylene ether resin as a major component, the circuit board 3 including a film-, thin plate-, or sheet-like insulating substrate 21 made of a thermoplastic resin containing a polyaryl ketone resin and amorphous polyether imide resin having a crystal-fusing peak temperature of 260° C. or more.

Abstract: A storage device backplane and an identification circuit for identifying using situations of the storage device backplane are provided. The storage device backplane possesses a first connection interface and a second connection interface, for being used as a first backplane supporting a motherboard, or a second backplane cascaded to the first backplane, or a first backplane supporting a daughterboard of the motherboard. The first and second backplanes possess the same storage device backplane structure. If the storage device backplane is used as the first backplane, a first connection interface of the first backplane is coupled to the motherboard or the daughterboard thereof; if the storage device backplane is used as the second backplane, a first connection interface of the second backplane is coupled to a second connection interface of the first backplane. The identification circuit identifies using situations of the storage device backplane and display corresponding correct indicator number.

Abstract: A package for providing electromagnetic shielding for microwave circuits. The package includes a top board having an upper surface, a lower surface opposite to the upper surface and a side surface joining the upper surface and the lower surface, and a bottom board having an upper surface attached to the lower surface of the top board, a lower surface opposite to the upper surface and an outer side surface joining the upper surface and the lower surface. The top board further includes at least one ground layer formed therein and a first metal coating formed on at least part of the side surface of the top board. The bottom board includes an inner side surface extending from the upper surface of the bottom board toward the lower surface of the bottom board and an inner lower surface joining the inner side surface, thereby providing an inner space for accommodating the microwave circuit.

Abstract: A wiring substrate includes a silicon substrate, a through hole formed to penetrate the silicon substrate in a thickness direction, an insulating layer formed on both surfaces and side surfaces of the silicon substrate and an inner surface of the through hole, a penetration electrode formed in the through hole, a wiring layer formed on at least one surface of the silicon substrate and connected to the penetration electrode, and a metal wire terminal connected to the wiring layer and formed to extend from one surface of the silicon substrate to a side surface thereof. The metal wire terminal on the side surface of the electronic device is connected to the mounting substrate such that a substrate direction of the electronic device in which an electronic component is mounted on the wiring substrate intersects orthogonally with a substrate direction of the mounting substrate.

Abstract: A wiring board and method of forming the wiring board. The wiring board includes a first substrate, and a second substrate having a smaller mounting area than a mounting area of the first substrate. A base substrate is laminated between the first substrate and the second substrate such that the first substrate extends beyond an edge of the second substrate, and at least one via formed in at least one of the first substrate or the second substrate. A thickness of a portion of the base substrate that is sandwiched between the first substrate and the second substrate is greater than a thickness of a portion of the base substrate that is not sandwiched between the first substrate and the second substrate.

Abstract: This invention provides a power supply comprising a mother board, a first socket, and a DC-DC converter module. The mother board comprises a transformer operative for transforming an input power into a first AC output power and a filter operative for receiving the first AC output power and filtering the first AC output power into a first DC output power. The first socket is mounted on the mother board and electrically coupled to a circuitry of the mother board by way of at least one conductor terminal operative for providing the first DC output power. The DC-DC converter module mounted on a printed circuit board electrically coupled to the mother board comprises a DC-DC converter operative for receiving the first DC output power and converting the first DC output power into a second DC output power and a third DC output power and a second socket operative for providing the second DC output power and the third DC output power by means of a conductive path of the printed circuit board.

Abstract: A wiring board and method of forming a wiring board. The wiring board includes a first substrate and a second substrate having a smaller mounting area than a mounting area of the first substrate. A base substrate is laminated between the first substrate and the second substrate such that the first substrate extends beyond at least one edge of the second substrate. At least one of the base substrate, the first substrate or the second substrate comprises pliable resin, and at least one other of the base substrate, the first substrate or the second substrate comprises an inorganic filler.

Abstract: A method of fabricating a printed circuit board having a coaxial via is disclosed. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.

Abstract: An object of the present invention is to provide a multilayered printed circuit board having a short wiring distance of the conductor circuits, wide option of the design of the conductor circuits and additionally excellent in reliability since cracking scarcely takes place in the interlaminar resin insulating layers in the vicinity of via-holes. The present invention is a multilayered printed circuit board comprising: a conductor circuit and an interlaminar resin insulating layer serially formed on a substrate in alternate fashion and in repetition, wherein a connection of the conductor circuits through the interlaminar resin insulating layers is performed by a via-hole, wherein via-holes in different level layers among the via-holes are formed so as to form a stack-via structure, and wherein at least one of the land diameters of the above-mentioned via-holes in different level layers having the stack via structure is different from the land diameters of other via-holes.

Abstract: A method of manufacturing a printed circuit board is disclosed. A method of manufacturing a printed circuit board, which includes: forming at least one interlayer connector on a first carrier, stacking at least one insulation layer on the first carrier such that the interlayer connector is exposed, removing the first carrier, and forming at least one circuit pattern on the insulation layer such that the circuit pattern is electrically coupled with the interlayer connector, can be used to increase the density of circuit patterns, as the method can provide electrical connection between circuit patterns and vias without using lands.

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

Abstract: Interconnect substrate (1) that connects at least the first circuit board and the second circuit board. Interconnect substrate (1) includes housing (1) and connecting terminal electrodes for connecting the top and bottom faces of housing (10). Housing (10) has protrusion (11) on its outer periphery and opening (13) in its inner periphery.

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

Abstract: An electronic circuit contains a circuit board with conducting tracks to which one or more electronic components with conducting contacts are positioned overlying portions of the conducting tracks and each such electronic component is held in place by a clamp that covers and is contact with the top surface of the electronic components so as to hold their conducting contacts in electrical contact with the conducting tracks of the circuit board. The clamp can include a resilient layer held between the top surface of electronic components and a rigid clamping sheet.

Abstract: A multilayer printed circuit board including a substrate board and a built-up structure formed over the substrate board. The built-up structure includes conductor circuits and resin insulating layers. The built-up structure has via holes interconnecting the conductor circuits through one or more resin insulating layers. The via holes are filled up with plating, and the resin insulating layers is formed of a cycloolefin resin.

Abstract: An apparatus includes a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits. Such capacitor may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the power supply. An example of both a space restricted application and a close coupling application may be an integrated circuit (IC) such as a microprocessor. The capacitor supplying and moderating power to the microprocessor needs to be closely coupled in order to respond to instantaneous power demands that may be found in high clock rate microprocessors, and the space inside a microprocessor package is very restricted.

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.

Abstract: A printed circuit board using paste bumps and manufacturing method thereof are disclosed.

Abstract: A stacked microelectronic assembly is disclosed, as are different embodiments related to the same. The stacked microelectronic assembly includes a plurality of stackable microelectronic units each having a semiconductor element mounted on a substrate, and also includes alignment elements which align and stack the units one atop another. The aligned assembly may be heated to melt or to reflow the conductive bonding material between the units, thereby electrically coupling and bonding corresponding conductive terminals on each unit.

Abstract: Wiring system which comprises: a flexible printed circuit board (1) with a surface (2) in turn comprising one or more electrical circuits formed by conductive strips (4) and a plurality of electronic components (5) connected to said conductive strips (4) and with at least one extension or branch (6) extending directly from said surface (2) and also comprising conductive strips (7); characterized in that it further comprised: at least one flexible flat cable (8) joined to said at least one extension or branch (6), such that an electrical connection is formed between said flexible flat cable (8) and said extension or branch (6). A vehicle door which internally comprises this wiring system.

Abstract: A wiring substrate includes a first insulation layer, a connection terminal, a second insulation layer, a via, and a wiring pattern. The connection terminal is disposed in the first insulation layer so as to be exposed from a first main surface of the first insulation layer, and is electrically connected with a semiconductor chip. The second insulation layer is disposed on a second main surface of the first insulation layer situated on the opposite side from the first main surface. The via is disposed in the second insulation layer, and is electrically connected with the connection terminal. The via is separated from the connection terminal. The wiring pattern is disposed on the second main surface of the first insulation layer and electrically connects the connection terminal and the via.

Abstract: Methods and apparatus for creating independent circuit connections within a through-hole of a substrate are described. According to one aspect of the present invention, a method includes defining a through-hole in a substrate, applying a conductive plating to a holewall of the through-hole, and selectively removing at least a first area of the plating. The through-hole has a height relative to a first axis, and the perimeter of the through-hole at each point along the first axis is approximately the same. Selectively removing the first area of the plating includes defining second areas of the plating. At least one of the plurality of second areas does not span a height of the hole.

Abstract: Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component.

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract: In a method of manufacturing a multilayer printed circuit board, a first insulating resin base material is formed. A resin surface of a second insulating resin base material formed by attaching copper foil on a surface of a resin-insulating layer is unified with the first insulating resin base material. A conductor circuit is formed on the second insulating resin base material and a via hole electrically connecting to the conductor circuit. A concave portion is formed from a resin-insulating layer surface in a conductor circuit non-formation area of the first insulating resin base material. A semiconductor element is housed within the concave portion and adhered with an adhesive. A resin-insulating layer is formed by coating the semiconductor element and a via hole.

Abstract: An integrated audio transducer with associated signal processing electronics is disclosed. A silicon audio transducer, such as a MEMS microphone or speaker, can be integrated with audio processing electronics in a single package. The audio processing electronics can be configured using control signals. The audio processing electronics can provide a single line serial data interface and a single line control interface. The audio transducers can be integrated with associated processing electronics. A silicon microphone can be integrated with an Analog to Digital Converter (ADC). The ADC output can be a single line serial interface. The ADC can be configured using a single line serial control interface. A speaker may be integrated with a Digital to Analog Converter (DAC). Audio transducers can also be integrated with more complex processing electronics. Audio processing parameters such as gain, dynamic range, and filter characteristics may be configured using the serial interface.

Abstract: A composite electronic component includes a multilayer wiring block having a plurality of insulating layers and a wiring pattern, and a chip-type electronic component built-in multilayer block having a plurality of insulating payers and a wiring pattern and including a first chip-type electronic component. The multilayer wiring block and the chip-type electronic component built-in multilayer block are electrically interconnected and arranged on substantially the same plane.

Abstract: High-frequency circuit components are disclosed in which parasitic capacitance between a high-frequency circuit element and a substrate is reduced and mechanical strength is improved. An exemplary component has a conductive substrate, a coil as the high-frequency circuit-element, a mounting board including a thin dielectric film on which the coil is mounted, and a support board that couples the mounting board to the substrate. The mounting board is coupled so that it floats relative to the substrate as a result of deliberate warping of the support board.

Abstract: According to one embodiment, a printed wiring board includes an insulating layer, a first conductor pattern on the insulating layer configured to be a signal line, and a second conductor pattern on the insulating layer. The second conductor pattern includes a larger conductor area than the first conductor pattern, and a slit which allows the second conductor pattern to stretch to follow a thermal expansion of the insulating layer.

Abstract: The present invention provides a circular electronic apparatus. The circular electronic apparatus includes a circular crust and a plurality of isosceles trapezoid circuit boards. The isosceles trapezoid circuit boards are put together to form an equilateral polygon. Each isosceles trapezoid circuit board is connected with an adjacent isosceles trapezoid circuit board by a plurality of electrical lines and all the isosceles trapezoid circuit boards are connected together. The circular crust covers the equilateral polygon circuit board.

Abstract: A plurality of film substrates (2) having a bare chip (1) mounted on one side or both sides are joined into a laminated state by joint portions (3) and are attached to a motherboard (4) through junction by a joint portion (8) at a location off the mounting areas of the bare chips (1), thereby achieving a lower profile, higher lamination, and higher capacity.

Abstract: A multi-layer printed wiring board including a first substrate having an opening and having external terminals positioned to be connected to a package substrate, a second substrate laminated to the first substrate and having external terminals positioned to be connected to a mother board, the second substrate having a metallic layer portion in the opening of the first substrate and non-through holes filled with conductive material and connected to the metallic layer portion, and an IC component having terminals and loaded in the opening of the first substrate such that the terminals of the IC component face an opposite side of the metallic layer portion of the second substrate. The IC chip is accommodated in the opening such that the metallic layer portion and non-through holes of the second substrate irradiate heat generated by the IC chip.

Abstract: A structure. The structure includes a substrate and an interposer. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N?2). The interposer includes N continuous interposer channels coupled to the N substrate channels to form M continuous loops (1?M?N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink.

Abstract: A positive differential signal trace and a negative differential signal trace are formed on different layers of a printed circuit board. A first ground trace is formed on the layer on which the positive differential signal trace is formed, and a second ground trace is formed on the layer on which the negative differential signal trace is formed. An insulation layer is positioned between the two layers and has a predetermined thickness. A differential mode impedance and a common mode impedance of differential signals are dependent on the predetermined thickness of the insulation layer, width and thickness of each differential signal trace, and a space between each differential signal trace and the corresponding ground trace formed on the same layer.

Abstract: The invention relates to the collective fabrication of n 3D modules. A batch of n wafers I are fabricated on one and the same plate. This step is repeated K times. The K plates are stacked. Plated-through holes are formed in the thickness of the stack. These holes are intended for connecting the slices together. The stack is cut in order to obtain the n 3D modules. The plate 10, which comprises silicon, is covered on one face 11 with an electrically insulating layer forming the insulating substrate. This face has grooves 20 that define n geometrical features, which are provided with an electronic component 1 connected to electrical connection pads 2? placed on said face.

Abstract: A wiring board has a first rigid wiring board having an accommodation section, a second rigid wiring board to be accommodated in the accommodation section, and an insulation layer formed on the first rigid wiring board and the second rigid wiring board. Here, a conductor of the first rigid wiring board and a conductor of the second rigid wiring board are electrically connected to each other, and at least either a side surface of the second rigid wiring board or a wall surface of the accommodation section has a concave-convex portion.

Abstract: Methods of forming multi-chip semiconductor substrates include forming a first plurality of dicing streets in a first surface of a first semiconductor wafer having a first plurality of bonding sites thereon and forming a second plurality of dicing streets in a first surface of a second semiconductor wafer having a second plurality of bonding sites thereon. The first surfaces of the first and second semiconductor wafers are bonded together so that the first plurality of dicing streets are aligned with the second plurality of dicing streets and the first plurality of bonding sites are matingly received and permanently affixed within the second plurality of bonding sites. A plurality of bonded pairs of semiconductor chips are then formed by planarizing the second surface of the second semiconductor wafer until the second plurality of dicing streets are exposed.

Abstract: A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole.

Abstract: A printed circuit board assembly includes a first printed circuit board having a plurality of electrical traces that is attached to a second printed circuit board having a plurality of electrical traces in a substantially perpendicular fashion. The first printed circuit board has a plurality of male terminal tabs that fit into a plurality of female terminal slots of the second printed circuit board to make a plurality of electrical connections between the electrical traces of the first printed circuit board and the electrical traces of the second printed circuit board. The assembly has at least two mechanical connections between the first printed circuit board and the second printed circuit board comprising connector blades that are substantially perpendicular to the first printed circuit board and to the second printed circuit board. The connector blades may also make electrical connections between electrical traces of the first and second printed circuit boards.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.

Abstract: According to one embodiment, there is provided a printed circuit board including a plurality of electrode pads provided on a component mounting face on which a semiconductor component is to be mounted, a plurality of hole terminals provided on the component mounting face so as to correspond to the electrode pads, and a plurality of wiring pattern layers connecting the plurality of electrode pads and the plurality of hole terminals corresponding to the plurality of electrode pads, the plurality of wiring pattern layers being wired across directions of elastic deformation of the component mounting face.