Overvoltage Patents (Class 361/91.1)
  • Patent number: 8941958
    Abstract: To provide a protection circuit having a small area, redundancy, and small leak current. In the protection circuit, a plurality of nonlinear elements is provided so as to overlap with each other and so as to be electrically connected in series. At least one nonlinear element in the protection circuit is a diode-connected transistor including an oxide semiconductor in its channel formation region. The other nonlinear element is a diode-connected transistor including silicon in its channel formation region or a diode including silicon in its junction region.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroyuki Tomatsu
  • Patent number: 8942013
    Abstract: A system and method for protecting an electrical power generation system from an over-voltage. The output voltage of a multi-phase rectifier, operatively connected between the output terminals of an electric machine and a load, is monitored. The input of the multi-phase rectifier is short-circuited upon detection that the output voltage has reached a threshold voltage. Removal of the short-circuiting of the input of the multi-phase rectifier is synchronized with a substantially zero-crossing of phase current flowing through switching devices in the rectifier once the output voltage is no longer above the threshold voltage.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: January 27, 2015
    Assignee: Pratt & Whitney Canada Corp.
    Inventor: Kevin A. Dooley
  • Publication number: 20150016003
    Abstract: Methods and apparatus to clamp overvoltages for inductive power transfer systems are described herein. An example overvoltage protection circuit is described, including a first terminal configured to receive an alternating current signal for conversion to a second signal, a capacitor, a first switch configured to selectively electrically couple the capacitor to the first terminal based on an overvoltage detection signal to reduce an overvoltage on the second signal, and an overvoltage detector. The example overvoltage detector is configured to determine a signal level of the second signal and, in response to determining that the signal level of the second signal is greater than a threshold, to output the overvoltage detection signal to cause the switch to electrically couple the capacitor between the first terminal and a second terminal.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 15, 2015
    Inventors: Stephen Christopher Terry, Paul L. Brohlin
  • Patent number: 8934206
    Abstract: A remote sensing circuit and a high-power supply apparatus having the remote sensing circuit. The high-power supply apparatus can include a feedback circuit to feedback power output from a high-power supply unit to an input terminal of the high-power supply apparatus. The remote sensing circuit can include a switching unit connected between an output terminal of the high-power generating unit and the feedback circuit of the high-power supply apparatus to open the connection in a normal status and to close the connection in an abnormal status, a load channel to connect the high-power generating unit and a load, and a remote sensing unit having one terminal commonly connected to the load and the load channel and another terminal commonly connected to the switching unit and the feedback circuit to sense power supplied to the load.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jee-hoon Jung
  • Patent number: 8929039
    Abstract: Aspects of the invention provide for an electrostatic discharge (ESD) clamp. In one embodiment, the ESD clamp includes: a silicon controlled rectifier (SCR); and a trigger circuit for providing a tunable trigger voltage to turn on the SCR, the trigger circuit including a metal-insulator transition (MIT) material. The trigger circuit includes an MIT resistor that includes a width and a length that tunes the trigger voltage to a desired voltage.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mohit Bajaj, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Patent number: 8929042
    Abstract: A surge protective device is disclosed that may include a comparator to determine when a line voltage of a line is above a threshold. The device may include a switch to couple a clamping device to the line voltage when the comparator determines the line voltage is above a threshold, wherein the clamping device shunts current from the line. The switch may include a silicon-controlled rectifier (SCR) or a thyristor and the clamping device may include a selenium surge suppression device.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: January 6, 2015
    Assignee: Thomas & Betts International, Inc.
    Inventors: Hans-Erik Pfitzer, Martin William Guy
  • Patent number: 8929043
    Abstract: Provided is an over-voltage protection device for a resonant wireless power reception device. The over-voltage protection device includes a resonance signal receiver for receiving a wireless resonance signal transmitted from a wireless power transmission device, an over-voltage protector which is driven by a driver in an over-voltage protection operation to detune a resonance frequency of the reception device, thereby reducing reception power, the driver for driving the over-voltage protector according to a control signal in the over-voltage protection operation, and a controller for outputting the control signal for driving the over-voltage protector to the driver when it is determined that over-voltage occurs.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Yu-Su Kim, Joon-Il Kim, Se-Ho Park, Sung-Kweon Park
  • Publication number: 20150002972
    Abstract: Protection device includes a group of lines, a protection board, and a connector. The group of the lines includes a first line and a second line. The first line is a ground wire and the second line is a power wire. The protection board includes a number of protection members. The connector includes a first connector port and a second connector port. The first line is directly connected to the first connector port, and the corresponding second line is connected to the corresponding second connector port through the protection board.
    Type: Application
    Filed: April 14, 2014
    Publication date: January 1, 2015
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD ., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: BO TIAN, KANG WU, YU HAN
  • Patent number: 8922962
    Abstract: A power clamp circuit having improved robustness to electrostatic discharge (ESD) events includes a voltage regulation circuit and a current controlled switch. The voltage regulation circuit and the current controlled switch may be used to modify a snapback voltage of the power clamp in a manner that enhances the power clamp's ability to handle ESD events.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: December 30, 2014
    Assignee: Allegro Microsystems, LLC
    Inventors: Washington Lamar, Maxim Klebanov
  • Patent number: 8923012
    Abstract: What is disclosed is a modular visualization display panel. The modular visualization display panel includes a first module having at least one surface and a connection to electrical ground. The modular visualization display panel also includes a second module having at least one surface with a plurality of raised contact nodes arranged on the one surface of the second module such that when in contact with the one surface of the first module electrostatic discharge energy is directed over at least one of the raised contact nodes to the one surface of the first module.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 30, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Andrew P. Kaufman, Keith O. Satula
  • Patent number: 8922964
    Abstract: A motor controller with a reverse-bias preventing mechanism includes a pre-charging unit, a protection unit, a conversion unit and a control unit. The pre-charging unit receives a power signal through a first electric-conduction path, and converts the power signal into a pre-charging signal according to a control signal. The protection unit receives the power signal through a second electric-conduction path, and determines whether to output the power signal, according to the polarity of the power signal. The conversion unit, coupled to the protection unit, receives the power signal outputted by the protection unit, and converts the power signal into a work voltage. The control unit, coupled to the conversion unit and the pre-charging unit, receives the work voltage to generate the control signal. The current of the power signal flowing through second electric-conduction path is smaller than the current flowing through first electric-conduction path.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Kun-Lun Chuang, Shin-Hung Chang, Tshaw-Chuang Chen
  • Patent number: 8922959
    Abstract: The apparatus for preventing a secondary accident by short of sensing lines in a high voltage battery using a fuse, includes: a plurality of battery modules provided with a plurality of battery cells; a battery pack including a plurality of battery modules; a battery management system (BMS) for monitoring and controlling voltage of each battery cell provided in each battery pack to monitor the status of each battery cell; sensing lines connected between the battery module and the battery management system to sense voltage of each battery cell of each battery pack; and a passive safety device to be connected in series to a terminal of each battery cell provided in each battery pack when a short accident that a closed circuit is formed in the sensing line occurs.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: December 30, 2014
    Assignee: SK Innovation Co., Ltd.
    Inventors: Sei Hoon Cho, Soo Yeup Jang, Young Lim Choi, Sang Hyuck Kim
  • Publication number: 20140376139
    Abstract: Various examples are provided for voltage protection of semiconductor devices. In one example, among others, a circuit includes a MOS device, a protective device connected between the MOS device and an output voltage connection, and gate protection circuitry configured to provide a bias voltage to a gate of the protective device. The bias voltage includes a DC bias component and an AC bias component that synchronously varies with a voltage of the output voltage connection. Another example includes a plurality of protective devices connected between the MOS device and the output voltage connection. The gate protection circuitry may be configured to provide a plurality of bias voltages to the plurality of protective devices. In another example, a method includes attenuating an output voltage, combining the attenuated output voltage with a constant offset voltage to generate a gate bias voltage, and providing the gate bias voltage to a protective device.
    Type: Application
    Filed: June 26, 2013
    Publication date: December 25, 2014
    Inventor: Khaled Mahmoud Abdelfattah Aly
  • Publication number: 20140368960
    Abstract: Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor, and a non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit.
    Type: Application
    Filed: September 25, 2013
    Publication date: December 18, 2014
    Applicant: Cypress Semiconductor Corporation
    Inventors: Supreet Bhanja DEO, Timothy WILLIAMS, Pat MADDEN
  • Patent number: 8913360
    Abstract: Power supplies together with related over voltage protection methods and apparatuses. A power supply has a transformer including a primary winding and an auxiliary winding. A power switch is coupled to the primary winding and a sensing resistor coupled between the power switch and a grounding line. A multi-function terminal of a controller is coupled to the sensing resistor. A diode and a first resistor is coupled between the auxiliary winding and the multi-function terminal.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: December 16, 2014
    Assignee: Leadtrend Technology Corp.
    Inventors: Kuo-Chien Huang, Ren-Yi Chen
  • Patent number: 8913362
    Abstract: A mixed-voltage circuit employs a higher-voltage transistor in series connection with a lower-voltage transistor. To protect the lower-voltage transistor from transient overvoltage events, a series of one or more diodes is connected between the current terminals (i.e., the source and drain terminals) of the lower-voltage transistor so as to limit the voltage across the lower-voltage transistor. This diode protection mechanism also may be provided between the gate terminal and a current terminal of the lower-voltage transistor so as to protect against an overvoltage event at the gate of the lower-voltage transistor. In this manner, the mixed-voltage circuit can provide the performance benefits of mixed use of lower-voltage and higher-voltage transistors while reducing the risk of damaging the lower-voltage transistors due to the use of the higher-voltage power supply needed for operation of the mixed-voltage circuit.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: December 16, 2014
    Assignee: Vixs Systems, Inc.
    Inventor: David Simmonds
  • Patent number: 8913357
    Abstract: An ESD circuit is disclosed. The ESD circuit includes a pad and a ground and a sensing element coupled between the pad and ground for sensing an ESD current. The sensing element generates an active sense output signal when an ESD current is sensed and an inactive sense output signal when no ESD current is sensed. The ESD circuit also includes a bypass element comprising a bi-polar junction transistor. The bypass element is coupled in parallel to the sensing element between the pad and ground. The active sense output signal causes the bypass element to be activated to provide a current path between the pad and ground.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Mahadeva Iyer Natarajan
  • Patent number: 8908341
    Abstract: A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Manjunatha Prabhu, Mahadeva Iyer Natarajan, Da-Wei Lai, Shan Ryan
  • Patent number: 8902554
    Abstract: Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor, and a non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 2, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Supreet Bhanja Deo, Timothy Williams, Pat Madden
  • Patent number: 8896975
    Abstract: Monitoring of a core logic internal voltage regulator output is performed to detect, alarm and put an integrated circuit device into a safe mode when the voltage on the core logic exceeds a safe operating voltage value. This allows putting the integrated circuit devise into a predictable, detectable and safe mode, and to alarm the over-voltage condition to a system monitor to alert on a fault and subsequent fault disposition.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 25, 2014
    Assignee: Microchip Technology Incorporated
    Inventor: Pieter Schieke
  • Patent number: 8896976
    Abstract: There is provide an inverter protection device including: a reference voltage obtaining unit obtaining a reference voltage signal based on output current from an inverter module; a filtering unit removing noise from the reference voltage signal to output the filtered signal; a sensing unit sensing the filtered signal through a sensing terminal; an electrostatic discharge diode provided between the sensing terminal and a ground; and a bypass unit provided between one terminal of the electrostatic discharge diode and the ground.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 25, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Min Gyu Park
  • Patent number: 8891219
    Abstract: A switching device is configured to connect a split-phase power source to a load. The split-phase power source includes a first hot lead, a second hot lead, and a neutral lead. When the split-phase power source is generating power, the voltage between the first hot lead and the neutral lead closes a first contact and the voltage between the second hot lead and the neutral lead closes a second contact. The contacts are connected in series between the first hot lead, the second hot lead and a third switch. The voltage potential present between the first hot lead and the second hot lead closes a third and fourth contact. The third contact is connected in series between the first hot lead and the load and the fourth contact is connected in series between the second hot lead and the load. The switching device protects against open neutral conditions.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: November 18, 2014
    Assignee: Reliance Controls Corporation
    Inventor: Neil A. Czarnecki
  • Publication number: 20140334050
    Abstract: At least one of an electrical circuit, and arc suppression device, and an arc suppressor includes a pair of terminals, an event detection element, and a non-linear current shunt element in series with the event detection element.
    Type: Application
    Filed: May 7, 2014
    Publication date: November 13, 2014
    Inventor: Reinhold Henke
  • Patent number: 8885309
    Abstract: A system includes undervoltage protection circuitry coupled in parallel with electronic circuitry configured to receive a supply voltage from a power supply. The undervoltage protection circuitry is configured to shunt undervoltage current resulting from an undervoltage transient in the supply voltage away from the electronic circuitry.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 11, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Taeghyun Kang, Alister Young, Duane Connerney
  • Patent number: 8879222
    Abstract: A circuit includes a discharge arrangement configured to discharge an electrostatic charge. The discharge arrangement has a discharge state. A first circuit is configured to provide a pulse to the discharge arrangement when the electrostatic charge is sensed. The pulse causes the discharge arrangement to enter the discharge state. A second circuit is configured to maintain the discharge arrangement in the discharge state after the pulse has ended. A third circuit is configured to receive the pulse and to provide a delayed output to the discharge arrangement. The delayed output causes the discharge arrangement to exit the discharge state.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics International N.V.
    Inventor: Gaurav Singh
  • Patent number: 8879221
    Abstract: A device having an ESD module is disclosed. The ESD module includes an ESD circuit coupled between first and second rails and a control circuit coupled between the rails and to the ESD circuit. When the control circuit senses an ESD event, it causes the ESD circuit to create a current path between the rails to dissipate ESD current. When no ESD event is sensed, the control circuit ensures that no current path is created between the rails to prevent latch-up.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Mahadeva Iyer Natarajan, Manjunatha Govinda Prabhu, Ryan Shan
  • Patent number: 8878460
    Abstract: A protection circuit of a DC-DC converter is disclosed. An input terminal of the DC-DC converter receives an input voltage and an output terminal of the DC-DC converter provides an output voltage. The DC-DC converter includes an output stage between the input terminal and the output terminal. The protection circuit includes a current sensor, a comparator, a determining circuit, and a protection control circuit. The current sensor provides a sensing signal. The comparator compares a default over-voltage with the sensing signal to provide an over-current control signal. The determining circuit provides a determining control signal. The protection control circuit determines whether to enable a short protection according to the over-current control signal and the determining control signal.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: November 4, 2014
    Assignee: UPI Semiconductor Corporation
    Inventor: Wen-Fu Lu
  • Patent number: 8879614
    Abstract: The present invention relates to an overpower detection device 51 capable of detecting, with a simple configuration, overpower of a circuit that processes a signal associated with instantaneous variation. The overpower detection device 51 of the present invention includes: a power information acquisition section 61 for acquiring an index value of power, at each timing, of a signal transmitted or received in a target device; a comparison section 62 for comparing the index value acquired by the power information acquisition section 61 with an evaluation threshold; a comparison result accumulation section 63 for accumulating a value indicating a comparison result of the comparison section 62 at the each timing; and an overpower determination section 64 for determining overpower of a circuit in the target device, based on an accumulation result of the comparison result accumulation section 63.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: November 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takashi Maehata
  • Patent number: 8879216
    Abstract: The invention relates to a circuit arrangement (10) for a control device, and a method for operating said circuit arrangement (10). The circuit arrangement (10) comprises a first field-effect transistor (12) actuating the control device, and a comparator, which compares the voltage provided for actuating the control device with a threshold voltage, and which actuates a timed operation of the first field-effect transistor (12) via a control unit (20) if the threshold voltage is exceeded.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: November 4, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Ralph Bauer, Klaus Dressler
  • Publication number: 20140321019
    Abstract: A method for protecting an intermediate circuit capacitor in a power converter circuit is disclosed. The power converter circuit includes at least two submodules in a series circuit, which draws electrical power from a power source outputting a DC voltage via an inductance, wherein each submodule has, on the input side, a single-phase half bridge and, on the load side, a single-phase full bridge, and wherein the half bridge, the full bridge and an intermediate circuit capacitor are connected in parallel with one another on the DC voltage side. When a fault in one of the submodules is detected, transmission of electrical power from the load-side output of the full bridge of the submodule with the detected fault into the submodule with the detected fault is blocked.
    Type: Application
    Filed: November 16, 2012
    Publication date: October 30, 2014
    Inventor: Stefan Völke
  • Publication number: 20140321018
    Abstract: The invention relates to a diagnostic method for multiple-stage excess voltage protection apparatuses that include at least one gas discharge distance between an input and a reference potential as a first stage, at least one diode path between an output and the reference potential as a second stage, and at least one decoupling inductance interposed between the input and the output. The diagnostic method is characterized in that a secondary voltage applied to a secondary inductance, which is actively connected, inductively, to the decoupling inductance, is measured and evaluated with a view to excess voltage events in the excess voltage protection apparatus. The invention also relates to a two-stage excess voltage protection apparatus.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 30, 2014
    Applicant: PEPPERL + FUCHS GmbH
    Inventor: Micha Beutel
  • Publication number: 20140312851
    Abstract: An apparatus for preventing an electric overstress in an electronic device, which is capable of protecting the electronic device from the electric overstress is provided. The apparatus includes an interface unit for connecting the electronic device to an external device, includes an electric power terminal which is included in the interface unit and includes a first electric power terminal and a second electric power terminal which are electrically separated, and an electric overstress preventing unit connected with the first and second electric power terminals.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 23, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Junhyun BYUN
  • Patent number: 8861157
    Abstract: A surge arrestor includes at least one arrestor element, and a disconnecting device for disconnecting the arrestor element from the grid. The disconnecting device includes a thermal disconnect point that is incorporated into the electrical connection path within the arrestor. A moving conductor section or a moving conductive bridge is connected to the arrestor element by way of the disconnect point. A conducting element is disposed in or at the end of the path of motion of the conductor section or of the bridge, the conducting element coming into contact with the conductor section or the bridge when the disconnecting device is triggered. A moving insulation part penetrates into the path of motion of the conductor section or of the bridge directly prior to or upon reaching a short circuit state.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: October 14, 2014
    Assignee: Dehn + Söhne GmbH + Co. KG
    Inventors: Arnd Ehrhardt, Stefanie Schreiter, Christian Burger
  • Patent number: 8861159
    Abstract: The semiconductor device is provided. The semiconductor device includes a substrate, an electrostatic discharge layer disposed on the substrate and including a plurality of electrostatic discharge circuits, at least one semiconductor chip stacked on the electrostatic discharge layer, and a plurality of vertical electrical connections which pass through the at least one semiconductor chip and the electrostatic discharge layer to connect the at least one semiconductor chip to the semiconductor substrate. The vertical electrical connections are connected to the electrostatic discharge circuits, respectively.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Jin Lee, Jang Seok Choi
  • Patent number: 8861163
    Abstract: According to one embodiment, there is provided a protection relay. The protection relay includes an input circuit that detects a state of an external device according to whether or not an external input voltage is larger than a preset threshold voltage. The input circuit includes switching unit that is made conductive by a divided voltage obtained by voltage-dividing resistors that divide the external input voltage when the external input voltage is higher than or equal to the threshold voltage, and a photocoupler that is operated by a constant current of a constant current output circuit supplying a constant current and outputs an operation signal to the operation unit when the switching unit is made conductive.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Shirakawa, Yusuke Yanagihashi, Hiroyuki Maehara, Toshio Tanaka, Noriyoshi Suga, Itsuo Shuto
  • Patent number: 8861151
    Abstract: Disclosed is an overvoltage protection circuit which includes a first terminal through which a first voltage is supplied to an internal circuit; a second terminal through which a second voltage is supplied; a rectifier having an input end connected to the first terminal and having an output end; and first-stage to n-th-stage switching elements which are connected in parallel to one another. The first-stage to n-th-stage switching elements have first to n-th controlling ends, respectively. Each of the switching elements has first and second controlled ends connected to the first terminal and the second terminal, respectively. The rectifier is configured to output a control voltage from the output end thereby to cause the first-stage to n-th-stage switching elements to be turned on, in response to receipt of an overvoltage from the first terminal.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Akihiro Sushihara
  • Patent number: 8861158
    Abstract: A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: October 14, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Dan Zupcau
  • Patent number: 8861160
    Abstract: The present invention provides an integrated circuit having a better ESD protection capability and capable of reducing a circuit layout area. The integrated circuit comprises: an internal circuit, a first pad, and at least a first impedance matching unit. The first impedance matching unit is coupled between the internal circuit and the first pad, and the first impedance matching unit comprises: a first switch unit and a first resistance unit. The first switch unit is coupled to the internal circuit, and the first resistance unit is coupled between the first switch unit and the first pad, wherein the first resistance unit has a first terminal and a second terminal. The first terminal is directly electrically connected to the first pad and the second terminal is coupled to the first switch unit.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: October 14, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chien-Ming Wu, Kai-Yin Liu
  • Patent number: 8861161
    Abstract: A driver circuit and a diagnostic method are provided. The driver circuit includes a first voltage driver, a second voltage driver, and a microprocessor. The microprocessor generates a first pulse width modulated signal to induce the first voltage driver to output a second pulse width modulated signal to energize a contactor coil. The microprocessor sets a first diagnostic flag equal to a first value if a first filtered voltage value is greater than a first threshold value. The microprocessor sets a second diagnostic flag equal to a second value if a second filtered voltage value is greater than a second threshold value. The microprocessor stops generating the first pulse width modulated signal to de-energize the contactor coil if the first and second diagnostic flags are set equal to the first and second values, respectively.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: October 14, 2014
    Assignee: LG Chem, Ltd.
    Inventor: Craig William Grupido
  • Patent number: 8854777
    Abstract: ESD (electrostatic discharge) protection for radio frequency (RF) couplers included in the same semiconductor package as other integrated circuits, such as integrated circuits having power amplifier (PA) circuitry, is disclosed along with related systems and methods. The disclosed embodiments provide ESD protection for RF couplers within semiconductor packages by including coupler ESD circuitry within an integrated circuit within the semiconductor package and coupling the connection ports of the RF coupler to this coupler ESD circuitry. Further, this coupler ESD circuitry can be implemented using two sets of serially connected diodes so that the signal connected to the coupler ESD circuitry can swing around ground without being clipped by the ESD circuitry. Still further, the ESD diodes can be formed in deep N well structures to improve isolation and to reduce parasitic capacitance associated with the ESD diodes.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 7, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Timothy J. Dupuis
  • Patent number: 8854778
    Abstract: An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsien Tsai, Tsun-Lai Hsu, Chew-Pu Jou
  • Patent number: 8854774
    Abstract: A fault current limiter includes a rectifier having AC terminals and direct current (DC) terminals, the AC terminals to be coupled to an AC power source and a load. The fault current limiter further includes a DC diode coupled in parallel across the DC terminals of the rectifier and a DC reactor coupled to the DC diode. When an AC current drawn from the AC power source is less than a predetermined threshold, the DC diode is in a forward bias state to allow the AC current flowing to the load through the DC diode. When the AC current drawn from the AC power source is greater than or equal to the predetermined threshold, the DC diode is in a reverse bias state, forcing the AC current to flow to the load through the DC reactor.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: October 7, 2014
    Inventor: James Nanut
  • Patent number: 8848328
    Abstract: A load driving device according to an exemplary aspect of the present invention includes: an output transistor coupled between a first power supply line and an output terminal, the output terminal being configured to be coupled with a load; a protection transistor that is provided between a gate of the output transistor and a second power supply line, and brings the output transistor into a conduction state when a polarity of a power supply coupled between the first power supply line and the second power supply line is reversed; and a back gate control circuit that controls the second power supply line and a back gate of the protection transistor to be brought into a conduction state in a standby mode when the polarity of the power supply is normal.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: September 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiro Nakahara
  • Publication number: 20140268462
    Abstract: In one general aspect, an apparatus can include an input terminal and an overvoltage protection device coupled to the input terminal and configured to receive energy via the input terminal. The overvoltage protection device can have a breakdown voltage at an ambient temperature less than a target maximum operating voltage of a source configured to be received at the input terminal. The apparatus can also include an output terminal coupled to the overvoltage protection device and a load.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Adrian Mikolajczak
  • Publication number: 20140268463
    Abstract: Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel M. DREPS
  • Publication number: 20140271239
    Abstract: By directly connecting, ballast to an emitter electrode of an ion generator (e.g., a corona-discharge device), a rapid and self-corrective reduction in emitter-to-collector voltage may be provided responsive to an increase in current characteristic of incipient sparking discharge. Voltage levels in the emitter-to-collector gap can be rapidly reduced based on voltage drop across the ballast that, while negligible under nominal ion current conditions, transiently increases in the event of a sparking discharge. As a result, the portion of supply voltage (typically multi-KV supply voltage) across the emitter-to-collector gap is transiently reduced to levels below a current breakdown voltage and, indeed, field intensity proximate to the emitter is transiently reduced below levels otherwise necessary to sustain ion generation.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Inventors: Kenneth Honer, Nels Jewell-Larsen, Wilbur Lau
  • Publication number: 20140268464
    Abstract: An output over-voltage protection circuit for power factor correction, which includes a chip external compensation network, a chip external resistor divider network, a static over-voltage detection circuit, a dynamic over-voltage detection circuit and a compare circuit; The chip external compensation network is connected between the chip external resistor divider network and the dynamic over-voltage detection circuit, the chip external compensation network converts the dynamic over-voltage signal conversion to the dynamic current signal and conveys it to the dynamic over-voltage detection circuit, the dynamic over-voltage detection circuit detects the dynamic current signal and ultimately produces the dynamic over-voltage signal (DYOVP); The dynamic over-voltage signal (DYOVP) is inputted into the compare circuit, which converts the dynamic over-voltage signal (DYOVP) into a voltage compared with a reference voltage and outputs a over-voltage control signal (OVP), so as to achieve a dynamic over-voltage prote
    Type: Application
    Filed: November 9, 2012
    Publication date: September 18, 2014
    Inventors: Guoding Dai, Xiaohui Ma, ChaoYao Xue, Jian Ou, Jing Lu
  • Patent number: 8837101
    Abstract: Aspects of the invention provide for qualifying a new meter with specific power supply requirements. In one embodiment, aspects of the invention include a system, including: an electric meter having a housing; and a voltage-modifying device connected to the electric meter for modifying a received voltage, such that the electric meter operates in accordance with a predetermined power supply requirement, wherein the voltage-modifying device is located within the electric meter housing or external to the electric meter housing.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: September 16, 2014
    Assignee: General Electric Company
    Inventor: Didier Gilbert Rouaud
  • Patent number: 8836166
    Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: September 16, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Gregory A. Maher, Myron J. Miske
  • Patent number: 8830637
    Abstract: Methods and apparatus to clamp overvoltages for inductive power transfer systems are described herein. An example overvoltage protection circuit is described, including a first terminal configured to receive an alternating current signal for conversion to a second signal, a capacitor, a first switch configured to selectively electrically couple the capacitor to the first terminal based on an overvoltage detection signal to reduce an overvoltage on the second signal, and an overvoltage detector. The example overvoltage detector is configured to determine a signal level of the second signal and, in response to determining that the signal level of the second signal is greater than a threshold, to output the overvoltage detection signal to cause the switch to electrically couple the capacitor between the first terminal and a second terminal.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen Christopher Terry, Paul L. Brohlin