Abstract: A non-volatile passive memory element comprising on a single surface a first electrode system and a second electrode system together with an insulating system, unless the insulating system is the surface, wherein the first electrode system is insulated from the second electrode system, the first and the second electrode systems are pattern systems and at least one conductive or semi-conducting bridge is present between the first and second electrode systems, and wherein the non-volatile passive memory device is exclusive of metallic silicon and the systems and the conductive or semiconducting bridges are printable using conventional printing processes with the optional exception of the insulating system if the insulating system is the surface. A non-volatile passive memory device comprising a support and on at least one side of the support the above-mentioned non-volatile passive memory element.

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a plurality of memory cells including diodes, a plurality of bit lines and a first conductive type first impurity region arranged to intersect with the bit lines for functioning as first electrodes of the diodes included in the memory cells and a word line. The first impurity region is divided every bit line group formed by a prescribed number of bit lines along a direction intersecting with the extensional direction of the first impurity region.

Abstract: A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in wafer form or in die form. The first stratum includes functional active devices and at least one non-programmed active device. The second stratum includes at least conductive routing to be associated with the at least one non-programmed active device. The bonded inter-strata connections include at least one bonded programmable inter-strata connection for programming the at least one non-programmed active device and for providing conductive routing to the programmed active device. The two strata thus form a programmed ROM. Other types of programmable storage devices may be implemented by bonding the two strata.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality of semiconductor chips 12 by using the program head 80.

Abstract: There is disclosed a static random access memory (SRAM) device that stores an embedded program that is accessible when the SRAM device is powered up. The SRAM device comprises a plurality of storage cells, each of the storage cells comprises a data latch having an input and an output, wherein the data latch comprises a) a first inverter having an input coupled to the first I/O line and an output coupled to the second I/O line, and b) a second inverter having an input coupled to the second I/O line and an output coupled to the first I/O line. The storage cell also comprises a biasing circuit that forces at least one of the first and second I/O lines to a known logic state when power is applied to the SRAM device. The known logic state comprises one bit in the embedded program.

Abstract: A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control node and first and second switched nodes between which the flow of current is dependent on the voltage applied to the control node, wherein each row has a word line connected to the control nodes of the switches of that row, each column comprises only one switch from each row, and each column has first, second and third bit lines connectable to one of the switched nodes of each switch of that column to define the stored data, the method comprising: fixing the voltage of the second bit line of the switch and reading data from the first and third bit lines, and subsequently: fixing the voltage of the first bit line of the switch and reading data from the second and third bit lines.

Abstract: A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material layer, including a phase-change layer positioned between and in electrical contact with the electrodes, wherein the lateral extent of the phase change layer is less than the lateral extent of the electrodes. An isolation material is positioned between the phase change layer and the dielectric layer, wherein the thermal conductivity of the isolation material is lower than the thermal conductivity of the dielectric material.

Abstract: To provide a memory device which operates with low power consumption, has high reliability of the stored data, and is small-size, light-weight and inexpensive, and a driving method thereof. In addition, to provide a semiconductor device which operates with low power consumption, has high reliability of the stored data and a long distance of radio frequency communication, and is small-size, light-weight and inexpensive, and a driving method thereof. The memory device includes a memory cell array in which at least memory elements are arranged in matrix, and a writing circuit. The memory element has a first conductive layer, a second conductive layer, and an organic compound layer formed therebetween, and the writing circuit includes a voltage generating circuit for generating a voltage in order to apply at plural times, and a timing controlling circuit for controlling output time of the voltage.

Abstract: A semiconductor memory includes a memory cell as a resistance change element and a switching element which are connected in series and a read word line connected to a control terminal of the switching element. In addition, the semiconductor memory includes a circuit which executes an auto-close operation for causing which makes a read word line RWL to be subjected to non-activation automatically after a fixed period from start of a read operation.

Abstract: A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines.

Abstract: A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.

Abstract: The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of memory cells and a redundant block of memory cells. In response to an error in writing to the primary block, a flag is stored in a set of memory cells allocated to the primary block, and the redundant block is written into. In another preferred embodiment, an error in writing to a primary block is detected while an attempt is made to write to that block. In response to the error, the redundant block is written into. In yet another preferred embodiment, a memory device is provided comprising a three-dimensional memory array and redundancy circuitry. In still another preferred embodiment, a method for testing a memory array is provided. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Abstract: A high-density memory device and design method that utilizes some or all of the existing stacked process conductor layers provided by a manufacturing process to enhance the number of available bitlines and/or wordlines within the memory device. The memory device includes a plurality of memory cells arranged in columns and rows, a plurality of wordlines, a plurality of bitlines, at least one via-stack, wherein said existing stacked process conductor layers are used to implement at least one additional wordline or bitline. The via-stacks consist of a plurality of vias, are located close to a memory cell, and adapted to electrically connect the memory cell to multiple bitlines or multiple wordlines or both0. This design method increases the number of possible connections to or from each individual memory cell. When this design method is combined with varied configurations of basic underlying ROM cell types, even further increased cell density can be achieved.

Abstract: A resistive memory cell random access memory device and method for fabrication.

Abstract: A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Abstract: A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response to the signal.

Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A compact mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines, a plurality of bit lines, and a plurality of MOS-type and diffusion-type memory cells arranged in an array. The memory cells in one column are coupled to one bit line, and the gates of the MOS-type cells in one row are coupled to one word line via contacts, wherein two columns of memory cells share a column of contacts. A MOS-type cell shares its source and drain with two memory cells in the same column, and a diffusion-type cell directly connects with the diffusions of two adjacent memory cells. A constant number of continuous memory cells are grouped as a memory string, wherein the two diffusions of the two terminal memory cells are electrically connected to a bank select transistor and a ground line, respectively.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated from the memory cell address. Row select lines or column select lines are pre-charged. A self-timed charging circuit is initiated to provide an adequate amount of time to charge a selected row, and to initiate elimination of static current flowing to unselected rows after a self-timed delay. The other of the row select lines or the column select lines are then pre-charged. Memory cells are selected based upon the column address and the row address. One of two states of the memory cells can be based upon sensing threshold voltages of sense lines that correspond with the selected memory cells.

Abstract: A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.

Abstract: A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Abstract: An NMOS field effect transistor may be utilized to drive the memory cell of a phase change memory. As a result, the leakage current may be reduced dramatically.

Abstract: A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB1 (n) to SB4 (n), selection switches MB1 (n) to MB4 (n), and memory cells M1 (n) to M4 (n). The memory cells M1 (n) to M4 (n) are electrically coupled to the sub-bit lines SB1 (n) to SB4 (n) and the sub-bit line SB1 (n+1), respectively. When the memory cell M3 (n) which is connected to SB3 (n) is read, the sub-bit lines SB1 (n) to SB3 (n) are connected to the corresponding main bit lines through the turned selection switches. At this time, the sub-bit lines SB1 (n) to SB3 (n) are not floating but are all at the same high voltage level. Therefore, the capacitance effect will not exist between them to change the voltage level of the sub-bit lines quickly.

Abstract: A read only memory (ROM) embedded dynamic random access memory (DRAM) has a 6F2 architecture and uses isolation gates as hard shorting connections for ground or supply voltage connections to program ROM bits within the ROM embedded DRAM.

Abstract: One embodiment of the present invention provides a system that updates an error-correcting code for a line when only a portion of the line is updated during a store operation. The system operates by receiving the store operation, wherein the store operation includes new data to be stored to the portion of the line, as well as an address of the portion of the line. Next, the system reads old data for the portion of the line from the address, and then stores the new data to the portion of the line at the address. The system also updates the existing error-correcting code for the line to reflect the new data. This involves calculating a new error-correcting code for the line from the existing error-correcting code, the old data and the new data. The system then replaces the existing error-correcting code with the new error-correcting code.

Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.

Abstract: A one time programmable memory circuit includes a one time programmable memory array. A write circuit outputs data to the one time programmable memory array. A power up write controller outputs the data and a write enable signal to the write circuit. A read circuit outputs data from the one time programmable memory array upon a read enable signal received from a read controller. An address decoder communicates with the power up write controller and the read controller, for providing an address to the one time programmable memory array.

Abstract: A polysilicon film and the like are patterned to form n-diffusion layers on a silicon substrate. Subsequently, an outer edge of an Al2O3 film is made retreat to be smaller than that of a gate electrode by performing isotropic etching of the Al2O3 film, using a solution of sulfuric acid with hydrogen peroxide. A silicon oxide film, a silicon nitride film, the polysilicon film and the like are hardly removed although the solution of sulfuric acid with hydrogen peroxide exhibits higher etching rate to the Al2O3 film, enabling almost exclusive etching of the Al2O3 film at a high selectivity ratio. Subsequently, another polysilicon film is formed so as to fill spaces formed after the retreat of the Al2O3 film under the silicon oxide film. Subsequently, a sidewall insulating film is formed by remaining portions of the later polysilicon film in the spaces by performing RIE, oxidation, or the like of the later polysilicon film.

Abstract: A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a drain of the access transistor, and a second terminal coupled to a corresponding bit line. At most, only one of the anti-fuse elements is programmed. The memory cell is capable of storing M bits, wherein N=2M−1. A method is provided for both programming and reading the memory cell. In another embodiment, the anti-fuse elements can be replaced with mask-programmable elements.

Abstract: The present invention provides a semiconductor device and a testing method capable of easily detecting a short circuit in a memory circuit with high precision and efficiently detecting a short circuit in a memory circuit. A memory circuit in which memory cells are disposed at intersections of a plurality of word lines and a plurality of bit lines performs, in a test mode, an operation of applying a predetermined potential to neighboring ones of a plurality of word lines or bit lines, an operation of selecting a plurality of word lines and applying a ground potential of the circuit to all of the plurality of bit lines, and an operation of setting all of the plurality of bit lines at a predetermined potential corresponding to the selection level of the word lines and setting all of the plurality of word lines into a non-selection state.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A memory device comprising a normal memory cell array and a spare memory cell array, in which memory cells each comprising a ferroelectric capacitor are arranged, a normal word line, a normal word line driver, a spare word line, a spare word line driver, an address input circuit to which an address signal is inputted, and a judging circuit which compares an input address with a faulty address and generates an output for selecting one of the normal and spare word line drivers according to the comparison, wherein the normal and spare word line drivers are simultaneously selected by an output of the address input circuit to start driving the normal and spare word lines, and thereafter the normal and spare word line drivers are enabled by the output of the judging circuit to stop the driving of one of the normal and spare word lines and continue the other.

Abstract: A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lines and word lines. Memory cells are defined at intersections of bit lines and word lines, and have dimensions that are defined by the widths of the bit lines and word lines in a self-aligned process. The memory cells comprise structures including a selection device, a heating/barrier plate layer and a phase change memory element, vertically arranged at the intersections of the bit lines and word lines.

Abstract: A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation element to be operated on the chip. In which case, as soon as the isolation information item is present for an isolation element, a one-time operation on the isolation element is begun.

Abstract: A read only memory (ROM) embedded dynamic random access memory (DRAM) has a 6F2 architecture and uses isolation gates as hard shorting connections for ground or supply voltage connections to program ROM bits within the ROM embedded DRAM.

Abstract: A metal programmable ROM includes a memory cell array having a depth defined by a plurality of wordlines and a width defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and a ground conection, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is defined by a memory cell transistor having its terminals shorted together.

Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.

Abstract: Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least some of the interconnections being disposed along axes oriented obliquely to the first and second arrays. First and second sets of oblique axes of interconnections may be parallel or opposed to each other. The interconnections may include obliquely slanted pillars or stair-stepped pillars disposed along the oblique axes. Methods for fabricating and using such structures are disclosed.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: By eliminating a current of bit lines which is generated regularly by an off-leak current in memory cells, the number of memory cells per bit line is made to increase, large storage capacity of the memory cell array is achieved, and a semiconductor memory device capable of reducing a chip area is provided. In order to achieve it, provided is a source line potential control circuit for setting a source potential of transistors included in the memory cells being selected by row selection signals at a ground potential, and for setting a source potential of the transistors included in the memory cells being set as a non-selection state by the row selection signals at a power potential. A potential difference between sources and drains of the transistors included in the memory cells of the non-selection state is thereby reduced, and the leakage current is eliminated.

Abstract: A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>=2. Each column includes 2N conductive lines; each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2N connections from among the set of 22N possible connections; and each of N read means is provided to apply a precharge voltage to a chosen group of 2N−1 first lines, connect the 2N−1 other lines to a reference voltage, select a memory point, read the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.

Abstract: A semiconductor memory device includes: a memory cell region having main virtual ground lines; and a reference cell region having reference virtual ground lines, and the reference cell region having substantially the same interconnection routine as said memory cell region, wherein, in said reference cell region, adjacent reference cells to a selected reference cell to be referred are off-bit cells.

Abstract: A 3-dimensional read only memory includes vertically stacked layers of memory cells. Each of the memory cells includes a mask programmed insulating layer, a pair of diode components, and a pair of crossing-conductors. The conductors (other than those at the top and the bottom of the array) each connect to both overlying conductors via overlying memory cells and to underlying conductors via underlying memory cells.

Abstract: A novel encoding system, compositions for use therein and methods for determining the source, location and/or identity of a particular item or component of interest is provided. In particular, the present invention utilizes a collection of one or more sizes of populations of semiconductor nanocrystals having characteristic spectral emissions, to “track” the source or location of an item of interest or to identify a particular item of interest. The semiconductor nanocrystals used in the inventive compositions can be selected to emit a desired wavelength to produce a characteristic spectral emission in narrow spectral widths, and with a symmetric, nearly Gaussian line shape, by changing the composition and size of the semiconductor nanocrystal. Additionally, the intensity of the emission at a particular characteristic wavelength can also be varied, thus enabling the use of binary or higher order encoding schemes.

Abstract: A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source to permanently program the first latch and the second latch to permanent ROM values.

Abstract: A level of a solid state memory device includes main memory and address logic. The address logic includes first and second groups of address elements. Current-carrying capability of the first group of address elements is greater than current-carrying capability of the second group of address elements. Current flowing through the address elements during programming causes the resistance states of only the second group of address elements to change.

Abstract: A Mask ROM testing device is described. The Mask ROM testing device comprises a substrate, a plurality of buried bit-lines in the substrate and a plurality of word-lines on the substrate perpendicular to the buried bit-lines. Each buried bit-line has two end portions with a combined length of about 3˜30 &mgr;m and can have an N-type conductivity or a P-type conductivity.