Capacitors Patents (Class 365/149)
  • Patent number: 10636479
    Abstract: A semiconductor memory device includes a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, a second bit line that is connected to a second terminal of the second transistor, and a controller that turns on the first transistor and turns off the second transistor during a write operation on the first memory cell and turns on the first transistor and the second transistor during a read operation on the first memory cell.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Ikeda, Chika Tanaka
  • Patent number: 10629443
    Abstract: A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • Patent number: 10622057
    Abstract: A sensing system can read from a memory cell configured to store a data bit and to produce a differential signal indicating a data state of the memory cell. The data state can be selected from three data states. An example of the system can include a pair of bit lines, a pair of sense amplifiers (SAs), and a data output circuit. The bit lines are coupled to the memory cell to receive the differential signal. The SAs are each independently coupled to the bit lines through an isolation circuit. The data output circuit can receive outputs from the SAs and indicate the data state of the memory cell based on the outputs.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Charles L. Ingalls, Scott J. Derner
  • Patent number: 10622070
    Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell without a selector device. In another embodiment, a method of operating a ferroelectric memory cell without a selector device is described. Other embodiments are likewise described.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 14, 2020
    Assignee: AP Memory Corp, USA
    Inventor: Wenliang Chen
  • Patent number: 10600475
    Abstract: This invention uses a novel mechanism to store a matrix of numbers or any two dimensional array of binary values in a novel storage entity called a Matrix Space. A matrix space which may reside in a processing unit, is designed to store a plurality of matrices or arrays of values into arrays of volatile or non-volatile memory cells or latch or flip-flop elements much like in a memory, but with accessibility in two or three dimensions. In this invention any row and/or any column of storage elements in a storage array is directly accessible for writing, reading or clearing via row bit lines and column bit lines, respectively. The elements in rows of arrays are selected or controlled for access using row address lines and the elements in columns of arrays are selected or controlled for access using column address lines. This allows access to data stored in matrix space arrays for use in matrix and array computations, by both rows and columns of the arrays.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 24, 2020
    Inventor: Sitaram Yadavalli
  • Patent number: 10558613
    Abstract: A storage system in one embodiment comprises a plurality of storage devices storing data pages. Each data page has a content-based signature derived from that data page. The content-based signatures are associated with physical locations storing the data pages. In response to receipt of a write input/output (IO) request that includes a data segment that is smaller than a page granularity of the storage devices, a content-based signature associated with the data segment is determined which also corresponds to a target data page stored at one of the physical locations. In response to determining the content-based signature, an inflight write count corresponding to the content-based signature is incremented. In response to a decrement request to decrement a reference count of the physical location corresponding to the content-based signature, a decrement flag corresponding to the content-based signature is set in the data structure and the decrement request is postponed.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: February 11, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Lior Kamran, Oran Baruch
  • Patent number: 10553594
    Abstract: Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 10553726
    Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: February 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kosei Noda, Kouhei Toyotaka, Kazunori Watanabe, Hikaru Harada
  • Patent number: 10539997
    Abstract: The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances tradeoffs between reduced power consumption and performance impacts. For example, according to various aspects, individual memory blocks may be associated with an access-dependent age, whereby memory blocks that are not accessed may be periodically aged. As such, in response to the age associated with a memory block crossing an appropriate threshold, the memory block may be transitioned to a power state that generally consumes less leakage power and has a larger performance penalty. Furthermore, one or more performance-related criteria may be defined with certain memory blocks to prevent and/or automatically trigger a transition to another power state.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: January 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Giby Samson, Parixit Laljibhai Aghera, Adam Edward Newham
  • Patent number: 10535399
    Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10529720
    Abstract: A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10529425
    Abstract: A semiconductor apparatus may include a unit memory region, a first column main decoder, a second column main decoder, and a control circuit. The unit memory region may include a plurality of sub-memory regions. The first and second column main decoders may be configured to receive and decode a column pre-decoding signal and configured to generate a respective column select signal for controlling a column access of a respective first and second half of the plurality of sub-memory regions. The control circuit may be configured to provide the column pre-decoding signal to the first or second column main decoders based on their proximities to a sub-memory region to be enabled among the plurality of sub-memory regions.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Ji, Sang Ho Lee, Ho Don Jung, Jun Hyun Chun
  • Patent number: 10529401
    Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10529410
    Abstract: Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Lucia Di Martino
  • Patent number: 10529413
    Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Junpei Sugao
  • Patent number: 10522214
    Abstract: A reliability aware negative bit-line write assist (RA-NBL) circuit comprises a coupling capacitor to provide a negative bump for write assist, and a control input generator control charging of the coupling capacitor, such that the negative bump is high at a low voltage, and the negative bump is low at a high voltage.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: December 31, 2019
    Assignee: Synopsys, Inc.
    Inventors: Sudhir Kumar, Vinay Kumar, Sumit Srivastava, Nikhil Puri
  • Patent number: 10505108
    Abstract: A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 10, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Jun Deguchi, Yoshifumi Nishi, Masamichi Suzuki, Fumihiko Tachibana, Makoto Morimoto, Yuichiro Mitani
  • Patent number: 10497420
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Smith, Michael A. Shore
  • Patent number: 10497428
    Abstract: A semiconductor memory device includes a memory cell that stores multi-bit data, and a bit line sense amplifier that is connected to a bit line of the memory cell and a complementary bit line corresponding to the memory cell in an open bit line structure. The bit line sense amplifier includes a first latch that sequentially senses a first bit and a second bit of the stored multi-bit data and transmits the sensed first bit to a second latch, and a second latch that senses the transmitted bit from the first latch.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungryun Kim, Younghun Seo, Soobong Chang
  • Patent number: 10489309
    Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: David A. Koufaty, Gilbert Neiger, Rajesh M. Sankaran, Andrew V. Anderson, Subramanya R. Dulloor, Werner Haas, Joseph Nuzman
  • Patent number: 10482951
    Abstract: The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: November 19, 2019
    Inventor: Chao-Jing Tang
  • Patent number: 10482981
    Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Vinh Diep
  • Patent number: 10461211
    Abstract: The invention pertains to a process for producing an array (1) of mesa-structured photodiodes (2), including at least the following steps: a) producing a useful layer (3); b) producing an etch mask formed of a plurality of etch pads (20); c) wet-etching part of the useful layer (3) located between the etch pads (20), forming a plurality of mesa-structured photodiodes (2), producing a recess (21); d) conformally depositing a passivation layer (14); e) removing the etch pads (20) by chemical dissolution; f) producing conductive pads (11).
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 29, 2019
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Giacomo Badano, Clement Lobre, Roch Espiau de Lamaestre, Jean-Paul Chamonal
  • Patent number: 10453863
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: October 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Patent number: 10447345
    Abstract: An embodiment near-field communication (NFC) router, includes a first switch coupled between a first terminal of the NFC router and a second terminal of the NFC router; and a rectifier bridge having an output terminal coupled to a control terminal of the first switch, the rectifier bridge being configured to rectify a signal detected by an antenna external to the NFC router.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 15, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nathalie Vallespin
  • Patent number: 10446199
    Abstract: A semiconductor device may include a latch circuit configured for storing a row address including information on a position where a smart refresh operation has been performed, as a storage address. The semiconductor device may include a refresh control circuit configured for controlling, depending on a result of comparing a row address inputted from an exterior and the storage address, a smart refresh operation to be performed for the row address, and omitting the smart refresh operation based on the row address and the storage address being the same combination.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang Ah Hyun, Yunyoung Lee
  • Patent number: 10423203
    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Rafael Rios, Somnath Paul, Muhammad M. Khellah
  • Patent number: 10424350
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. The sensing circuitry includes a primary latch and a secondary latch. The primary latch is coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines. The secondary latch is selectively coupled to the primary latch. The primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch. The primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10410964
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Patent number: 10403627
    Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 3, 2019
    Assignee: IMEC vzw
    Inventors: Jan Van Houdt, Julien Ryckaert, Hyungrock Oh
  • Patent number: 10403388
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric current relationship, such as a short, between cells that make up the pair. Cells may be arranged in cell plate groups, and a pair of cells may include a first cell plate from one cell plate group and a second cell plate from the same cell plate group or from another, adjacent cell plate group. So a pair of cell plates may include cell plates from different cell plate groups. The first and second cell plates may be selected as a pair or a group based at least in part on the electric current relationship between the cell plates.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Charles L. Ingalls
  • Patent number: 10403389
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10394618
    Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Briana E. Foxworth, Saravanan Sethuraman, Kevin M. Mcilvain, Lucas W. Mulkey, Adam J. McPadden
  • Patent number: 10395992
    Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10388360
    Abstract: An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. The example apparatus further includes a component positioned outside the edge array section and proximate the first sensing circuitry, the component configured to perform an operation based on data sensed by the first sensing circuitry.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10373682
    Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 6, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ward Parkinson, James O'Toole, Thomas Trent
  • Patent number: 10361204
    Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Slmsek-Ege, Diem Thy N. Tran
  • Patent number: 10354714
    Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Donald M. Morgan
  • Patent number: 10346227
    Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: July 9, 2019
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 10341571
    Abstract: In various embodiments, an image sensor and related methods of operation of the image sensor are disclosed. In an embodiment, an image sensor includes at least one pixel. The at least one pixel including a transistor to couple an overflow capacitor to a floating diffusion node. Under a low light condition, photocharge is to be collected in a floating diffusion, but substantially not into an overflow node. Under a high light condition, photocharge is to overflow into the overflow node. Other sensors and related operations are disclosed.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: July 2, 2019
    Assignee: INVISAGE TECHNOLOGIES, INC.
    Inventors: Emanuele Mandelli, David Michael Boisvert, Nikolai Bock
  • Patent number: 10332581
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 25, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Keiji Ikeda, Chika Tanaka, Toshinori Numata, Tsutomu Tezuka
  • Patent number: 10332580
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10324645
    Abstract: A data storage method for a data storage device is provided. The data storage method includes steps of: determining whether a power drop/loss event occurs; when the power drop/loss event is determined to have occurred, recording a voltage level of a charge storage device, wherein the charge storage device provides power to the data storage device during the power drop/loss event; determining whether the charge storage device is operating normally according to the recorded voltage level of the charge storage device; and when the charge storage device is determined to be not operating normally, configuring the data storage device to enter a safe operation mode. A data storage device is also provided.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 18, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Tsai-Fa Liu, Hung-Lian Lien
  • Patent number: 10319431
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 10304516
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a storage area and a control device. The storage area includes a memory row. The control device is configured to selectively allow the memory row to be eligible for a row-hammer refresh according to temperature of the DRAM.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 28, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-jen Chen
  • Patent number: 10305457
    Abstract: A voltage trimming circuit includes a comparator, a code generator, nonvolatile storage device, a switch circuit, and a voltage generator. The comparator compares a reference voltage with a feedback voltage. The code generator generates a plurality of trimming codes for trimming the feedback voltage based on the comparison result of the comparator. If the feedback voltage is less than the reference voltage, the code generator adjusts up codes to increase the feedback voltage, from among the plurality of trimming codes and maintains down codes to decrease the feedback voltage, from among the plurality of trimming codes at an initial value. If the feedback voltage is greater than the reference voltage, the code generator adjusts the down codes and maintains the up codes at an initial value.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye Jung Kwon, Younghun Seo
  • Patent number: 10290747
    Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10276792
    Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: April 30, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ming-Che Wu, Tanmay Kumar
  • Patent number: 10276230
    Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10269441
    Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, William C. Waldrop