Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array receives a first power supply voltage and includes a plurality of bit cells that store data based on the first power supply voltage. The peripheral circuit is receives a second power supply voltage and controls the memory cell array based on the second power supply voltage. The peripheral circuit includes a voltage generation circuit that receives the first power supply voltage and the second power supply voltage. The voltage generation circuit adaptively adjusts a word-line driving voltage directly or indirectly based on a difference between the first power supply voltage and the second power supply voltage during a memory operation on the plurality of bit cells, and applies the word-line driving voltage to a first word-line coupled to first bit cells selected from the bit cells.

Abstract: A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL1) and a gate of a first pull-down device (PD1). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL2) and a gate of a second pull-down device (PD2) and the gate of the PD1 is directly under the gate of the PD2.

Abstract: A method for detecting unreliable bits in transistor circuitry includes adjusting a value of a variable capacitor coupled to a physical unclonable function (PUF) cell of a transistor circuit. The adjusting includes tilting the PUF cell to either a zero or one state: if the PUF cell changes its state during the tilting it is deemed unstable, and if the PUF cell does not change its state during the tilting it is deemed stable.

Abstract: A microelectromechanical device, in particular a non-volatile memory module or a relay, comprising: a mobile body including a top region and a bottom region; top electrodes facing the top region; and bottom electrodes, facing the bottom region. The mobile body is, in a resting condition, at a distance from the electrodes. The latter can be biased for generating a movement of the mobile body for causing a direct contact of the top region with the top electrodes and, in a different operating condition, a direct contact of the bottom region with the bottom electrodes. In the absence of biasing, molecular-attraction forces maintain in stable mutual contact the top region and the top electrodes or, alternatively, the bottom region and the bottom electrodes.

Abstract: Memory circuit for implementing logic operations and provided with memory cells, in particular of structure 6T, with a control circuit configured to activate the first access transistors or the second access transistors of at least two cells of the same given column and for detecting from a low- or high-voltage power supply line, from said given column, separate from the bit lines, a signal representative of the result of a logic operation having for operands data stored in said at least two cells.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

Abstract: A method uses data retention time (DRT) characteristics of a logic-compatible gain-cell embedded DRAM (dynamic random-access memory) (GC-eDRAM) array in a transistor circuit as a source for physical unclonable function (PUF) signature extraction of the circuit.

Abstract: A memory circuit includes a memory array with one or more reference columns providing a reference signal and a data column providing a data signal when selected by a read operation. The memory circuit also includes a first circuit that removes a common signal component from the reference signal and from the data signal, along with a second circuit that adjusts the reference signal to be between a logic 1 signal level and a logic 0 signal level. The memory circuit also includes a sense amplifier that determines whether the data signal represents a logic 1 or a logic 0 using the reference signal after the common signal component is removed and after being adjusted, along with the data signal after having the common signal component removed.

Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.

Abstract: A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor. The first inverter has a first latch node and the second inverter has a second latch node. The write transistor is coupled in series with a wordline transistor between the first latch node of the first inverter and a bitline. The read transistor is coupled between the bitline and a reference terminal and has a control terminal coupled to the first latch node of the first inverter. A method of operating the static random access memory cell includes enabling the wordline transistor during a write operation, and enabling the write transistor during the write operation. The reference terminal is set to floating during the write operation.

Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving a layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region, and a gate via positioned at a location along the width. The location is used to divide the width into a plurality of width segments, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with a design specification.

Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.

Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

Abstract: An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

Abstract: An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bl-sects for an extended period of time, to save power.

Abstract: Disclosed herein are techniques for performing memory access. In one embodiment, an integrated circuit may include a memory device, a first port to receive first data elements from a memory access circuit within a first time period, and a second port to transmit second data elements to the memory access circuit within a second time period. The memory access circuit may receive the first data elements from the memory device within a third time period shorter than the first time period and transmit, via the first port, the received first data elements to a first processing circuit sequentially within the first time period. The memory access circuit may receive, via the second port, the second data elements from a second processing circuit sequentially within the second time period, and store the received second data elements in the memory device within a fourth time period shorter than the second time period.

Abstract: An adaptive interface high availability storage device. In some embodiments, the adaptive interface high availability storage device includes: a rear storage interface connector; a rear multiplexer, connected to the rear storage interface connector; an adaptable circuit connected to the rear multiplexer; a front multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the front multiplexer. The adaptive interface high availability storage device may be configured to operate in a single-port state or in a dual-port state. The adaptive interface high availability storage device may be configured: in the single-port state, to present a single-port host side storage interface according to a first storage protocol at the rear storage interface connector, and in the dual-port state, to present a dual-port host side storage interface according to the first storage protocol at the rear storage interface connector.

Abstract: A memory array is described herein that includes a static random-access memory (SRAM) array to store data. The memory array also includes a bit circuit to retrieve the data from the SRAM array, the bit circuit to be operated with a clock signal that oscillates between a low state and an intermediate state, wherein the intermediate state is between the low state and a high state. Furthermore, the memory array includes a sense amplifier to amplify an output signal from the bit circuit indicating a value of the stored data, wherein the sense amplifier does not include a cross coupled positive field-effect transistor.

Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driving arrangement. The distributed write driving arrangement includes: a global write driver including a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line; and a local write driver included at an interior of each segment, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar line.

Abstract: A server and method for supporting device registration by the server are provided. The present disclosure relates to a sensor network, Machine Type Communication (MTC), Machine-to-Machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

Abstract: Systems, methods, and apparatus for complementary self-limiting logic are disclosed. In one or more embodiments, a method for mitigating errors caused by transients in a logic gate transistor comprises biasing, by a first stage of transistors, a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential. The method further comprises biasing, by the second stage of transistors, the logic gate transistor such that a voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.

Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.

Abstract: Semiconductor structures are provided. A memory cell includes a latch circuit formed by two cross-coupled inverters and a pass-gate transistor coupling an output of the latch circuit to a bit line. Each cross-coupled inverter is connected to a VDD line of a first metallization layer. A word line of a second metallization layer is connected to a gate of the pass-gate transistor through a first via over the gate of the pass-gate transistor, a first landing pad of the first metallization layer, and a second via over the first landing pad. A source/drain region of the pass-gate transistor is connected to the bit line of a third metallization layer through a contact over the source/drain region, a third via over the contact, a continuous via-plug over the third via, and a fourth via over the continuous via-plug. The continuous via-plug penetrates the first and second metallization layers.

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.

Abstract: Disclosed is a multi-port memory array configured to minimize resistance-capacitance (RC) delay caused by wordline coupling. In each row of the array, a first voltage boost circuit is connected to the distal ends of a first wordline and a second wordline and boosts a first voltage on the first wordline during an access period when the first voltage is transitioning from low to high and when, concurrently, a second voltage on the second wordline is either low or transitioning to low. Optionally, a second voltage boost circuit is also connected to the distal ends of the first and second wordlines and boosts the second voltage on the second wordline during a different access period when the second voltage is transitioning from low to high and when, concurrently, the first voltage on the first wordline is either at low or transitioning from high to low. Also disclosed is a corresponding method.

Abstract: The present information processing apparatus is provided with a flash memory divided into a plurality of areas based on characteristics of information to be stored therein. The present information processing apparatus detects a problem in data stored in each area using a different method for each area, and repairs the detected problem using a different method for each area.

Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.

Abstract: Disclosed approaches for managing a translation look-aside buffer (TLB) have a bus master circuit that issues a read request that specifies a first virtual address of a first page. In response to a sequential access being identified and before data of the first page is returned, the bus master circuit issues a dummy read request that specifies a second virtual address of a second page. A TLB has mappings of virtual addresses to physical addresses, and a translation logic circuit translates virtual addresses to physical addresses. The translation logic circuit signals a miss in response to absence of a virtual address in the TLB. A control circuit in the MMU determines from a page table a mapping of a virtual address to a physical address in response to the signaled miss. The translation logic circuit updates the TLB circuit with the mapping.

Abstract: In one embodiment, there is a system comprising a first group of blocks connected to a first address line, a second group of blocks connected to a second address line separate and distinct from the first address line, a host controller (or memory device) configured to: allocate a single open block to each of: the first group of blocks connected to the first address line that transmits an address signal generated by a first peripheral circuitry module, and the second group of blocks connected to the second address line that transmits an address signal generated by a second peripheral circuitry module; in response to receiving a first program request: program the open block in the first group of blocks connected to the first address line in response to a first program request in response to receiving a second program request separate and distinct from the first program request: forego programming any of the blocks in the first group of blocks connected to the first address line; and program one of the blocks in

Abstract: Disclosed herein is a method of operating a non-volatile static random access NVSRAM memory formed from words. Each word includes NVSRAM cells, each of those NVSRAM cells having an SRAM cell and an electronically erasable programmable read only memory EEPROM cell. If the SRAM cells of a word have been accessed since powerup, data is read from the NVSRAM cells of that word through the SRAM cells. However, if the SRAM cells of that word have not been written since powerup, data is read from the NVSRAM cells of that word through the EEPROM cells.

Abstract: A static random access memory (SRAM) bit cell and a related SRAM array are provided. In one aspect, an SRAM cell is configured to perform an XNOR function on a first input value and a second input value. In another aspect, a number of the SRAM cells can be employed to form an SRAM array for supporting deep neural network and machine learning applications. The SRAM cell is coupled to a word line(s) and an inverted word line(s) that collectively define the first input value. The SRAM cell causes a voltage and/or current difference between a bit line(s) and a complementary bit line(s) coupled to the SRAM cell. By customizing the SRAM cell to enable the XNOR function and forming a binary neural network based on the SRAM array, it is possible to effectively implement computing-in-memory (CIM) for deep neural network and machine learning applications.

Abstract: An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract: Disclosed is a semiconductor storage device having a dual-port SRAM cell with a smaller area and low-current consumption and securing a good static noise margin. The semiconductor storage device includes a memory cell circuit constituting the dual port SRAM cell comprised of six transistors. When driving the first or second word line, a word line driver circuit lowers a high-level voltage which is to be output to the driven word line such that the high-level voltage is lower than a high-level voltage which is to be output to both of the first and second word lines when driving both the first and second word lines.

Abstract: SRAM arrays are provided. In each SRAM cell arranged in a column of cell array, a pull-down transistor and a pass-gate transistor are formed in P-type well region. A pull-up transistor is formed in N-type well region. At least one well strap cell includes an N-well strap structure formed on the N-type well region and a P-well strap structure formed on the P-type well region. A first distance between the active region of the P-well strap structure and the N-type well region is greater than a second distance between an active region of the pull-down transistor and the pass-gate transistor and the N-type well region.

Abstract: PMOS-based temperature compensated read-assist circuits for low-Vmin 6T SRAM bitcells realized in nanometer scale (e.g., 7 nm) CMOS FinFET technologies generate maximum wordline lowering (lower wordline voltages) at higher temperatures and minimum wordline lowering (higher wordline voltages) at lower operating temperatures in way that is substantially process independent and avoids post-silicon tuning. A read-assist PMOS transistor is connected between an associated wordline and VSS and controlled by a temperature compensation signal produced at an intermediate node between weak pull-up and strong pull-down PMOS transistors that are connected in series between VDD and VSS and respectively controlled by VDD and VSS during read operations. This configuration generates the temperature compensation signal at a level closer to VSS at high temperatures than at low temperatures, whereby write-ability is not impacted by the read-assist circuit at low temperature.

Abstract: The present disclosure relates to an electronic device. A storage device having improved reliability may include a memory device performing a program operation of storing data in selected memory cells, among a plurality of memory cells included in a memory block, and a memory controller controlling the memory device to perform a retention control operation of applying a retention control voltage to at least one source line coupled to a plurality of memory cell strings included in the memory block for a predetermined time duration when the program operation is completed.

Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.

Abstract: One illustrative device includes, among other things, a first resistive storage element; a second resistive storage element; and logic to couple the first resistive storage element and the second resistive storage element in a series arrangement in a first configuration and to couple the first resistive storage element and the second resistive storage element in a parallel arrangement in a second configuration.

Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.

Abstract: An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.

Abstract: A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.

Abstract: A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM.

Abstract: To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.

Abstract: An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit.