Abstract: Bipolar transistor memory cell and method for use in a random access memory. A pair of state elements are cross coupled so that they assume opposite states in accordance with signals applied thereto, a pair of bipolar pass transistors are connected to respective ones of the state elements for applying signals to the state elements, and current flow through the pass transistors is monitored to determine the states of the state elements.

Abstract: A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to both load transistors, are connected to a drain line. The word line is connected to an emitter common to both of the load transistors. The cell is connected to a bit line pair through Schottky Barrier Diodes (SBD's) or, alternatively, through emitters of transistors which share a common base and a common collector with the cross coupled storage transistors.

Abstract: Disclosed is a bipolar SRAM including, in each memory cell, two NPN multiemitter transistors, with a base of one transistor being cross-connected to a collector of the other transistor. The respective collectors of these two multiemitter transistors in an arbitrary memory cell are connected to the same positive word line through a load. The first emitter of one of these two multiemitter transistors and the first emitter of the other transistor are connected to the same negative word line. Only when the positive word line corresponding to this negative word line is not selected, a data holding current flows to the negative word line from the first emitter of the transistor having a H level collector potential out of these two multiemitter transistors, and when the corresponding positive word line is selected, the negative word line is controlled not to allow the data holding current to flow.

Abstract: A bit line discharge and sense circuit is provided for use with a static RAM that includes a row and column array of memory cells addressable via first and second bit lines and also a row select line. Each memory cell includes a transistor pair, wherein the first and second bit lines are coupled to an emitter of a first and second transistor comprising the transistor pair. The invention couples two current sources via the associated bit lines to the emitter of each transistor in the cell. A first current source is coupled when the cell is selected and provides a first current value having a bit line capacitance discharge current component and a first transistor read current component. A second current source is coupled to the same emitter when the cell is selected, and provides a lower current value. The first current source rapidly discharges capacitance associated with the associated bit line on the selected cell.

Abstract: A heterojunction bipolar transistor formed as a collector top or emitter top type. This heterojunction bipolar transistor can operate at high speed and can be fabricated into a semiconductor integrated circuit with ease. The manufacturing method thereof is also disclosed.

Abstract: A bipolar memory array arranged in a row and column matrix is responsive to a plurality of word line driver transistors for selecting one row of memory cells thereof. The current flowing through each memory cell is provided by a pair or lateral PNP transistor current source loads. The collectors of the word line driver transistors are commonly connected for distributing the source of collector current flowing therethrough between the bases of all of the laterla PNP transistor current sources of the entire memory array which maintains a constant current flow through each of the memory cells during the select and deselect cycles thereby maintaining a constant memory cell array power dissipation which allows for expanded capacity of the memory array and a performance improvement.

Abstract: A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for forming an address signal for the memory section and address signal delivering means for delivering the address signal for the memory section to the decode means. The address signal delivered from the address signal delivering means is defined by complementary signals.

Abstract: A multiple port memory includes memory cells with merged PNP and NPN bipolar transistors. Each memory cell has a pair of PNP load transistors and a pair of NPN control transistors in a symmetric arrangement. One or more storage ports provides differential signals on two lines which can modify current flow in the memory cell. Similarly, one or more retrieval ports can be connected to two lines connected to the memory cell for reading current flow in the memory cell.

Abstract: A bipolar random access memory comprises a plurality of memory cells arranged in row and column formation, a plurality of word lines provided in correspondence to respective rows of the memory cells, a plurality of bit lines provided in correspondence to respective columns of the memory cells, a row addressing part connected to each of the plurality of word lines, a column addressing part connected to each pair of the adjacent bit lines, a read/write controller supplied with a cell information to be written into an addressed memory cell and further with a read/write control signal indicating whether the random access memory is to be operated in a reading mode or in a writing mode and acting as a current source in the reading and writing modes, a first current control part provided in each column of the memory cells so as to be connected to one of the bit lines in a column selected by the column addressing part at the first side of each of the memory cells, a second current control part provided in each column

Abstract: An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary transistors are biased to a standby current that, in combination with the parasitic capacitances in the new cell, establishes a time constant sufficient to maintain the state of the secondary nodes during an alpha hit on the primary nodes, so that alpha immunity is achieved without added capacitance. A write boost circuit increases the current in the secondary transistors during a write operation. A memory array is formed of rows of such cells with all of the secondary emitters of each row coupled to a common emitter standby current source.

Abstract: There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the individual word lines. The word lines implemented are formed from at least a pair of stacked conductive layers and which layers have interposed therebetween an insulating film. The pair of layers form a pair of wiring lines wherein together they form a work line and wherein the wiring lines are, furthermore, interconnected at predetermined intervals along the lengths thereof. This leads to the ability to decrease the chip size of semiconductor integrated circuits noting that a decrease in the voltage drop of a signal line results, and to prevent electromigration in the signal (wiring) lines.

Abstract: A switched load diode cell has been developed wherein first and second multi-emitter NPN transistors are provided having bases cross coupled to the other's collectors in typical latch fashion as shown in FIG. 5. A PN diode is provided having an anode coupled to the select line through a load resistor and a cathode coupled to the collector of each associated multi-emitter transistor. A parasitic lateral PNP transistor associated with the PN diode is provided having an emitter coupled to the select line through the same load resistor and a collector connected to the base of the associated multi-emitter transistor. A relatively low resistance load of about 500.OMEGA. is connected between the common node which consists of the emitter of the parasitic lateral PNP transistor and the anode of the PN diode and the select line. In this way, a switched load diode cell is provided.

Abstract: A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for forming an address signal for the memory section and address signal delivering means for delivering the address signal for the memory section to the decode means. The address signal delivered from the address signal delivering means is defined by complementary signals.

Abstract: Two pairs of bit lines are associated with each column of memory cells in a static random access memory (RAM) to provide separate paths for reading and writing operations or to provide a RAM having dual read ports. One pair of bit lines is connected to the emitters of the cross-coupled transistors in each cell to permit write operations to be carried out. The second pair of bit lines is connected to the collectors of clamping transistors which limit the collector voltage of the cell transistors, to permit data to be read.

Abstract: A memory cell circuit with a pair of load bipolar transistors and a pair of control bipolar transistors, and with a pair of supplemental transistors providing current shunts.

Abstract: A sense amplifier is provided for a bipolar random access memory that has memory cells arranged in a column and a pair of bit lines for said column of memory cells. A first bipolar transistor has its collector-emitter path coupled to one of the bit lines of a pair, and a base coupled through a diode means to the second bit line. A second bipolar transistor has its collector-emitter path coupled to the second bit line and its base coupled through a second diode to the first bit line. The collectors of both of the bipolar transistors are coupled to provide an output signal. Resistors are coupled to a pulse source and to both of the bases of the bipolar transistors. A current sink is coupled to both of the select bit lines. The diode means are connected so as to be forward biased when the base-emitter junction of the transistor to which the diode means is coupled is also forward biased.

Abstract: Logic gates with large logic swings and large noise margins use complementary pull-up and pull-down enhancement-mode drivers. Connected between the input node of the logic gate and the control electrode of each of the drivers is a series combination of a level shifter (or constant-voltage element) and a current regulator (or constant-current element). The level shifter permits a voltage drop approximately independent of current, while the current regulator limits current flowing between the input node and the control electrode approximately independent of voltage.

Abstract: A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by .alpha. rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line.

Abstract: A bipolar random access memory having no write recovery time. During a data write operation, while the memory state of the memory cell is being shifted, a data bypass circuit sets a sense latch in the sense amplifier to store the new state to which the memory cell is being set. To prevent the sense latch from being shifted by transient write recovery currents charging bit line parasitic capacitances following the data write operation, a read/write transmission circuit isolates the sense amplifier from the bit lines, diverts current from the sense amplifier to a source of high voltage to charge the parasitic capacitances, and then realigns the sense amplifier to the bit lines.

Abstract: This invention relates generally to Static Random Access Memory (SRAM) cells and more particularly, relates to a SRAM cell wherein soft-error due to .alpha.-particle radiation is reduced by permitting the potential at the common-emitter node of the cross-coupled transistors of the memory cell to swing freely. Still more particularly, it relates to a SRAM cell wherein the common-emitter node of the cell is decoupled from a heavily capacitively loaded word line with its common constant current source by means of a constant current source or current mirror disposed in each cell between the common-emitter node and the word line.

Abstract: A semiconductor memory includes a memory cell (42) which utilizes a cross-coupled bipolar SCR latch. The latch includes two sense nodes (78) and (80). Sense node (78) has associated therewith an NPN transistor (82) and a PNP load transistor (84). Similarly, sense node (80) has associated therewith an NPN transistor (90) and a PNP load transistor (92) configured as an SCR. Each of these sense nodes is cross-coupled to the base of the NPN transistor connected to the opposite sense node. A forward biased PN junction is connected between an external Write circuit and the collector of each of the NPN transistors to provide an independent current path when changing from a low logic state to a high logic state. This decreases the recovery time when going from a saturated to a cut-off state for the NPN transistor.

Abstract: A bipolar RAM having improved read and write cycle times. During a write operation, the state of a selected memory cell is sensed by read/write current controller circuits. A high write current is selected if the data to be written requires a shift of the memory state of the memory cell, and a low write current is selected if the data to be written corresponds to the present memory state of the memory cell. This improves the write cycle time by reducing saturation of the memory cell. If a long write signal is impressed on the RAM, the read/write current controller circuit terminates the high level write current after the memory cell has shifted its memory state. When a memory cell is being selected for a read or write operation, the write current select circuit discharges the bit line attached to the low voltage side of the selected memory cell, improving the read cycle time.

Abstract: A transistor memory cell device comprising a pair of cross-coupled transistors constituting storage elements for storing binary information and having column drive emitter inputs to which a relatively high column drive current is applied for the selective read or write operation of storage elements of the cell device. A constant current source provides a relatively low value hold current to maintain the binary digit information stored in the storage elements in the absence of column drive current. A voltage clamping dual emitter transistor has the emitters thereof connected directly to the respective base-collector interconnections of the cross-coupled transistors, with the base of the clamping transistor having applied to it an offset voltage higher than a voltage applied to a non select line connected to the collector circuits of the cross-coupled transistors.

Abstract: A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the memory cell is formed under a digit line. This memory device is greatly reduced in its required area, and the Schottky barrier diode and capacitor are negligibly influenced by the digit line. In other embodiments, it is arranged to provide different electrodes for the Schottky barrier diode and the capacitor to optimize construction in a minimized space.

Abstract: A digital memory characterized by a plurality of memory cells arranged into a matrix having rows and columns; a row activation circuit for concurrently activating all of the rows of the matrix; and column activation means for concurrently applying either a reset signal or a preset signal to the columns of the matrix. The column activation circuit can include a plurality of digital switches coupled to reset and preset lines associated with each column of the matrix; and reset/preset logic which control the digital switches to selectively couple the reset and preset lines to a constant current source. A complementary, multi-emitter flip-flop memory cell is formed on a semiconductor substrate and includes "riser" portions.

Abstract: A semiconductor memory device having a plurality of word line pairs and drain lines, a plurality of bit line pairs, and a plurality of memory cells connected to both of the word line pairs and the bit line pairs at the cross points thereof, comprising: a first and a second word line provided as the word line pair, a memory cell including a first and a second multi-emitter transistor whose commonly connected emitters are connected to the drain line, first and second resistors where one of their ends are connected between the collectors of the first and second multi-emitter transistors respectively, and where their other ends are both connected to the first word line and the bases of the second and first multi-emitter transistors are connected to the other's collectors, respectively, and first and second diodes such as Schottky barrier diodes are connected between the collectors of the first and second multi-emitter transistors and the second word line, respectively.

Abstract: An integrated bipolar memory cell with random access, includes an upper word line, a lower word line, two bit lines, two transistors each having two emitters, a base and a collector fed back crosswise to the base of the other transistor, two Schottky diodes, two low-resistance load resistors each forming a series circuit with a respective one of the Schottky diodes, two high-resistance load resistors each forming a parallel circuit with a respective one of the series circuits, each of the parallel circuits being connected between a respective one of the collectors and the upper word line defining active regions of the memory cell, one of the emitters of each of the transistors being connected to the lower word line, the other of the emitters of each of the transistors being connected to a respective one of the bit lines, and an external capacitance connected between the collectors outside the active regions.

Abstract: Load resistors are connected in series between the PNP portions of the SCRs and the upper word-line. The load presented to the NPN portions of the SCRs is thus a composite formed of a PNP transistor in series with a resistor. The resistor causes a downward shift of voltage due to IR drop on the ON side of the cell and provides a dramatic improvement in writing speed. During a write operation, the IR drop across the resistor on the ON side of the cell collapses as current declines, and the consequent rise in voltage is coupled to the low base line, significantly shortening the time required to raise its voltage sufficiently to securely write the cell.

Abstract: A memory cell includes two active load, pnp transistors, and two npn switching transistors. The collector and base regions of the switching transistors are cross coupled. Each of the load transistors have two collectors, with the base of each load transistor directly connected to only one of its two collectors. The additional collector prevents the switching transistors from heavily saturating and thus increases the speed of operation of the cell.

Abstract: An improved memory cell circuit in which the collector of the "ON" transistor is clamped to a variable voltage level to prevent saturation. Saturation is prevented by providing a mechanism for limiting the voltage between a first node in the word line circuit and the collector of the conducting transistor to a first level, while limiting the voltage between the first node and the collector of the nonconducting transistor to a second, lower level.In one embodiment, clamping transistors have their emitters coupled to the collectors of the memory cell transistors and their bases coupled to the word line. A common resistor couples the load resistors of a plurality of memory cells to the word line.In a second embodiment, the common resistor couples the bases of the clamping transistors to an intermediate node in a Darlington driver for the word line.

Abstract: A circuit reduces the row select voltage swing in a memory array, thereby reducing access time, power dissipation, disturb problems, glitches on the output, and alpha particle sensitivity. A row driver transistor is coupled between a first voltage source and the word line of a row of memory cells and has a base coupled to a row decode signal. A clamp circuit coupled to the base clamps a voltage on the base in accordance with a current provided by a current mirror coupled thereto. A write enable circuit is differentially connected to the current mirror and the clamp circuit for enabling the clamp circuit during a read mode for limiting the voltage swing on the word line.

Abstract: In a semiconductor memory cell having PNPN type memory cells, a vertical PNPN element is used as a load transistor and a sense transistor or a hold transistor, or both. A buried layer is used as a wiring layer for a word line or a bit line, so that the switching speed can be increased and the memory cell area can be decreased.

Abstract: Semiconductor integrated word organized store comprising a two-dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled merged transistor logic (MTL) gates having a structure providing a vertical inverting base transistor and two complementary lateral injector transistors. A cell is driven by read/write logic pulses applied to the word lines and bit lines only. To read the contents of a word from the array, read logic drives the read injectors of the cells constituting the word at a high injector current level and the read injectors of all other cells at a low injector current level. To select a word for writing, the read logic drives the read injectors of the cells comprising the word at a low injector current level and all other cells at a high injector current level. The contents of the selected word may then be changed by differentially driving the cell write injectors over the bit lines.

Abstract: A circuit for reading bipolar storage cells includes a storage element formed of two fed-back inverters, each of the inverters being formed of a multi-emitter transistor and a load element connected to a respective one of the multi-emitter transistors, two complementary bit-lines each being connected to one emitter of a respective one of the multi-emitter transistors, a first potential source, two bit-line current sources each being connected between the first potential source and a respective one of the complimentary bit-lines, a differential amplifier having two inputs, two read transistors each having a collector-emitter path connected between a respective one of the inputs of the differential amplifier and a respective one of the complimentary bit-lines, a second potential source, a read-current source connected to the second potential source, and two diode paths each connected between the read-current source and a respective one of the complimentary bit-lines.

Abstract: To extend the function of a bipolar type RAM, a register function is added to the RAM function. The register function is such that the contents stored in a memory cell is inputted to a differential switch, and the output to the differential switch is derived out to constantly read out the stored content of a desired bit with a simple circuit construction.

Abstract: A semiconductor memory device used as a bipolar random access memory including a plurality of pairs of word lines, a plurality of pairs of bit lines, and a plurality of static memory cells located at the intersections of and connected between the pairs of word and bit lines. A plurality of constant current sources are selectively connected to the bit lines. A reading-writing voltage control circuit controls the potential of each bit line during the reading and writing of data and a writing current control circuit controls the current flowing to each bit line during the writing of data into the memory cell. Further, the writing current control circuit connects the constant current source to the reading-writing voltage control circuit in the writing of data to the memory cell. Accordingly, the bipolar random access memory can operate at a high speed with reduced power consumption and without unnecessary current flowing in the peripheral circuits.

Abstract: A semiconductor memory comprising at least memory cells, word lines (W.sub.+, W.sub.-), bit lines (BL, BL) and word line discharge circuits to be co-operated together with a word line discharge current controller. The word line discharge current controller is operative to gradually reduce a word line discharge current absorbed from the word line W.sub.- to the word line discharge circuit together with a gradual attenuation of an inverse current from the bit line to the corresponding memory cell.

Abstract: Disclosed is a memory cell circuit for a gate array. The memory cell circuit is D.C. testable and has particular utility when employed in an integrated circuit containing "a mix of logic and array".Also disclosed is a memory array particularly adapted for use in an integrated circuit containing TTL logic circuits.

Abstract: A semiconductor memory circuit including a charge absorbing circuit. The charge absorbing circuit absorbs at least a current induced by a voltage increase in the word line occurring soon after the word line is switched from a selection state to a nonselection state.

Abstract: A fall-through memory array comprising in a plurality of rows and columns a plurality of memory cells, each memory cell comprising a pair of cross-coupled transistors having three emitters, a collector and a base. Control potentials applied to a word line, coupled to each one of two of the emitters of each of the transistors, control the transfer of data bits from one row of such memory cells to another.

Abstract: A memory circuit is provided wherein the speed of the downward transition of the memory cell is increased. A plurality of memory cells are coupled between a select line and a current drain line. A first means is coupled to the select line for providing current to the plurality of memory cells and is responsive to a select signal having first and second states. A first PNP transistor has an emitter coupled to the current drain line for drawing any charge from the plurality of memory cells when the select signal transitions downward. A second means is coupled to the base of the first PNP transistor and is responsive to the select signal for setting the current level in said first PNP transistor. A second embodiment additionally includes a second PNP transistor having an emitter coupled to the select line and a collector coupled to said second supply voltage terminal for removing charge stored on the select line.

Abstract: A semiconductor memory includes a dynamic discharge circuit for the quick discharging of a power supply line to which a memory matrix row is connected when this power supply line changes over from the electrical selected state to the electrical rest state. A transistor which is rendered conductive by a dynamic potential difference which arises, due to the slow discharge of the power supply line, between this line and the selection circuit thereof, supplies a current for a brief period of time in order to achieve the quick discharging. The invention is typically used notably for the discharging of power supply lines of E.C.L.-type random access memories.

Abstract: A semiconductor memory device in which a bipolar memory cell includes two cross-coupled transistors. The collector load is a Schottky barrier diode. A capacitor is formed to be connected to the Schottky barrier diode. The capacitor is formed by a junction between a P.sup.+ -type diffusion region and an N.sup.+ -type buried layer functioning as a collector of the transistor. The P.sup.+ -type diffusion region is formed in the periphery of the Schottky barrier diode and between a metal layer connected to a word line and the N.sup.+ -type buried layer. By the capacitor, the stability of the memory holding state is improved without deteriorating the operating speed of the memory cell.

Abstract: The random access memory device of the present invention provides the memory cell array arranged in the form of a matrix. The plurality of memory cells have cross-connected flip-flop circuits. Word driver transistors are provided corresponding to a plurality of word lines, wherein the collector is connected to a high power supply voltage while the emitter is connected to the word line. Moreover, the base of the word driver transistor is connected respectively in common to a selected word line level switching circuit via diodes. The selected word line level switching circuit supplies a current during the write operation to the common connecting point of diodes and forms a current switch together with the diodes. Thus, the voltage of a selected word line is lower than that during the read operation. The present invention provides a random access memory device which has a simplified structure, consumes less current and assures a high speed read operation.

Abstract: A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results in a signal path with reduced series resistance and thus higher signals and a faster read operation obtainable. The density is additionally increased by using in common the primary injectors and the bit line injectors of adjacent cells of the array.

Abstract: A semiconductor memory device included memory cells each including two PNPN cells cross-coupled with each other, the PNPN cells each including a load transistor and a multi-emitter transistor, the multi-emitter transistor comprising a read/write transistor and a data holding transistor. The read/write transistor has means for decreasing the current amplification factor of the read/write transistor when it operates inversely, whereby the operating speed of the device is improved.

Abstract: A monolithic storage array (10) having multiple write ports (12, 14) and multiple read ports (16, 18), which may be used simultaneously in any combination. Each cell of the illustrative array has two storage flip-flops (Q1/Q4 and Q5/Q8), one for connection to each read port, and has a switching network (Q9-Q16) for connecting write-port row and column selection signals to set or reset both flip-flops as desired. Row selection for reading is effected by raising a power supply voltage coupled to the flip-flops, to increase noise immunity, and the device has only four isolated collectors, for high device density in monolithic form.

Abstract: Disclosed is a memory cell circuit including a pair of memory transistors having respective collectors and bases cross-coupled to each other, wherein load means connected to the collector of each one of said memory transistors comprises a parallel circuit of a load resistance and a transistor whose emitter and collector are connected to both ends of the load resistance and whose base is connected to the collector of the other of the memory transistors, thereby causing the readout currents of the memory cell circuit to be greater irrespective of increased load resistances.

Abstract: A semiconductor memory includes memory cells each respectively provided with a flip-flop circuit in which a pair of transistors is included, the flip-flop circuit being connected to a pair of bit lines and to a pair of word lines. The semiconductor memory further includes a pair of switching transistors connected to the pair of bit lines. One of the pair of switching transistors is turned ON while the other is turned OFF when they receive high and low potentials according to write data at the time of a write operation so as to flow write current from a memory cell to a voltage source via one of the pair of bit lines and one of the pair of switching transistors.

Abstract: A semiconductor device, such as a bipolar semiconductor memory device, includes an internal circuit and a reference signal generating circuit. The difference in potential between at least one internal signal produced by the internal circuit and a reference signal, which is called a noise margin, is decreased during a test mode, rather than during a usual or normal mode, so that the device artificially obtains a high temperature state at room temperature.