Abstract: In a differential read amplifier of a bipolar memory module for the evaluation of a difference of read currents in a first and second bit line, an additional current generated by the read amplifier is fed into the bit line conducting the higher read current. As a result, a time period is reduced in which high interference susceptibility exists during successive read accesses to different memory cells with the same information content. Thus, read accesses can proceed in shorter time intervals.

Abstract: An integrated injection logic (I.sup.2 L) memory where sink currents flowing into non-selected memory cells are supplied from clamp circuits, not from the selected memory cell. In addition, the potential of the selected bit line through which a write current flows is decreased by the clamp circuits.

Abstract: A decoder circuit comprises input gates, a logic circuit for generating an output according to input signals, an output gate for driving a word line, and a current control device for activating the output gate according to the output of the logic circuit.

Abstract: Circuitry for presetting a bipolar random access memory includes switching transistors, responsive to an applied memory preset signal, for opening the circuit between the memory word lines and their respective current sources, for applying a positive voltage to the bottom word lines, for breaking the circuitry between bit line clamping circuits and their respective power sources, and for grounding the bit line pairs to drain all current from the bit line circuits. The preset circuitry also includes read/write control transistors coupled between each bit line and a V.sub.cc source for steering the set of the memory cells upon removal of the preset signal.

Abstract: A semiconductor memory device including memory cells, formed by a pair of multi-emitter transistors each having a collector and a base which are cross connected to each other and arranged in row and column directions, and read-out transistors, each having an emitter which is commonly connected to one of the emitters of the multi-emitter transistors, wherein the read-out transistors are arranged in each column. The multi-emitter transistors and the read out transistors are formed in patterns and the characteristics of both the multi-emitter and read-out transistors have the same variation due to a dispersion of the patterns caused by the manufacturing process.

Abstract: An I.sup.2 L type semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor body of the device, wherein an injector region is formed under said insulating layer and surrounded by thicker portions of said insulating layer, and base regions are formed under said insulating layer between said thicker portions of said insulating layer and said V-shape grooves.

Abstract: A termination circuit for word lines of a static semiconductor memory device comprising, for each word line, a first transistor which detects a potential change on the word line, a delay circuit which delays an output signal from the first transistor by a predetermined time period and a second transistor which is turned on and off by an output signal from the delay circuit. Each of the second transistors is connected between one of the hold lines and a common hold current source, so that the second transistors and the common hold current source forming a current switch.

Abstract: A semiconductor memory circuit, comprising memory cells; word lines, hold lines and bit lines connected to respective memory cells; and a hold-current controlling circuit. The hold-current controlling circuit comprises identical controlling circuit elements connected to respective hold lines and a constant-current source commonly connected to the controlling circuit elements. Each of the controlling circuit elements comprises means for absorbing electric charges from respective hold lines, when corresponding word lines change from a selection status to a non-selection status, until the voltage level of the hold line reaches a full "L" or "H" level, and means for blocking a flow of electric charges from the hold line, when a corresponding word line changes from a non-selection status to a selection status, during a predetermined interval after time data switching from one memory cell to another memory cell is performed.

Abstract: A semiconductor memory device is provided which includes a first transistor (TR1) having its emitter grounded, a second transistor (TR2) having its base and collector connected to the collector and base of the first transistor (TR1) and its emitter grounded, a data line (DL), and a third transistor (TR5) having its emitter-to-collector path connected between the data line (DL) and the base of the second transistor (TR2). The semiconductor memory device further includes a fourth transistor (TR6) having its base connected to another collector of the second transistor (TR2) and a fifth transistor (TR7) having its emitter-to-collector path connected between the base of the fourth transistor (TR6) and the row select line. Data is written through the data line (DL) and third transistor (TR5) and stored data is read out of the collector of the fourth transistor according to the conduction state of the second transistor (TR2).

Abstract: In a memory comprising an upper word line and a lower word line for selecting memory cells connected therebetween, a delay circuit connected to the upper word line provides a first signal having a predetermined level when a voltage applied to the upper word line is between a selection voltage and a predetermined voltage, and a second signal, which is a delayed signal of the upper word line voltage signal, when the upper word line voltage changes from the predetermined voltage toward the non-selection voltage. The output of the delay circuit is used to control a switch circuit for discharging the lower word line therethrough.

Abstract: A memory cell for integration into a static memory includes two transistors with cross-coupled base and collector regions. The collector regions are connected to p-n junction diode load elements having at least one region of polycrystalline silicon material. The collector regions of the transistors are connected to the regions of the diodes which are of the same conductivity type as the collector regions.

Abstract: An I.sup.2 L circuit is provided for sensing relatively small differences in magnitude between two input signals. A dual input bistable circuit generates an output representative of the degree to which each of the bistable circuit inputs is actuated, subsequent to the energization of the bistable circuit by a current source in the form of an injector transistor, which is disabled to reset the bistable circuit. A pair of load transistors are provided, the control terminals of which are, respectively, connected to receive the input signals. Each load transistor serves to actuate a different one of the bistable means inputs to a degree dependent upon the conductivity thereof, which, in turn, is dependent upon the magnitude of the input signal connected thereto. The load transistors also serve to isolate the source of the input signals from the energizing injector current, to prevent the sensing circuit from disrupting the state of the source of the input signals.

Abstract: A new and improved write and read control circuit for semiconductor memories is provided that comprises a first pair of transistors having their emitter terminals coupled to a current source, a base terminal of a first of the first pair being disposed for receiving data to be written in the array and a base terminal of a second of the first pair being coupled to a first reference potential, and each of the first pair of transistors having collector terminals; a second pair of transistors having their collector terminals coupled to a second reference potential, the base terminal of a first of the second pair being coupled to the collector terminal of the first of the first pair of transistors and the base terminal of a second of the second pair being coupled to the collector terminal of a second of the first pair, the emitter terminal of the first of the second pair being coupled to a second current source and forming a first output of the circuit, and the emitter terminal of the second of the second pair bein

Abstract: A semiconductor device includes a bipolar transistor having at least two emitter zones. One of the emitter zones is divided into two separate sub-zones, which are separated by a conductive channel which connects the base zone to an adjoining resistive zone. Two substantially identical transistors of the type disclosed may be interconnected in a cross-coupled arrangement to form an ECL memory cell.

Abstract: An integratable semi-conductor memory cell has two bipolar transistors which are identical to one another and which have their collectors connected in series with respective circuit parts having a non-linear current characteristic, the respective circuit parts being connected to a first electrical potential. The circuit parts are also connected to the base of the other respective transistor. One emitter of each of the transistors is provided for control by means of logic signals and the invention is particularly characterized in that the circuit part located between the collector of each one of the transistors and a switching point carrying the first electrical potential are selected in such a fashion that the slope dU/dI of the current-voltage characteristic will always be higher than the slope of the corresponding current values in the current-voltage characteristic of the pn-junctions of the emitter-base circuit of both transistors.

Abstract: An improved semiconductor integrated circuit device having an array of integrated injection logic memory cells arranged in matrix form, with word and bit lines connected to the memory cells arranged in lines. The second word line is formed by a semiconductor bulk, and dummy cells each comprising a shunt circuit for shunting the write current of the memory cells and a hold circuit for supplying a hold current to the memory cells are arranged in each line of the memory array.

Abstract: A unique topography of I.sup.2 L bipolar semiconductor elements provides Read-Write Random Access Memory (RAM) with very high packing density, low cost, and good power and speed characteristics and with a very simple metallization pattern.

Abstract: A master-slave flip-flop, wherein a master latch circuit and a slave latch circuit each include only one pair of single-emitter bipolar transistors and one pair of dual-emitter bipolar emitter-follower transistors, is disclosed. In each circuit the first emitters of the dual-emitter transistors are cross-coupled to the bases of the single emitter transistors, and the bases of the dual-emitter transistors are coupled to the collectors of the single-emitter transistors. In the master latch circuit the bases of the single-emitter transistors are respectively coupled to complementary data input terminals. The bases of the single-emitter transistors in the slave latch circuit are coupled to the second emitters of the dual-emitter transistors of the master latch circuit. The second emitters of the dual-emitter transistors of the slave latch circuit are coupled to complementary output terminals.

Abstract: A register building block is disclosed comprising binary memory cells of cross-coupled double emitter transistors which are fed from a source of constant current and addressed by raising the collector potential. Given a predetermined operating voltage, two memory cells are connected in series to save dissipation loss in each constant current circuit. A switch controlled by one bit of the address is used to select one memory cell from the addressed pair of memory cells. The circuit arrangement disclosed is utilized in highly integrated building blocks.

Abstract: A memory system of an array of memory elements arranged in an electrical matrix of rows and columns. Each memory element comprises a bistable circuit of two bipolar transistors. Holding current flows through the on transistor of each memory element of a row from a common current source to a common line. When a memory element is switched so that is transistors reverse operating conditions, the holding current flow through the memory element is diverted during the transition. A clamping arrangement of a transistor and associated resistance is connected between the common current source and the common line of each row. When all of the memory elements of a row are switched at the same time the clamping arrangement provides an alternative controlled current path for the diverted holding currents.

Abstract: A semiconductor integrated circuit comprises a pair of load transistors and a pair of inverter transistors to constitute a flip-flop circuit. The load transistors are formed of p-channel field effect transistors serving as carrier injectors for the inverters formed of npn bipolar transistors. The p-type drain region of each load transistor is merged into the p-type base region of each inverter transistor. The absence of carrier storage effect in the field effect transistors improves the operation speed of the flip-flop remarkably and the high impedance gate electrode can be utilized as the clocking electrode to achieve clocking with voltage pulses without substantial power consumption. A plurality of such flip-flops are connected in cascode one after another to constitute a shift register.

Abstract: A memory cell having input and output buffering. Input buffering is provided by connecting the injector input of an integrated injection logic (I.sup.2 L) gate to the data input line of the memory cell and by connecting the injector input of the input gates of the memory cell to the write enable line. In order to enter data into the memory cell, the input gates must be energized via the injector input. Output buffering is provided by placing another integrated injection logic gate between the memory cell output and the data output line. The injector input of the another gate is connected to a read select line thereby permitting information contained within the memory cell to be read out to the data output line whenever the read select line connected to the injector input is enabled.

Abstract: A sense-write circuit for use with a emitter coupled logic memory array is provided. A first differential stage includes a pair of emitter-coupled transistors connected to a current source controlled by a chip select voltage. A first one of the emitter-coupled transistors has its base connected to a first reference voltage and the second one of said transistors has its base coupled to a write enable input. The collector of a first one of the emitter-coupled transistors serves as a current source for a second differential stage including a second pair of emitter-coupled transistors, a first one having its base connected to a second reference voltage and the second having its base coupled to a data input conductor. The two respective outputs of the second differential stage are coupled to emitter follower drivers, and are also independently coupled through a pair of respective diode-connected transistors to the collector of the first transistor of the first emitter coupled pair.

Abstract: An active storage or memory cell includes first and second high input impedance inverters cross coupled to form a flip-flop. The output impedance of the second inverter is significantly lower than the output impedance of the first inverter. Input signals are applied at, and information is read out from, a single input-output point common to the output of the second inverter and the input of the first inverter via a gating means connected between said input-output point and an input-output line which is turned on more slowly than it is turned off.