Abstract: A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor, a first transmission gate switch coupled between the first input node and the second input node, a second transmission gate switch coupled between a first common node of the first and second inverters and a second common node of the first and second inverters. The sense amplifier is maintained at a maximum gain point in a read cycle.

Abstract: Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.

Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.

Abstract: A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a feedback loop coming from storage node QB. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” are carried out differently. Contrary to standard SRAM cells, in the hold states, only the QB storage node presents a valid value of stored data. The feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch. By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states are eliminated altogether.

Abstract: A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

Abstract: A sense amplifier includes a first inverter responsive to a first output of a latch. The first inverter is powered by a sense enable signal. The sense amplifier also includes a second inverter responsive to a second output of the latch. The second inverter is also powered by the sense enable signal.

Abstract: A complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array. Modern sub-micron CMOS structures have been observed to have reduced vulnerability to latchup. Chip area is reduced by providing no well contacts within the array. Wells of either or both conductivity types may electrically float during operation of the memory. In other implementations, extensions of the array wells into peripheral circuitry may be provided, with well contacts provided in those extended portions.

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

Abstract: A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.

Abstract: In a loadless 4T-SRAM constituted using vertical-type transistor SGTs, a small SRAM cell area is realized. In a static memory cell constituted using four MOS transistors, the MOS transistors are SGTs formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction. The gates of access transistors are shared, as a word line, among a plurality of cells adjacent to one another in the horizontal direction. One contact for the word line is formed for each group of cells, thereby realizing a CMOS-type loadless 4T-SRAM with a very small memory cell area.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract: Example embodiments relate to an SRAM device and a method of manufacturing the same. The SRAM device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction. In example embodiments, the second transistors may be vertically connected to the first transistors. In example embodiments, the second transistors may be vertical transistors that include vertical gates surrounding vertical channels.

Abstract: A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other.

Abstract: A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries. A CVss line carrying a VSS power supply voltage crosses the first long boundary and the second long boundary. The CVss line is parallel to the second direction. A bit-line and a bit-line bar are on opposite sides of the CVss line. The bit-line and the bit-line bar are configured to carry complementary bit-line signals.

Abstract: A memory circuit properly workable under low working voltage includes a plurality of write word lines, a plurality of write bit lines, a plurality of read/write word lines, a plurality of read/write bit lines, a plurality of read/write inverted word lines, a plurality of virtual voltage source circuits, a plurality of virtual ground circuits, and a plurality of asymmetrical RAM cells constituting a cell array. The asymmetrical RAM cells are formed of seven transistors, five of which are NMOS transistors and two of which are PMOS transistors. The virtual voltage power source circuit and the virtual ground circuit can reinforce the write-in and read abilities under low working voltage to make the write-in and read actions more stable, decrease leakage current, and lower power consumption.

Abstract: An electronic device comprises a semiconductor memory cell having a bistable bit storage circuit having first and second power contact points. A first switch is coupled to the first power contact point to receive a first voltage. A second switch coupled to the second power contact point to receive a second voltage. Circuitry is provided for turning off the first and second switches to decouple the respective first and second voltages from the respective first and second power contact points, during stand-by operation of the electronic device.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: An SRAM cell and a method of forming an SRAM cell. The SRAM cell includes a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; a first gate electrode common to the first pull-down FET and the first pull-up FET and physically and electrically contacting the first S/D of the first pull-up FET; a second gate electrode of the first pull-up FET; a third gate electrode common to the second pull-down FET and the second pull-up FET and physically and electrically contacting the first S/D of the second pull-up FET; and a fourth gate electrode of the first pull-up FET.

Abstract: A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM.

Abstract: Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.

Abstract: A method for writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell. The method may include adjusting a bias level of the n-wells that contain the bit driver, bit-bar driver, bit passgate, and optional bit-bar passgate.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: In at least one embodiment, a sense amplifier circuit includes a pair of bit lines, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the pair of bit lines and includes an NMOS transistor coupled between a power node and a corresponding one of the pair of bit lines. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the corresponding bit line and configured to maintain a voltage level of the corresponding bit line. The noise threshold control circuit is connected to the sense amplifier output and the pair of bit lines. The noise threshold control circuit comprises a half-Schmitt trigger circuit or a Schmitt trigger circuit.

Abstract: Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract: A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.

Abstract: Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.

Abstract: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12.

Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.

Abstract: A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.

Abstract: An embodiment of the invention provides a method for decreasing power in a static random access memory (SRAM). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle. A second voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are not column addressed during a read cycle. Because the second voltage is less than the first voltage, power in the SRAM is reduced. In this embodiment, a memory cell in the SRAM includes at least one read buffer and a latch connected between the latch sourcing and latch sinking supply lines.

Abstract: A static random access memory (SRAM) is provided for establishing an initialization state. The SRAM connects to a plurality of signal lines including a bit line and an inverse bit line. The SRAM includes first and second inverters, a voltage potential and a ground. The first inverter includes a first n-type metal oxide semiconductor (MOS) transistor having a first n-type threshold voltage and a first p-type MOS transistor having a first p-type threshold voltage. The second inverter includes a second n-type MOS transistor having a second n-type threshold voltage and a second p-type MOS transistor having a second p-type threshold voltage. The first transistors connect respectively first n-type and first p-type drains together at a first junction that connects to the bit line. The second transistors connect respectively a second n-type and second p-type drains together at a second junction that connects to the inverse bit line.

Abstract: A method and circuit for implementing low power write disabled local evaluation for Static Random Access Memory (SRAM), and a design structure on which the subject circuit resides are provided. The circuit includes a write disable function to prevent discharge of a global bit line during a write operation. The write disable function disables a NAND gate driving a global pull down device during the write operation preventing the global pull down device from discharging the global bit line.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell provided with a pair of storage nodes which store data in a complementary manner, a pair of bit lines that are driven in a complementary manner based on data written to the memory cell, a word line that selects a row of the memory cell, and a word line potential fixing circuit that fixes a potential of the word line so that the row of the memory cell is not selected when a power supply of the memory cell rises.

Abstract: An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.

Abstract: An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.

Abstract: An integrated circuit including a ram array with SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.

Abstract: A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode.

Abstract: A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column.

Abstract: A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA.

Abstract: A sense amplifier for a static random access memory (SRAM) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an SRAM cell. A second pass gate transistor is driven by a bit line complement associated with the SRAM cell. A first pull down transistor is coupled to the first pass gate transistor and a second pull down transistor is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pull down transistor with the first pass gate transistor. A data line complement is coupled to a node coupling the second pull down transistor with the second pass gate transistor.

Abstract: An object of the current invention is to provide DRAM that is not limited by capacitors.

Abstract: A five transistor static random-access-memory (SRAM) cell is disclosed which can be made part of an SRAM array to provide an improved reduction in size. The cell includes two cross-coupled inverters, each having two complementary transistors, and an n-channel transistor switch connected to a bit line (BL) and a word line (WL). The p-channel element of one of the inverters is connected to a power supply, and the p-channel transistor of the other inverter is coupled to a write bit line (WBL). By varying the voltage levels on the BL and WBL lines the biasing of the individual n-channel transistors of each of the inverters can be changed based on the data to be written to the cell. Various biasing systems are presented such that the SRAM cell memory state can be changed without requiring larger transistor elements to overpower the cell state.

Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.