Abstract: Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a first heavy metal layer and a first magnetic tunnel junctions (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area that is different than the first area. The second MTJ shared a reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer that is coupled to the second MTJ.

Abstract: A SOT-MRAM cell, comprising at least one magnetic tunnel junction (MTJ) comprising a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; a SOT line, extending substantially parallel to the plane of the layers and contacting a first end of said at least one MTJ; at least a first source line connected to one end of the SOT line; at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ, each bit line being connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and second bit line.

Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.

Abstract: Methods and systems for locating a filament in a resistive memory device are described. In an example, a device can acquire an image indicating an occurrence of photoemission from the resistive memory device. The device can determine a location of the filament in a switching medium of the resistive memory device using the acquired image.

Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

Abstract: A modified double magnetic tunnel junction structure is provided which includes an amorphous spin diffusion layer (i.e., an amorphous non-magnetic, spin-conducting metallic layer) sandwiched between a magnetic free layer and a first tunnel barrier layer; the first tunnel barrier layer contacts a first magnetic reference layer. A second tunnel barrier layer is located on the magnetic free layer and a second magnetic reference layer is located on the second tunnel barrier layer. Such a modified double magnetic tunnel junction structure exhibits efficient switching (at a low current) and speedy readout (high tunnel magnetoresistance).

Abstract: A magnetic sensing device includes a non-magnetic layer serving as a spacer and two magnetic layers that sandwich the spacer, and two oxide layers that sandwich the trilayer structure including the two magnetic layers and the spacer.

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

Abstract: According to one embodiment, a magnetoresistive memory device includes: a first conductor; a layer stack; an insulator on a side surface of the layer stack; a second conductor on a second surface of the layer stack; a third conductor; and a fourth conductor on the third conductor. The layer stack includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer and has a first surface in contact with the first conductor. The second surface is at an opposite side of the first surface. The third conductor has a portion on the second conductor and a portion on a side surface of the insulator.

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a sense amplifier circuit for current sensing in a memory structure and methods of manufacture and operation. In particular, the present disclosure relates to a circuit including: a sensing circuit including a first set of transistors, at least one data cell circuit, and a reference cell circuit; a reference voltage holding circuit comprising a second set of transistors and a bitline capacitor; and a comparator differential circuit which receives a data sensing voltage signal from the sensing circuit and a reference voltage level from the reference voltage holding circuit and outputs an output signal.

Abstract: Provided is a magnetic storage element including a stack structure which includes a fixed layer whose magnetization direction is fixed, a storage layer whose magnetization direction is reversible, and a non-magnetic layer sandwiched between the fixed layer and the storage layer. The magnetization direction has a direction along a stack direction of the stack structure, and the fixed layer or the storage layer has a region which contains at least one contained element selected from the element group consisting of B, C, N, Al, Mg, and Si at 30 atm % or more and 80 atm % or less.

Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

Abstract: A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.

Abstract: The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.

Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

Abstract: A multiply and accumulate calculation device includes a multiple calculation unit and a accumulate calculation unit. The multiple calculation unit includes a plurality of multiple calculation elements, which are variable resistance elements, and at least one reference element. The accumulate calculation unit includes an output detector configured to detect a total value of at least outputs from the plurality of multiple calculation elements. Each of the plurality of multiple calculation elements is a magnetoresistance effect element including a magnetized free layer having a magnetic domain wall, a magnetization fixed layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetized free layer and the magnetized fixed layer. The reference element is a reference magnetoresistance effect element having a magnetization free layer that does not have the magnetic domain wall.

Abstract: A circuit for reducing read disturbance error in a tag array. The circuit includes a decoder, a plurality of m-bit comparators, and a plurality of n-bit comparators. The decoder is configured to enable access to a respective set of the tag array based on a value of an index of a requested address. Each respective m-bit comparator is configured to enable access to a respective plurality of Most Significant Bits (MSBs) of the respective set responsive to each respective Least Significant Bit (LSB) of a respective plurality of LSBs of the respective set being equal to a respective LSB of a tag of the requested address. Each respective n-bit comparator is configured to enable access to the respective set by a data bus responsive to each respective MSB of the respective plurality of MSBs being equal to a respective MSB of the tag.

Abstract: A stacked structure is positioned on a nonmagnetic metal layer. The stacked structure includes a ferromagnetic layer and an intermediate layer interposed between the nonmagnetic metal layer and the ferromagnetic layer. The intermediate layer includes a NiAlX alloy layer represented by Formula (1): Ni?1Al?2X?3 . . . (1), [X indicates one or more elements selected from the group consisting of Si, Sc, Ti, Cr, Mn, Fe, Co, Cu, Zr, Nb, and Ta, and satisfies an expression of 0<?<0.5 in a case of ?=?3/(?1+?2+?3)].

Abstract: An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.

Abstract: A memory system includes: a first memory subsystem suitable for storing a first segment of map data for first logical addresses in a logical address region; a second memory subsystem suitable for storing a second segment of map data for second logical addresses in the logical address region; and a host interface suitable for: providing any one of the first and second memory subsystems with a first read command of a host according to a logical address included in the read command, providing the host with an activation recommendation according to a read count of the logical address region including the provided logical address, providing map data for the first and second logical addresses obtained from the first and second memory subsystems, wherein the activation recommendation allows the host to further provide a physical address corresponding to a target logical address in the logical address region.

Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.

Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.

Abstract: A device is disclosed. The device includes a first memory cell, a second memory cell, a first pair of a driver and a sinker, and a second pair of a driver and a sinker. The first memory cell is coupled between the first pair of the driver and the sinker through a first line and a second line. The second memory cell is coupled between the second pair of the driver and the sinker through a third line and a fourth line. The first pair of the driver and the sinker are configured to be controlled to have resistances depending on a row location of the first memory cell in a memory column.

Abstract: A cell trace circuit includes a memory cell, a voltage generator and a measuring circuit. The memory cell has a resistor and a memory layer coupled in series to have a top electrode, a middle electrode and a bottom electrode, wherein the resistor and the memory layer are coupled at the middle electrode. The voltage generator provides a test bias to the memory cell ranging from a negative voltage to a positive voltage in a reset path or ranging from the positive voltage to the negative voltage in a set path. The measuring circuit is to determine a current (I) and a voltage (V) crossing the memory layer by the test bias.

Abstract: A magnetic memory according to an embodiment includes: a magnetic member including a first to third magnetic parts, the first magnetic part including a first portion and a second portion and extending in a first direction from the first portion to the second portion, the second magnetic part extending in a second direction that crosses the first direction, and the third magnetic part connecting the second magnetic part and the first portion; a first nonmagnetic metal layer arranged along the third magnetic part, the first nonmagnetic metal layer including a first end portion on a side of the second portion, a position of the first end portion along the first direction being between positions of the first and second portions along the first direction; and a first and second electrodes supplying a current between the first and second magnetic parts via the third magnetic part.

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

Abstract: An apparatus is provided which comprises: a magnetic junction (e.g., a magnetic tunneling junction or spin valve). The apparatus further includes a structure (e.g., an interconnect) comprising spin orbit material, the structure adjacent to the magnetic junction; first and second transistors. The first transistor is coupled to a bit-line and a first word-line, wherein the first transistor is adjacent to the magnetic junction. The second transistor is coupled to a first select-line and a second word-line, wherein the second transistor is adjacent to the structure, wherein the interconnect is coupled to a second select-line, and wherein the magnetic junction is between the first and second transistors.

Abstract: An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

Abstract: A semiconductor memory device includes a substrate; a first impurity region of a first conductive type; a second impurity region of the first conductivity type apart from the first impurity region in a first direction; a first transistor including a first electrode disposed between the first impurity region and the second impurity region; a third impurity region of the first conductive type apart from the first impurity region in a second direction that crosses the first direction; a fourth impurity region of the first conductive type apart from the third impurity region in the first direction; a second transistor including a second electrode disposed between the third impurity region and the fourth impurity region. The semiconductor memory device includes an active region of the first conductive type between the first transistor and the second transistor.

Abstract: The disclosed non-volatile memory cell comprises a storage layer of an electrically insulating polarisable material in which data is recordable as a direction of electric polarisation, preferably of ferroelectric material, arranged between a magnetically frustrated layer, preferably of Mn-based antiperovskite piezomagnetic material and a conduction electrode. The magnetically frustrated layer has a different change in density of states relative to the conduction electrode in response to a change in electric polarisation of the storage layer, such that an electron or spin tunnelling resistance across the storage layer is dependent on the direction of electric polarisation.

Abstract: A non-volatile memory device includes a data generation circuit and a reconfiguration processing circuit. The data generation circuit generates: third response data that is different from the first response data (PUF registration mode), when the reconfiguration writing is executed by the reconfiguration processing circuit and the first type of challenge data is obtained again after the reconfiguration writing is executed, after the first response data is generated; and fourth response data that is identical to the second response data (permanent PUF registration mode), when the reconfiguration writing is executed by the reconfiguration processing circuit and the second type of challenge data is obtained again after the reconfiguration writing is executed, after the second response data is generated.

Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

Abstract: An apparatus is provided that includes an array including m rows and n columns of nodes. Each column of nodes is coupled to one of n first conductive lines, and each row of nodes is coupled to one of m second conductive lines. Each node of the m rows and n columns of nodes includes a spin orbit torque-based spin torque oscillator circuit configured to oscillate at a corresponding intrinsic frequency. The spin orbit torque-based spin torque oscillator circuits are configured to generate m output signals at the m second conductive lines upon application of n input signals to corresponding n first conductive lines. The n input signals correspond to an n-element input vector, and each input signal includes a corresponding input signal frequency. Each of the m output signals include frequency domain components at the input signal frequencies.

Abstract: A memory unit with an asymmetric group-modulated input scheme and a current-to-voltage signal stacking scheme for a plurality of non-volatile computing-in-memory applications is configured to compute a plurality of multi-bit input signals and a plurality of weights. A controller splits the multi-bit input signals into a plurality of input sub-groups and generates a plurality of switching signals according to the input sub-groups, and the input sub-groups are sequentially inputted to the word lines. The current-to-voltage signal stacking converter converts the bit-line current from a plurality of non-volatile memory cells into a plurality of converted voltages according to the input sub-groups and the switching signals, and the current-to-voltage signal stacking converter stacks the converted voltages to form an output voltage. The output voltage is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals multiplied by the weights.

Abstract: A magnetic double tunnel junction (MDTJ) (which, preferably, has a large aspect ratio, wherein length L of the MDTJ>>width w of the MDTJ) has magnetic domain wall(s) or DW(s) in the free layer of the MDTJ, wherein controlled movement of the DW(s) across the free layer is effected in response to the polarity, magnitude, and duration of a voltage pulse across the MDTJ. The motion and relative position of DW(s) causes the conductance of the MDTJ (that is measured across the MDTJ) to change in a symmetric and linear fashion. By reversing the polarity of the bias voltage, the creation and/or direction of the DW(s) motion can be reversed, thereby allowing for a bi-directional response to the input pulse.

Abstract: This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.

Abstract: A device includes a programmable ROM circuit, an address circuit, and a processor. The programmable ROM circuit includes multiple physically contiguous pairs of bit-cells, each pair of bit-cells includes an active layer trace extending continuously across both of the bit-cells, each pair of bit-cells comprises a shared contact layer point when the pair of bit-cells is programmed to a value of one and no shared contact layer point when the pair of bit-cells is programmed to a value of zero. The address circuit is coupled to the programmable ROM circuit and configured to address only a first bit-cell of each pair of bit-cells. The processor is coupled to the address circuit and the programmable ROM circuit and configured to use the address circuit to read data from one or more pairs of bit-cells of the programmable ROM circuit.

Abstract: A spin current magnetization rotational element according to the present disclosure includes a first ferromagnetic metal layer configured for a direction of magnetization to be changed and a spin-orbit torque wiring extending in a direction intersecting a lamination direction of the first ferromagnetic metal layer and bonded to the first ferromagnetic metal layer. The spin-orbit torque wiring includes a narrow portion, and at least a part of the narrow portion constitutes a junction to the first ferromagnetic metal layer.

Abstract: An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.

Abstract: A synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; an output line, and a cell for generating the output signal. The cell includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor is electrically coupled to the first output line.

Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; first and second output lines, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor of the first cell is electrically coupled to the first output line and the drain of the upper select transistor of the second cell is electrically coupled to the second output line.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a magnetic layer over the substrate; a magnetic tunnel junction (MTJ) cell over the magnetic layer; and a non-magnetic conductive layer between the magnetic layer and the MTJ cell. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: Disclosed is a magnetic logic device including: a plurality of input branches configured by a magnetic nanowire including a non-magnetic metallic layer, a free layer, and an insulating layer sequentially stacked; an output branch configured by the magnetic nanowire; a coupling portion configured by the magnetic nanowire and where the input branches and the output branch meet; gate electrodes arranged adjacent to the insulating layer in each of the plurality of input branches; and in-plane anisotropic ferromagnetic layers arranged adjacent to the non-magnetic metallic layer in each of the plurality of input branches.

Abstract: A memristor memory device comprises a memristive memory cell, an input terminal, an output terminal, and a gate terminal. The input terminal and the output terminal are directly attached to the memristive memory cell, and the gate terminal is electrically isolated from the memristive memory cell. The gate terminal is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell, by which a correction of non-ideal conductance modulations of the memristor memory device is achieved.

Abstract: An AND or OR logic device has multiple layers of ferromagnetic material separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. The anti-magnetic response in a layer below a layer magnetized with a polarity is summed in a region which is coupled to an output, the output generating at least one of a AND or OR logic function on applied input magnetization.

Abstract: A system including a racetrack memory layer is described. The racetrack memory layer includes a plurality of bit locations and a plurality of domain wall traps. The bit locations are interleaved with the domain wall traps. Each of the bit locations has a first domain wall speed. Each of the domain wall traps has a second domain wall speed. The first domain wall speed is greater than the second domain wall speed. The first domain wall speed and the second domain wall speed are due to at least one of a Dzyaloshinskii-Moriya interaction variation in the racetrack memory layer, a synthetic antiferromagnetic effect variation in the racetrack memory layer, and a separation distance for the plurality of domain wall traps corresponding to an intrinsic travel distance. The separation distance is less than one hundred nanometers.

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.