Negative Resistance Patents (Class 365/159)
  • Patent number: 11502189
    Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 15, 2022
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao, Wei-Chih Kao
  • Patent number: 10593402
    Abstract: A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: March 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-Soo Pyo, Hyuntaek Jung, Taejoong Song, Boyoung Seo
  • Patent number: 10177159
    Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Scott J. Derner
  • Patent number: 10153251
    Abstract: Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Feng Lin, Yuanzhong Wan
  • Patent number: 9842639
    Abstract: Techniques are provided for managing voltages on memory cells in a cross-point array during a read operation. The techniques apply to vertical layer thyristor memory cells and non-thyristor memory cells. Voltages on selected bitlines (e.g., corresponding to memory cells from which data is to be read), are set to a read voltage level. Voltages on unselected bitlines (e.g., corresponding to memory cells from which data is not to be read and which are not to be disturbed) are set to a de-bias voltage level that is different from the read voltage level.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: December 12, 2017
    Assignee: Kilopass Technology, Inc.
    Inventors: Frank Guo, Bruce Bateman
  • Patent number: 9721655
    Abstract: Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 1, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 9659944
    Abstract: A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: May 23, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Qintao Zhang, Mei Xue, Wenwei Yang, Akira Ito
  • Patent number: 9543398
    Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: January 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Matteo Dainese, Franz Hirler, Christian Jaeger, Maximilian Roesch, Wolfgang Roesner, Martin Stiftinger, Robert Strenz
  • Patent number: 9490009
    Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 8, 2016
    Assignee: Rambus Inc.
    Inventors: Deepak Chandra Sekar, Gary Bela Bronner, Frederick A. Ware
  • Patent number: 9230641
    Abstract: A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element and a first terminal of the second resistive memory element, and a transistor comprising a gate electrically coupled with the common node.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: January 5, 2016
    Assignee: Rambus Inc.
    Inventors: Deepak Chandra Sekar, Gary Bela Bronner, Frederick A. Ware
  • Patent number: 9190118
    Abstract: Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas
  • Patent number: 9135164
    Abstract: First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 15, 2015
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Shibabrata Mondal, Swamy Gowda
  • Patent number: 8767438
    Abstract: A memelectronic device may have a first and a second electrode spaced apart by a plurality of materials. A first material may have a memory characteristic exhibited by the first material maintaining a magnitude of an electrically controlled physical property after discontinuing an electrical stimulus on the first material. A second material may have an auxiliary characteristic.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: July 1, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Byungjoon Choi, Minxian Max Zhang, Gilberto Medeiros Ribeiro, R. Stanley Williams
  • Patent number: 8767449
    Abstract: A memory device includes a first conductive layer, a second conductive layer, an in-bit current limiter including a voltage controlled negative differential resistance (VC-NDR) layer in electrical contact with the first conductive layer and a memristor element in electrical contact with the VC-NDR layer and the second conductive layer. A method for programming a memory device that comprises a VC-NDR device is also provided.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 1, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew D. Pickett, Gilberto Medeiros Ribeiro
  • Patent number: 8686386
    Abstract: Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 1, 2014
    Assignees: SanDisk 3D LLC, Kabushiki Kaisha Toshiba
    Inventors: Mihir Tendulkar, Imran Hashim, Yun Wang
  • Patent number: 8679912
    Abstract: A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: March 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sung-Taeg Kang, Gowrishankar L. Chindalore, Brian A. Winstead, Jane A. Yater
  • Patent number: 8652923
    Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 18, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim
  • Publication number: 20140003139
    Abstract: A memory device includes a first conductive layer, a second conductive layer, an in-bit current limiter including a voltage controlled negative differential resistance (VC-NDR) layer in electrical contact with the first conductive layer and a memristor element in electrical contact with the VC-NDR layer and the second conductive layer. A method for programming a memory device that comprises a VC-NDR device is also provided.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Matthew D. Pickett, Gilberto Medeiros Ribeiro
  • Patent number: 8587988
    Abstract: Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching.
    Type: Grant
    Filed: May 8, 2010
    Date of Patent: November 19, 2013
    Assignees: Forschungszentrum Juelich GmbH, Rheinish-Westfaelische Technische Hochschule Aachen (RWTH)
    Inventors: Eike Linn, Carsten Kuegeler, Roland Daniel Rosezin, Rainer Waser
  • Patent number: 8546789
    Abstract: Disclosed herein is a volatile negative differential resistance device using metal nanoparticles, the device includes an organic layer disposed between two metal electrodes, in which the organic layer includes uniformly dispersed metal nanoparticles having a diameter of about 10 nm or less in an organic material. The device of this invention exhibits a volatile negative differential resistance phenomenon at room temperature upon application of a voltage and is thus suitable for use in various switching devices and logic devices, with excellent reproducibility and simple inexpensive processing.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Jae Joo, Kwang Hee Lee, Sang Kyun Lee, Chulhee Kim
  • Patent number: 8514642
    Abstract: A driver circuit having a redundant control function to store address data of a defective memory cell is provided to compensate a defect of a memory cell array. In other words, address data of a defective memory cell is stored not by using part of the memory cell array, but by using a non-volatile memory, which is provided in a memory controller, to store address data of a defective memory cell. The memory controller storing the address data of a defective memory cell contributes an increase in process speed, because it is not necessary to access the memory cell array in order to obtain the address data of the defective memory cell.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 8467236
    Abstract: A continuously variable resistor is disclosed. The continuously variable resistor may comprise a first chalcogenide layer and a second chalcogenide layer. The second chalcogenide layers may be connected to the first chalcogenide layer and may have a metal interspersed within it. The second chalcogenide layer may be metal-rich, in a state of solid solution with the interspersed metal. The continuously variable resistor may be configured to exhibit NDR behavior. The continuously variable resistor may be configured to have three or more substantially non-volatile resistance states.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: June 18, 2013
    Assignee: Boise State University
    Inventor: Kristy A. Campbell
  • Patent number: 8329535
    Abstract: A memory device having at least one multi-level memory cell is disclosed, and each multi-level memory cell configured to store n multiple bits, where n is an integer, wherein the multiple bits are stored in a charge storage layer trapping charge carriers injected by application of a voltage to set or reset a threshold voltage Vt of the memory cell to one of 2n levels. Each memory cell may be programmed to one of 2n multiple levels, wherein each level represents n multiple bits.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: December 11, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chao-I Wu
  • Patent number: 8299450
    Abstract: A non-volatile memory device includes a lower electrode, a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. The phase-change material layer includes a phase-change material including a composition represented by the formula (I)A(IIXIIIYIVZ)(1-A), where I is at least one of As and Se, II is at least one of Ge, Si and Sn, III is at least one of Sb and Bi, and IV is at least one of Te and Se, and where 0.001?A?0.3, 0.001?X?0.3, 0.001?Y?0.8, 0.1?Z?0.8, and X+Y+Z=1.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-ho Ahn, Hideki Horii, Soon-oh Park, Young-hyun Kim, Heo-ju Shin, Jin-ho Oh
  • Patent number: 8238146
    Abstract: The invention relates to the use of chalcogenide devices exhibiting negative differential resistance in integrated circuits as programmable variable resistor components. The present invention is a continuously variable integrated analog resistor made of a chalcogenide material, such as a GeSeAg alloy. Continuously variable resistor states are obtained in the material via application of an electrical pulse to it. The pulse sequence, duration and applied potential determine the value of the resistance state obtained.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: August 7, 2012
    Assignee: Boise State University
    Inventor: Kristy A. Campbell
  • Patent number: 8194435
    Abstract: This invention relates to a high-speed volatile and non-volatile memory assemblies. And, an inventive FET and capacitor are also revealed and introduced into the memory assembly to enhance its performance. Further, the memory assembly has physical addressing capability with CPU so that operating system stored in the memory assembly can be quickly booted.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: June 5, 2012
    Inventors: Yen-Wei Hsu, Whei-Chyou Wu
  • Patent number: 8125003
    Abstract: One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Publication number: 20120014161
    Abstract: A memristive Negative Differential Resistance (NDR) device includes a first electrode adjacent to a memristive matrix, the memristive matrix including an intrinsic semiconducting region and a highly doped secondary region, a Metal-Insulator-Transition (MIT) material in series with the memristive matrix, and a second electrode adjacent to the MIT material.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Matthew D. Pickett, Julien Borghetti, Gilberto Medeiros Ribeiro
  • Patent number: 8081501
    Abstract: A multi-level nonvolatile memory device using variable resistive element with improved reliability of read operations is provided. A multi-level nonvolatile memory device comprises a multi-level memory which includes a resistance element, wherein the resistance level of the resistance element is variable depending on data stored in the multi-level memory cell, and a read circuit which provides the multi level memory cell with a read bias and performs a sensing operation in response to the read bias, wherein the read bias has at least two levels during a read cycle.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Gil Choi, Du-Eung Kim
  • Patent number: 7995380
    Abstract: A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: August 9, 2011
    Assignee: Synopsys, Inc.
    Inventor: Tsu-Jae King Liu
  • Patent number: 7961505
    Abstract: An electronic device includes: a first conductor; an insulative supporting film formed in a part on one surface of the first conductor; and a second conductor, one surface of which is opposed to the one surface of the first conductor and a part of which is supported by the supporting film. An air gap is formed in a region in which the first conductor and the second conductor are opposed to each other excluding the supporting film. The thickness of the supporting film is larger than a space between the first conductor and the second conductor, at least a part of which forms the air gap.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: June 14, 2011
    Assignee: Sony Corporation
    Inventor: Masayoshi Sasaki
  • Patent number: 7961540
    Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: June 14, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Farid Nemati, Hyun-Jin Cho, Robert Homan Igehy
  • Patent number: 7940558
    Abstract: An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: May 10, 2011
    Assignee: Qimonda AG
    Inventor: Stefan Slesazeck
  • Patent number: 7924603
    Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: April 12, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Patent number: 7855910
    Abstract: A memory device including a plurality of electric elements corresponding to a plurality of transistors on a one-to-one basis; a word line driver for driving a plurality of word lines; and a bit line/plate line driver for driving a plurality of bit lines and a plurality of plate lines. Each of the plurality of electric elements includes a first electrode connected to one of the transistors corresponding to the electric element, a second electrode connected to one of the plate lines corresponding to the electric element, and a variable-resistance film connected between the first electrode and the second electrode, and the variable-resistance film includes Fe3O4 as a constituent element and has a crystal grain size of 5 nm to 150 nm.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: December 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Satoru Mitani, Koichi Osano, Shunsaku Muraoka, Kumio Nago
  • Patent number: 7778063
    Abstract: An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: August 17, 2010
    Assignee: Symetrix Corporation
    Inventors: Matthew D. Brubaker, Carlos A. Paz de Araujo, Jolanta Celinska
  • Patent number: 7745808
    Abstract: The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes and to methods of making such a device. The stored data is semi-volatile. Generally, information written to a device in accordance with the invention can maintain its memory for a matter of minutes, hours, or days before a refresh is necessary. The power requirements of the device are far reduced compared to DRAM. The memory function of the device is highly stable, repeatable, and predictable. The device can be produced in a variety of ways.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 29, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Patent number: 7724587
    Abstract: In reading data from a memory cell, a determining circuit determines whether a received voltage value is within at least one first voltage range through a one-time read operation using a semiconductor device that senses an output current corresponding to the received voltage value. The at least one first voltage range includes a first upper limit voltage value and a first lower limit voltage value. A data value of the memory cell is set as a first data value when the received voltage value is within the specific voltage range.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: May 25, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hwan Song, Dong Hyuk Chae, Jun Jin Kong, Seung Hoon Lee, Dongku Kang
  • Patent number: 7682992
    Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: March 23, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Publication number: 20100027324
    Abstract: The invention relates to the use of chalcogenide devices exhibiting negative differential resistance in integrated circuits as programmable variable resistor components. The present invention is a continuously variable integrated analog resistor made of a chalcogenide material, such as a GeSeAg alloy. Continuously variable resistor states are obtained in the material via application of an electrical pulse to it. The pulse sequence, duration and applied potential determine the value of the resistance state obtained.
    Type: Application
    Filed: August 3, 2009
    Publication date: February 4, 2010
    Applicant: BOISE STATE UNIVERSITY
    Inventor: KRISTY A. CAMPBELL
  • Patent number: 7630235
    Abstract: A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: December 8, 2009
    Assignee: GlobalFoundries Inc.
    Inventor: Hyun-Jin Cho
  • Patent number: 7577022
    Abstract: An electric element includes: a first electrode (1); a second electrode (3); and a layer (2) connected between the first electrode and the second electrode and having a diode characteristic and a variable resistance characteristic. The layer (2) conducts a substantial electric current in a forward direction extending from one of the first electrode (1) and the second electrode (3) to the other electrode as compared to a reverse direction opposite of the forward direction. The resistance value of the layer (2) for the forward direction increases or decreases according to a predetermined pulse voltage applied between the first electrode (1) and the second electrode (3).
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: August 18, 2009
    Assignee: Panasonic Corporation
    Inventors: Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Hiroshi Seki
  • Publication number: 20090190392
    Abstract: An electronic device includes: a first conductor; an insulative supporting film formed in a part on one surface of the first conductor; and a second conductor, one surface of which is opposed to the one surface of the first conductor and a part of which is supported by the supporting film. An air gap is formed in a region in which the first conductor and the second conductor are opposed to each other excluding the supporting film. The thickness of the supporting film is larger than a space between the first conductor and the second conductor, at least a part of which forms the air gap.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 30, 2009
    Applicant: Sony Corporation
    Inventor: Masayoshi Sasaki
  • Patent number: 7508701
    Abstract: Negative differential resistance devices are implemented to facilitate current flow under different operating conditions. According to an example embodiment of the present invention, an NDR device is arranged for selective passage of current through relatively high tunneling efficiency regions and relatively low tunneling efficiency regions. In some applications, a gate is used to accumulate carriers to facilitate the passage of current that is predominantly one of tunneling current and generation current, respectively, by controlling the passage of current through a relatively high tunneling efficiency region and a relatively low tunneling efficiency region. In some implementations, the NDR device is arranged to mitigate leakage in a storage device using a two-terminal connection.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: March 24, 2009
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Yue Liang, Kailash Gopalakrishnan, Peter Griffin, James D. Plummer
  • Patent number: 7505309
    Abstract: An SRAM memory device having improved stability including two series connected devices, at least one of the devices being a chalcogenide device exhibiting differential negative resistance characteristics. One of the two devices serves as the load of the other. A switch is provided to bias a middle input node and switch the memory device between two logic states.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: March 17, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Terry L. Gilton
  • Patent number: 7460395
    Abstract: A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: December 2, 2008
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Hyun-Jin Cho, Farid Nemati
  • Patent number: 7440310
    Abstract: One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of the memory cell, including forward biasing a thyristor to switch the thyristor into a high conductance low impedance state, and storing a first charge type in the storage node and storing the first charge type in a trapping insulator separating a floating body of an access transistor from the thyristor. The method further includes discharging the storage node of the memory cell, including reverse biasing the thyristor into a low conductance high impedance state, and discharging the first charge type from the storage node and discharging the first charge type from the trapping insulator. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: October 21, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7405963
    Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: July 29, 2008
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Farid Nemati, Hyun-Jin Cho, Robert Homan Igehy
  • Publication number: 20080123395
    Abstract: To provide a nonvolatile memory including a word-line drive circuit that supplies a selective voltage to a selective transistor connected in series to a nonvolatile memory device. The word-line drive circuit applies a first selective voltage VDD to a control electrode of the selective transistor in a first period, and applies a second selective voltage VPP higher than the first selective voltage VDD to the control electrode of the selective transistor in a second period that follows the first period. Thereby, a current drive capability of the selective transistor is gradually changed. Thus, it becomes possible to limit the current drive capability of the selective transistor at timing at which snap-back is caused. As a result, an excessive current caused by the snap-back is suppressed, thereby reducing damage inflicted on the nonvolatile memory device.
    Type: Application
    Filed: June 29, 2007
    Publication date: May 29, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kiyoshi NAKAI
  • Patent number: 7336523
    Abstract: A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory device, a nanotube cell array comprising a capacitor and a PNPN nanotube switch which does not require an additional gate control signal is located between a word line and the sub-bit line, so that a cross point cell array is embodied to reduce the whole chip size.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: February 26, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang