Abstract: In one embodiment, a desirable (e.g., substantially 100%) SOT switching probability is achieved in a SOT device by applying in-plane input current as one or more pulses having a tuned pulse width. In the case of a single pulse, pulse width may be selected as a single tuned pulse width or a range of pulse widths that avoid a specific pulse width determined to cause a switch-back response. In the case of multiple pulses, pulse width, a time interval between pulses and other factors such as intensities may be selected to prevent a switch-back response. Further, SOT switching speed may be achieved by reducing incubation delay through modification of an external magnetic field or input current density applied to the SOT device.

Abstract: A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

Abstract: In one embodiment, a bit state in a supply-switched dual cell memory bitcell in accordance with the present description, may be read by coupling a supply line to a common node of the bitcell to drive complementary currents through complementary resistance state storage cells for a pair of complementary bit line signal lines of the bitcell. The bit state of the bitcell may be read by sensing complementary bit state signals on the pair of first and second complementary bit line signal lines. In one embodiment, each resistance state storage cell has a resistance state ferromagnetic device such as a magnetic-tunneling junction (MTJ). In one embodiment, a supply-switched dual cell memory bitcell in accordance with the present description may lack a source or select line (SL) signal line. Other aspects are described herein.

Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction for storing data may include a fixed layer, a barrier layer, and a composite free layer. A barrier layer may be disposed between a fixed layer and a composite free layer. A composite free layer may include one or more ferromagnetic layers. A composite free layer may include one or more anisotropy inducer layers that induce an in-plane magnetic anisotropy for the composite free layer in response to a perpendicular bias voltage.

Abstract: A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

Abstract: In order to stably write data into a magnetic memory that uses in-plane current-induced perpendicular switching of magnetization to write data, the magnetic memory includes a recording layer formed as a perpendicular magnetization film, an adjacent layer joined to an upper surface or a lower surface of the recording layer, an external magnetic field application part configured to apply a first external magnetic field to the recording layer in a first direction which is an in-plane direction of the recording layer, and a current application part configured to allow a write current to flow through the adjacent layer in the first direction or a second direction which is opposite to the first direction. The external magnetic field application part is configured to switch a direction of a second external magnetic field applied in a direction perpendicular to the first direction in accordance with a direction of the write current.

Abstract: According to one embodiment, a magnetic memory element comprises a first magnetic unit, a second magnetic unit, a first insulating unit, a first electrode, a second electrode, and a third electrode. The first magnetic unit includes a plurality of magnetic domains. The second magnetic unit includes a first region and a second region. The first region includes a conductive material. The second region includes an insulating material. At least one of the first region or the second region is magnetic. The first insulating unit is provided between the first magnetic unit and the second magnetic unit. The first electrode and the second electrode are connected to the first magnetic unit. A part of the second magnetic unit and a part of the first insulating unit are provided between the third electrode and a part of the first magnetic unit.

Abstract: A multibit MRAM cell including a magnetic tunnel junction including a sense layer having a freely orientable sense magnetization; a tunnel barrier layer; and a synthetic antiferromagnet storage layer having a first and second storage layer. The sense magnetization induces a dipolar field having a magnitude above a spin-flop field of the storage layer. The MRAM cell also includes aligning means for aligning the sense magnetization in a plurality of distinct orientations such as to encode a plurality of distinct logic states in the MRAM cell. The present disclosure also concerns a method for operating the multibit MRAM cell.

Abstract: A magnetic memory device includes a substrate, a circuit device on the substrate, a lower electrode electrically connected to the circuit device, a magnetic tunnel junction structure (MTJ structure) on the lower electrode, and an upper electrode on the MTJ structure. The MTJ structure includes a pinned layer structure including at least one crystalline ferromagnetic layer and at least one amorphous ferromagnetic layer, a free layer, and a tunnel barrier layer between the pinned layer structure and the free layer.

Abstract: Embodiments described herein are related to contactless data communication. Related systems and methods for contactless data communication are disclosed herein. For example, a magnetic field-based contactless transmitter is disclosed that includes a substrate, a pair of dipole coils disposed on the substrate, and a drive circuit electrically coupled to the pair of dipole coils. To transmit data to a magnetic tunnel junction (MTJ) receiver disposed on a second substrate, the drive circuit is configured to drive the pair of dipole coils so as to generate a magnetic field in-plane to the MTJ receiver. Data can be transmitted from the magnetic field-based contactless transmitter to the MTJ receiver using the magnetic field.

Abstract: An electronic device includes a semiconductor memory unit, which includes resistive memory cells; an access circuit to apply, during a write operation, a write voltage across a selected one of the resistive memory cells in a first or second direction; first switching units, each of which is disposed between the access circuit and a first end of a corresponding one of the resistive memory cells and turned on in response to a first voltage having a level higher than a predetermined level when the corresponding resistive memory cell is selected during the write operation; and second switching units, each of which is disposed between the access circuit and a second end of the corresponding resistive memory cell and turned on in response to a second voltage having a level equal to or lower than the predetermined level when the corresponding resistive memory cell is selected during the write operation.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a free layer comprising CoFeGeB alloy, and having a changeable magnetization direction that is perpendicular to the free layer; a tunnel barrier layer positioned over the free layer, and configured for enabling electron tunneling; a pinned layer positioned over the tunnel barrier layer, and having a pinned magnetization direction that is perpendicular to the pinned layer; and a bottom layer positioned under the free layer, and having a B2 structure to improve a perpendicular magnetic crystalline anisotropy of the free layer.

Abstract: An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. The conductive upper electrode has a lower portion and an upper portion. The lower portion overlies the magnetic tunnel junction and is laterally surrounded by an encapsulation structure. The upper portion is arranged onto the lower portion and the encapsulation structure, and laterally extends past the lower portion of the conductive upper electrode. By laterally extending past the lower portion, the upper portion of the conductive upper electrode gives a via a larger landing area than the lower portion of the upper electrode would provide, thereby mitigating via punch through resulting from overlay errors.

Abstract: A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.

Abstract: Example embodiments relate to magnetic memory devices and methods for manufacturing the same. The magnetic memory device includes a magnetic tunnel junction layer including a first magnetic layer, a second magnetic layer, and a first tunnel barrier layer between the first and second magnetic layers. The second magnetic layer is disposed on the first tunnel barrier layer and is in direct contact with the first tunnel barrier layer. The second magnetic layer includes cobalt-iron-beryllium (CoFeBe). A beryllium content of CoFeBe in the second magnetic layer ranges from about 2 at % to about 15 at %.

Abstract: A magnetic storage media which has an endurance (durability) characteristics close to an infinite number of writing times of data and a data retention (holding) characteristics close to permanency, and is ultra-high-speed writable and erasable, and a data storage device and an image storage device which apply this magnetic storage media are provided. A magnetic storage media includes a thin layer magnet and a magnetic field generating unit arranged facing a surface of the magnet, and is capable of creating or eliminating a skyrmion by applying heat energy to another surface of the magnet positioned on the opposite side of the surface of the magnet, and a skyrmion memory includes the magnetic storage media.

Abstract: A magnetic storage apparatus is disclosed, and is configured to access data. The magnetic storage apparatus includes a magnetic storage track, a first write apparatus, a second write apparatus, and a drive apparatus. The first write apparatus and the second write apparatus are located at different positions on the magnetic storage track. The first write apparatus is configured to write first data “0” or second data “1”. The second write apparatus is configured to write third data “2” and fourth data “3”.

Abstract: According to one embodiment, a magnetic memory element includes a stacked structure. The stacked structure includes a first and a second stacked member. The first stacked member includes a first and second ferromagnetic layer. A magnetic resonance frequency of the second ferromagnetic layer is a first frequency. A direction of a magnetization of the second ferromagnetic layer is settable to a direction of a first current when a magnetic field of the first frequency is applied to the first stacked member and the first current flows in the first stacked member. The direction of the magnetization of the second ferromagnetic layer does not change when the second current smaller than the first current flows in the first stacked member. The second stacked member includes a third ferromagnetic layer. A magnetization of the third ferromagnetic layer can generate a magnetic field of the first frequency by the second current.

Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.

Abstract: The present invention is directed to an MTJ memory element comprising a magnetic free layer structure including one or more magnetic free layers that have a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure including a first magnetic reference layer and a second magnetic reference layer with a perpendicular enhancement layer interposed therebetween, the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer.

Abstract: According to one embodiment, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode, and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to transition a resistive state of the memory cell. The control circuit performs a first reset operation by applying a first pulse having a voltage of a first polarity to the memory cell, and applying a second pulse having a voltage of a second polarity that is an inverse of the first polarity to the memory cell after applying the first pulse.

Abstract: Example embodiments relate to a magnetic memory device that includes a magnetic tunnel junction layer including a first magnetic layer, a second magnetic layer, and a first tunnel barrier layer between the first and second magnetic layers. The second magnetic layer is disposed on the first tunnel barrier layer and is in direct contact with the first tunnel barrier layer. The second magnetic layer includes cobalt-iron-beryllium (CoFeBe). A beryllium content of CoFeBe in the second magnetic layer ranges from about 2 at % to about 10 at %.

Abstract: An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.

Abstract: A holographic polymer dispersed liquid crystal (HPDLC) tunable filter exhibits switching times of no more than 20 microseconds. The HPDLC tunable filter can be utilized in a variety of applications. An HPDLC tunable filter stack can be utilized in a hyperspectral imaging system capable of spectrally multiplexing hyperspectral imaging data acquired while the hyperspectral imaging system is airborne. HPDLC tunable filter stacks can be utilized in high speed switchable optical shielding systems, for example as a coating for a visor or an aircraft canopy. These HPDLC tunable filter stacks can be fabricated using a spin coating apparatus and associated fabrication methods.

Abstract: Provided is a skyrmion memory circuit capable of circularly transferring a magnetic element skyrmion, comprising one or more current paths in a magnet having a closed-path pattern that are provided surrounding an end region including an end portion of the magnet in a plane of the magnet with the closed-path pattern, and applying current between an outer terminal connected to an outer circumferential portion of the closed-path pattern and an inner circumference electrode connected to an inner circumferential portion of the closed-path pattern, transferring the skyrmion in a direction substantially perpendicular to the direction of the applied current, and circulating the skyrmion in the magnet with the closed-path pattern.

Abstract: An apparatus includes circuits including a first circuit and a second circuit, each circuit including subarrays of magnetic tunnel junctions, where: (1) the magnetic tunnel junctions in each subarray are arranged in rows, the magnetic tunnel junctions in each row are connected in series, and the rows are connected in parallel; and (2) the subarrays are connected in series. The apparatus further comprises a field line configured to generate a first magnetic field for configuring an operating point of the first circuit based on a current flow through the field line, where the impedance of a subset of the plurality of rows in each subarray of magnetic tunnel junctions included in the first circuit is configured based on the first magnetic field.

Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.

Abstract: According to one embodiment, an integrated circuit includes first and second data lines, a first memory cell includes first and second resistance changing elements connected in series between the first and second data lines and a first selection transistor including a drain connected to a connection node of the first and second resistance changing elements, and a second memory cell includes third and fourth resistance changing elements connected in series between the first and second data lines and a second selection transistor including a drain connected to a connection node of the third and fourth resistance changing elements.

Abstract: A memory architecture has improved controllability of operations for bipolar current directions used to write data in programmable resistance memory cells, including ReRAM cells based on metal oxide memory materials. Instead of a fixed gate voltage on a specific decoder transistor or cell selection device, and a control voltage set to values that cause the decoder transistor or cell selection device to operate in a fully-on mode for one current direction or in a current moderating mode with opposite current direction. Using this technology allows symmetrical or close to symmetrical operation in both current directions with little or no effect on the array complexity.

Abstract: A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state (e.g., to a highest resistance state), but existing techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that causes the state change.

Abstract: A method of reading a memory cell of a magneto-resistive random access memory device, wherein the memory cell has a ferromagnetic free layer having a first magnetization orientation and a ferromagnetic reference layer, includes applying a first read current from the ferromagnetic free layer to the ferromagnetic reference layer and storing a first voltage generated by the memory cell in response to the first read current, generating a magnetic field adjacent to the memory cell, the magnetic field having a second magnetization orientation that is not parallel to the first magnetization orientation, while the magnetic field is being generated, applying a second read current from the ferromagnetic free layer to the ferromagnetic reference layer and storing a second voltage generated by the memory cell in response to the second read current, and determining a state of the memory cell based on the first voltage and the second voltage.

Abstract: A plasmon generator generates a surface plasmon, and generates a near-field light from the surface plasmon on a front end surface positioned on an air bearing surface opposing to a magnetic recording medium. The plasmon generator has a first surface that is adjacent to the front end surface and that faces a lower layer where the plasmon generator is deposited, and a second surface at the back side of the first surface relative to a down track direction. The first surface tilts toward a surface that is orthogonal to the down track direction, and, is parallel to across track direction, and the plasmon generator is deposited with a (111) orientation from the first surface toward the second surface.

Abstract: Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F2 within an individual of the tiers. Also disclosed is an array of nonvolatile memory cells comprising a plurality of unit cells which individually comprise three elevational regions of programmable material, the three elevational regions comprising the programmable material of at least three different memory cells of the unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells. Other embodiments and aspects are disclosed.

Abstract: A magnetoresistive element has a crystalline structural quality and magnetic anisotropy enhancement bilayer (CSMAE bilayer) with a). enhanced the crystalline structural quality, hence fabrication yield, of the resulting magnetoresistive element; and b). enhanced the magnetic anisotropy of the recording layer whereby achieving a high MR ratio for the magnetoresistive element with a simultaneous reduction of an undesirable spin pumping effect. As the magnetoresistive film is thermally annealed, a crystallization process occurs to form bcc CoFe grains having epitaxial growth with (100) plane parallel to the surface of the tunnel barrier layer as Boron elements migrate into the impurity absorbing layer. Removing the top portion of the impurity absorbing layer by means of sputtering etch or RIE etch processes followed by optional oxidization process, a thin but thermally stable portion of impurity absorbing layer is formed on top of the magnetoresistive element with a low damping constant.

Abstract: Systems, methods, and other embodiments associated with providing real time closed loop control of memory access are described. According to one embodiment, a method includes accessing a memory of a computing device during real time operation of the computing device and detecting bit errors associated with the accessing of the memory. The method also includes generating a performance metric based on, at least in part, the detected bit errors during the real time operation of the computing device. The method further includes adjusting a setting of at least one timing element, of a plurality of timing elements of a physical layer of the computing device, based on the performance metric during the real time operation of the computing device to maintain a determined memory access performance.

Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.

Abstract: The present invention is notably directed to a spin-orbit coupled device. This device comprises a confinement part. It further includes a circuitry, having an input device, energizable to inject spin-polarizations to charge carriers in an input region of the confinement part. The circuitry further comprises an output device, usable to detect spin-polarizations of charge carriers in an output region of the confinement part. The confinement part may be is configured to subject charge carriers drifting therein to a non-linear spin-orbit interaction, which causes to rotate a spin polarization of the drifting charge carriers by an angle that depends non-linearly on momenta of such charge carriers. The circuitry may be configured to allow momenta of charge carriers drifting in the confinement part to be varied, while injecting spin-polarizations in the input region. Varying momenta allows spin-polarizations of drifting charge carriers to be rotated, owing to said non-linear spin-orbit interaction.

Abstract: A memory element includes a memory layer having magnetization perpendicular to a film face of the memory layer in which a direction of the magnetization configured to be changed. The memory element includes a magnetization-fixed layer having a magnetization perpendicular to the film face. The memory element includes an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. The memory layer includes a multilayer structure in which a non-magnetic material and an oxide are laminated. The direction of the magnetization of the memory layer is configured to be changed by applying a current in a lamination direction of the layered structure to record information in the memory layer.

Abstract: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.

Abstract: A spin transport channel includes a dielectric layer contacting a conductive layer. The dielectric layer includes at least one of a tantalum oxide, hafnium oxide, titanium oxide, and nickel oxide. An intermediate spin layer contacts the dielectric layer. The intermediate spin layer includes at least one of copper and silver. The conductive layer is more electrochemically inert than the intermediate spin layer. A polarizer layer contacts the intermediate spin layer. The polarizer layer includes one of a nickel-iron based material, iron, and cobalt based material. The conductive layer and intermediate layer are disposed on opposite sides of the dielectric layer. The dielectric layer and the polarizer layer are disposed on opposite sides of the intermediate spin layer. The intermediate spin layer is arranged to form a conducting path through the dielectric layer configured to transport a plurality of electrons. Each of the plurality of electrons maintains a polarized electron spin.

Abstract: A magnetic memory element includes a first magnetic unit, a second magnetic unit, a third magnetic unit, a read/write unit, a first electrode, a second electrode, a third electrode, a first current source, the second current source. The third magnetic unit is connected to one end in the first direction of the first magnetic unit and one end in the first direction of the second magnetic unit. The read/write unit includes a nonmagnetic layer and a pinned layer. The nonmagnetic layer is connected to the third magnetic unit. The pinned layer is connected to the nonmagnetic layer. The first current source causes a current to flow between the third electrode and at least one of the first electrode or the second electrode. The second current source causes a current to flow between the first electrode and the second electrode.

Abstract: An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period ? has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of memory access of the basic circuit element 1A satisfies the following relation: ?>?1/f1(0<?1?1).

Abstract: There is provided a magnetoresistive element whose magnetization direction is stable in a direction perpendicular to the film surface and whose magnetoresistance ratio is controlled, as well as magnetic memory using such a magnetoresistive element. By having the material of a ferromagnetic layer forming the magnetoresistive element comprise a ferromagnetic material containing at least one type of 3d transition metal, or a Heusler alloy, to control the magnetoresistance ratio, and by controlling the thickness of the ferromagnetic layer on an atomic layer level, the magnetization direction is changed from being in-plane with the film surface to being perpendicular to the film surface.

Abstract: A storage device comprises at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device. The storage device searches for a read voltage for at least one memory cell in at least one page when power is turned on following a power-off state, calculates an off-time corresponding to the searched read voltage using a voltage-to-time lookup table, and sets a timer of the storage device using a time stamp corresponding to a page programmed before the power-off, and the off-time.

Abstract: An antiferromagnetic nanostructure according to one embodiment includes an array of at least two antiferromagnetically coupled magnetic atoms having at least two magnetic states that are stable for at least one picosecond even in the absence of interaction with an external structure, the array having a net magnetic moment of zero or about zero, wherein the array has 100 atoms or less along a longest dimension thereof. An atomic-scale structure according to one embodiment has a net magnetic moment of zero or about zero; two or more stable magnetic states; and having an array of atoms that has magnetic moments that alternate between adjacent magnetic atoms along one or more directions. Such structures may be used to store data at ultra-high densities.

Abstract: This invention is about a method to make an MRAM element with small dimension, by building an MTJ as close as possible to an associated via connecting an associated circuitry in a semiconductor wafer. The invention provides a process scheme to flatten the interface of bottom electrode during film deposition, which ensures a good deposition of atomically smooth MTJ multilayer as close as possible to an associated via which otherwise might be atomically rough. The flattening scheme is first to deposit a thin amorphous conducting layer in the middle of BE deposition and immediately to bombard the amorphous layer by low energy ions to provide kinetic energy for surface atom diffusion to move from high point to low kinks. With such surface flattening scheme, not only the MRAM element can be made extremely small, but its device performance and magnetic stability can also be greatly improved.

Abstract: To provide a memory apparatus capable of operating at high speed with less current and inhibiting a decrease in an amplitude of a readout signal. A memory apparatus includes a memory device at least including a memory layer, a magnetic fixed layer, and an intermediate layer made of a non-magnetic body disposed between the memory layer and the magnetic fixed layer; current being capable of flowing in a lamination direction; a wiring for supplying current flowing to the lamination direction; and a memory control unit for storing information by flowing standby current at a predetermined level to the memory device via the wiring to incline the magnetization direction of the memory layer from the direction perpendicular to a film surface and flowing recording current that is higher than the standby current via the wiring to change the magnetization direction of the memory layer.

Abstract: A semiconductor device includes: a semiconductor substrate including a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.