Abstract: A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.

Abstract: Provided are semiconductor devices and methods for fabricating and using the semiconductor devices, wherein the semiconductor devices may include a first element, a second element, and a plurality of parallel IO lines connecting the first element with the second element. The plurality of IO lines may have different lengths and the shortest IO line from among the plurality of the IO lines may be adjacent to a longest IO line from among the plurality of the IO lines.

Abstract: A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time.

Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line.

Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

Abstract: An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.

Abstract: A memory device is provided which includes a write bit line, a read bit line, and at least one memory cell. The memory cell includes a write access transistor, a read access transistor coupled to the read bit line and to the first write access transistor, and a gated-lateral thyristor (GLT) device coupled to the first write access transistor. Among its many features, the memory cell prevents read disturbances during read operations by decoupling the read and write bit lines.

Abstract: A data read/write device according to an example of the present invention includes a recording layer, and means for applying a voltage to the recording layer, generating a resistance change in the recording layer, and recording data. The recording layer is composed of a composite compound having at least two types of cation elements, at least one type of the cation element is a transition element having a “d” orbit in which electrons have been incompletely filled, and the shortest distance between the adjacent cation elements is 0.32 nm or less.

Abstract: A stacked memory cell for use in a high-density static random access memory is provided that includes first and second pull-down transistors formed in a first layer, a pass transistor connected between a gate of the second pull-down transistor and a bit line and formed in the first layer and a first and second pull-up transistors formed in a second layer located above the first layer and connected with the first and second pull-down transistors respectively to form an inverter latch. With the construction of a stacked memory cell having a lone pass transistor, cell size is reduced compared to a conventional six-transistor cell, and driving performance of the pass transistor can be improved.

Abstract: A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.

Abstract: A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated.

Abstract: An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions.

Abstract: A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first diameter. In a particular embodiment, the pillars associated with the plurality of memory cells may define rows and columns of an array. In a further embodiment, a pillar may be spaced by a first distance of magnitude up to the first diameter relative to a neighboring pillar within its row. In an additional further embodiment, the pillar may be spaced by a second distance of a magnitude up to twice the first diameter, relative to a neighboring pillar within its column.

Abstract: A memory device includes a bit line, a reading word line, a bit line contact, an electrode, a writing word line and a contact tip. The bit line is formed on a substrate. The reading word line is formed over the bit line. The bit line contact is disposed between adjacent reading word lines. The electrode extends substantially in parallel to the reading word line and includes a conductive material being bent in response to an applied voltage. The writing word line is formed over the electrode and is separated from the electrode. The contact tip is formed at an end portion of the electrode and is separated from the reading and the writing word lines. The contact tip protrudes toward the reading word line or writing word line.

Abstract: In the semiconductor memory device having a resistance memory element, a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage, and a second transistor having source terminal connected to the resistance memory element, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from a low resistance state to a high resistance state, a voltage is controlled to be a value which is not less than a reset voltage and less than a set voltage by applying to a gate terminal of the second transistor a voltage which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage.

Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

Abstract: An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive channel includes the first carbon material.

Abstract: Colloidal-processed Si particle devices, device fabrication, and device uses have been presented. The generic device includes a substrate, a first electrode overlying the substrate, a second electrode overlying the substrate, laterally adjacent the first electrode, and separated from the first electrode by a spacing. A colloidal-processed Si particle layer overlies the first electrode, the second electrode, and the spacing between the electrodes. The Si particle layer includes a first plurality of nano-sized Si particles and a second plurality of micro-sized Si particles.

Abstract: A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.

Abstract: A novel nonvolatile memory element, which can be manufactured by a simple and high yield process by using an organic material and has a high on/off ratio, and a method for manufacturing such nonvolatile memory element. A switching layer (14) made of an electrical insulating radical polymer is provided between an anode layer (12) and a cathode layer (16). Further, a hole injection transport layer (13) is provided between the switching layer (14) and the anode layer (12), and an electron injection transport layer (15), between the switching layer (14) and the cathode layer (16). An intermediate layer is provided between the switching layer and the adjacent layer. The radical polymer is preferably nitroxide radical polymer. The switching layer (14), the hole injection transport layer (13) and the electron injection transport layer (15) are formed by being stacked by a wet process.

Abstract: A non-volatile memory cell and method of use therefore are disclosed. In accordance with various embodiments, the memory cell comprises a tunneling region disposed between a conducting region and a metal region, wherein the tunneling region comprises an active interface region disposed between a first tunneling barrier and a second tunneling barrier. A high resistive film is formed in the active interface region with migration of ions from both the metal and conducting regions responsive to a write current to program the memory cell to a selected resistive state.

Abstract: A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and drain layer and lower than the other of the potentials of the source and drain layer so that electric charges flow in the body region, and a potential of the second gate electrode is set to be higher as an absolute value than those of potentials of the source layer, drain layer, and first gate electrode so that electric charges flow from the body region, and in the data holding state, the memory cell is kept in a stationary state that a first amount of the electric charges flowing in the body region per unit time is substantially the same as a second amount of the electric charges flowing from the body region per unit time.

Abstract: One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.

Abstract: A memory device including a plurality of electric elements corresponding to a plurality of transistors on a one-to-one basis; a word line driver for driving a plurality of word lines; and a bit line/plate line driver for driving a plurality of bit lines and a plurality of plate lines. Each of the plurality of electric elements includes a first electrode connected to one of the transistors corresponding to the electric element, a second electrode connected to one of the plate lines corresponding to the electric element, and a variable-resistance film connected between the first electrode and the second electrode, and the variable-resistance film includes Fe3O4 as a constituent element and has a crystal grain size of 5 nm to 150 nm.

Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract: Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel region is formed around a perimeter of the source/drain region. Such transistors should facilitate a reduction in edge effect and leakage as the channel of the transistor is not bordering on an isolation region. Additionally, the use of a source/drain region extending through a channel region facilitates high-power, high-voltage operation.

Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.

Abstract: Memory devices and methods for operating such devices are described herein. A memory cell as described herein comprises a transistor electrically coupled to first and second access lines. A programmable resistance memory element is arranged along a current path between the first and second access lines. A capacitor is electrically coupled to the current path between the first and second access lines.

Abstract: To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.

Abstract: This invention provides approaches to improve the signal to noise ratio (S/N) in electrochemical measurements (e.g., amperometry, voltammetry, etc.). In particular, a method is described wherein the faradaic current is temporally dissociated from the charging current associated with reading the charge of a redox-active species (e.g., a self-assembled monolayer (SAM)). This method, designated herein as open circuit potential amperometry (OCPA), quantitatively reads the charge of the redox species bound to (electrically coupled to) an electrode surface, while discriminating against both charging current(s) and amperometric signal(s) that arise, e.g., from diffusion-based species in solution.

Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

Abstract: The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the electrical characteristics of the TFT in order to integrate with other electrical components formed by TFTs, such as logic circuit or TFT-LCD pixel transistor, on the LCD panel without additional semiconductor manufacturing processes.

Abstract: A nonvolatile solid state magnetic memory with a ultra-low power consumption and a recording method thereof, the memory including a magnetic material having a magnetic anisotropy that can be changed by increasing or decreasing a carrier concentration, wherein a direction of an easy axis of magnetization, in which the magnetization is oriented easily, is controlled by increasing or decreasing the carrier concentration. The nonvolatile solid state magnetic memory including a recording layer of a magnetic material, and a recording method thereof, in which a carrier (electron or hole) concentration in the recording layer is increased and/or decreased, whereby the magnetization is rotated or reversed and the recording operation is performed.

Abstract: A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector.

Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

Abstract: A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0<R1<R2) are selectively set, wherein resistance gaps ?R1(=R1?R0) and ?R2(=R2?R1) are set to satisfy the relationship of ?R1>?R2.

Abstract: A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Abstract: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.

Abstract: This disclosure concerns a semiconductor memory device including Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an electrically floating state and accumulating or discharging carries so as to store data; first gate electrodes provided in first grooves located between the Fin semiconductors adjacent to each other; second gate electrodes provided in second grooves adjacent to the first grooves and located between the Fin semiconductors adjacent to each other; bit lines connected to the drain layers, and extending in a first direction; word lines connected to the first gate electrodes, and extending in a second direction orthogonal to the first direction; and source lines connected to the source layers, and extending in the second direction.

Abstract: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.

Abstract: A method and system for probing FCode in problem state memory. A PCI device is detected from a PCI-PCI bridge node included in a device tree. A child node for the detected PCI device is created in problem state memory. The active package is switched to the child node, and the processor switches from running in privileged mode to running in problem mode. FCode of an FCode driver in the PCI device is probed. Data, properties and methods generated in response to the probe are created in problem state memory. After the probe is complete, the active package is switched to the parent node of the child node, and the processor switches back to running in privileged mode.

Abstract: A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.

Abstract: A data read/write device according to an example of the present invention includes a recording layer, and means for applying a voltage to the recording layer, generating a resistance change in the recording layer, and recording data. The recording layer is composed of a composite compound having at least two types of cation elements, at least one type of the cation element is a transition element having a “d” orbit in which electrons have been incompletely filled, and the shortest distance between the adjacent cation elements is 0.32 nm or less.

Abstract: Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

Abstract: Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes.

Abstract: A memory device and a manufacturing method thereof are provided. The manufacturing method of memory device includes the following steps. Firstly, a substrate having a substrate surface is provided. Next, at least two memory units separated via a space are formed on the substrate. Then, an insulating layer covering the memory units and the substrate surface is formed. After that, a mask layer only covering the bottom of the insulating layer is formed on the insulating layer. Afterwards, the part of the insulating layer partially covered by the mask layer is etched. Then, the mask layer is removed. Next, the part of the insulating layer where the mask layer is removed is etched. Lastly, a protecting layer is formed on the memory units and in the space between the memory units.

Abstract: A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.