Ion Implantation Patents (Class 365/178)
  • Patent number: 4333164
    Abstract: A read only memory (ROM) comprising word lines, bit lines, virtual ground lines and memory cells of FETs arranged on intersections of the word lines and bit lines. A gate of each cell is connected to one of the word lines. A drain of each cell is connected to one of the bit lines. A source of each cell is connected to one of the virtual ground lines. According to the invention, the particular cells storing information "0" are depletion-type transistors, the threshold voltage of which being lowered by ion implantation. When the ROM is in operation with respect to the memory cells on a selected bit line, the potential difference between a selected word line and a selected virtual ground line is enough to turn on the depletion-type cell but not enough to turn on the other cells, and the potential difference between a nonselected word line and the selected virtual ground line is not enough to turn on the depletion-type cell.
    Type: Grant
    Filed: February 25, 1980
    Date of Patent: June 1, 1982
    Assignee: Fujitsu Limited
    Inventors: Yasuo Orikabe, Masakazu Matsuda
  • Patent number: 4295209
    Abstract: An IGFET ROM is programmed later in its process of manufacture. An array of IGFETs having an operable channel region and gate electrode is provided. The gate electrode is penetrable by an ion beam. A first dielectric penetrable by the ion beam is deposited onto the array. A second dielectric not penetrable by the ion beam is then deposited onto the array. Windows are then etched into the second dielectric material but not the first, over channel regions of selected IGFETs. The wafer surface is given an ion implantation to change threshold voltage of those IGFETs selected. A metallization pattern is formed on the second dielectric, with the first dielectric providing an insulating coating for gate electrode portions otherwise exposed within the aforementioned windows.
    Type: Grant
    Filed: November 28, 1979
    Date of Patent: October 13, 1981
    Assignee: General Motors Corporation
    Inventor: William B. Donley
  • Patent number: 4212083
    Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor elements are beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. Resistors of this type are ideally suited for load devices in static RAM cells.
    Type: Grant
    Filed: August 18, 1978
    Date of Patent: July 8, 1980
    Assignee: Texas Instruments Incorporated
    Inventor: G. R. Mohan Rao
  • Patent number: 4198693
    Abstract: A VMOS read only memory or ROM array is formed by a process compatible with standard N-channel silicon gate manufacturing methods used for circuitry peripheral to the array. The ROM array is programmed after the top level of contacts and interconnections, usually metal, has been deposited and patterned for the periphery. Each cell is formed with a very short channel in a V-shaped anisotropically etched groove. Address lines and gates are polysilicon, and the output lines are defined by elongated N+ regions. The ground or Vss connection to the source of each transistor in the array is provided by a buried N+ epitaxial layer. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned protective oxide as a mask, or using photoresist as a mask prior to application of protective oxide.
    Type: Grant
    Filed: March 20, 1978
    Date of Patent: April 15, 1980
    Assignee: Texas Instruments Incorporated
    Inventor: Chang-Kiang Kuo
  • Patent number: 4164751
    Abstract: Disclosed is a memory system capable of being integrated into a semiconductor substrate and having an array of Hi-C memory cells. The Hi-C cells are selectively addressable by row and column lines. Each cell of the array is comprised of a transistor having a source coupled to a bit line, a gate coupled to a word line, and a drain coupled to a node N. Node N is coupled in parallel to a dielectric capacitor and to a depletion capacitor. The dielectric capacitor and the depletion capacitor are constructed to have substantially the same charge capacity.
    Type: Grant
    Filed: November 10, 1976
    Date of Patent: August 14, 1979
    Assignee: Texas Instruments Incorporated
    Inventor: Aloysious F. Tasch, Jr.
  • Patent number: 4163243
    Abstract: A one-transistor memory cell is provided in which the depletion-layer capacitance of an MOS capacitor is increased by locally enhancing the substrate dopant concentration. In preferred embodiments the substrate may also be doped adjacent to the substrate-insulator boundary with ions of appropriate conductivity type to form a diode junction in the substrate. The effective capacitance of the memory cell is therefore the capacitance of the insulator in parallel with the substantially increased depletion-layer or diode junction capacitance.
    Type: Grant
    Filed: September 30, 1977
    Date of Patent: July 31, 1979
    Assignee: Hewlett-Packard Company
    Inventors: Theodore I. Kamins, Charles G. Sodini
  • Patent number: 4156289
    Abstract: A semiconductor memory has at least one V-MOS transistor which includes a trench and a storage capacitor. A semiconductor substrate is doped with concentration centers of a first conductivity type and has a buried layer which is doped with concentration centers of a second conductivity type opposite to the first conductivity type. At least two additional layers are divided by the trench and have alternately differing conductivity types, the two additional layers and the buried layer being produced by diffusion and/or implantation.
    Type: Grant
    Filed: January 26, 1978
    Date of Patent: May 22, 1979
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kurt Hoffmann, Rudolf Mitterer
  • Patent number: 4151610
    Abstract: A semiconductor memory device comprising an N conductivity type semiconductor substrate, a P conductivity type well formed in a specified section of the surface of the semiconductor substrate, N conductivity type source and drain regions formed in the P conductivity type well, and a gate insulation layer deposited on the surface of the well over the source and drain regions. The P conductivity type well has a higher impurity concentration than the N conductivity type semiconductor substrate and the N conductivity type source and drain regions have a higher impurity concentration than the P conductivity type well. An insulation film is formed on the drain region and the insulation film, a metal electrode layer deposited on the insulation film and drain region collectively institute a capacitor.
    Type: Grant
    Filed: March 15, 1977
    Date of Patent: April 24, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yasoji Suzuki, Kiyofumi Ochii
  • Patent number: 4142111
    Abstract: A cell for a semiconductor memory of the static type employs only one conventional MOS transistor, along with a field implanted resistance and a vertical P-channel junction-type field effect transistor. These elements, along with a resistor element which may be another field implanted resistance or a polysilicon implanted resistance, provide a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.
    Type: Grant
    Filed: January 27, 1977
    Date of Patent: February 27, 1979
    Assignee: Texas Instruments Incorporated
    Inventor: David J. McElroy
  • Patent number: 4139785
    Abstract: An integrated semiconductor memory device of the static type uses a memory cell circuit having an MOS transistor of the conventional type as the access transistor, along with a resistance element buried under field oxide and an inverted field-effect transistor formed by a polycrystalline layer over a gate region. The MOS transistor connects a storage node to the access line, and the inverted field-effect transistor connects the storage node to reference potential. The storage node is connected to a second node through the resistance element, and a resistor connects the second node to a voltage supply; the magnitude of the resistance element varies according to the voltage on the storage node. The impedance of the inverted field-effect is determined by the voltage on the second node which is a moat region forming the gate.
    Type: Grant
    Filed: May 31, 1977
    Date of Patent: February 13, 1979
    Assignee: Texas Instruments Incorporated
    Inventor: David J. McElroy
  • Patent number: 4139786
    Abstract: A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.
    Type: Grant
    Filed: May 31, 1977
    Date of Patent: February 13, 1979
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph H. Raymond, Jr., Keith H. Gudger
  • Patent number: 4112575
    Abstract: Disclosed is a process for constructing an array of memory cells. Each cell is constructed to have a high storage capacity and low leakage current. The cells are formed on a surface of a semiconductor substrate. Each cell has a storage region and an adjacent transfer region. The process forms a deep ion layer and a shallow ion layer in the storage region of each cell. At the storage region-transfer region interface, the deep ion layer lies laterally within the shallow ion layer. In the other portions of the storage region, the deep ion layer extends laterally into adjoining channel stops.
    Type: Grant
    Filed: December 20, 1976
    Date of Patent: September 12, 1978
    Assignee: Texas Instruments Incorporated
    Inventors: Horng-sen Fu, Thomas C. Holloway, Al F. Tasch, Jr., Pallab K. Chatterjee
  • Patent number: 4070653
    Abstract: A self-refresh MOS RAM cell uses a resistor element made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor element is beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. The cell employs two transistors and a gated capacitor, connected in a manner such that a stored "1" switches the implanted resistor to a high impedance state, while a stored "0" maintains the resistor in a relatively low resistance state.
    Type: Grant
    Filed: June 29, 1976
    Date of Patent: January 24, 1978
    Assignee: Texas Instruments Incorporated
    Inventors: G. R. Mohan Rao, Gerald R. Rogers, David J. McElroy
  • Patent number: 4064495
    Abstract: A non-volatile archival memory storage media has a planar junction diode structure into which are written a plurality of diode bits permanently formed at or beneath the top surface thereof by selective ion implantation. Each of the plurality of ion implanted regions represents a data bit of a first binary value, with the remaining un-implanted regions of the planar diode representing data bits of the remaining binary value. The permanently stored data is read by inducing a flow of current by recombination phenomena responsive to a scanning electron beam sequentially incident on each of the possible data bit sites of an array of such sites in the planar diode. Wide bandwidth methods for writing the ion implantation sites into the planar diode media are disclosed.
    Type: Grant
    Filed: March 22, 1976
    Date of Patent: December 20, 1977
    Assignee: General Electric Company
    Inventors: Conilee G. Kirkpatrick, James F. Norton, George E. Possin
  • Patent number: 4059826
    Abstract: N-channel silicon gate MOS memory cells are programmed by an ion implant step which is done prior to forming the gates or the diffused source and drain regions. The implanted devices have a threshold voltage which is about zero, so the devices cannot be turned off at usual logic levels. Either ROM or RAM arrays can be made using implant for programming.
    Type: Grant
    Filed: December 29, 1975
    Date of Patent: November 22, 1977
    Assignee: Texas Instruments Incorporated
    Inventor: Gerald D. Rogers