Abstract: A semiconductor memory device includes a plurality of static-type memory cells connected to pairs of word lines, each word line pair being composed of a word line having a high potential and a word line having a low potential, and a plurality of word-line discharging circuits, each being connected to one of the word line pairs. Each of the word-line discharging circuits includes, a thyristor whose anode is connected, via a voltage level shifter, to a word line having a high potential and whose cathode is connected to a constant-current source or a constant-voltage source. The thyristor comprises a PNP transistor and an NPN transistor. The NPN transistor can be a multi-emitter transistor or a multi-collector transistor whose second emitter or collector is connected to a word line having a low potential.

Abstract: A fully selectable static memory cell formed in a single isolation region comprises a pair of word lines, an SCR latch including an NPN device and an associated parasitic PNP device connected between the word lines, and a pair of bit lines, each of which is connected to the NPN device and the PNP device either directly or through a Schottky diode or an additional transistor device.

Abstract: A read only memory comprised of a semiconductor substrate and an epitaxial semiconductor layer formed on the substrate and having the same conductivity type as the substrate and a lower impurity density than the substrate. A plurality of word lines are formed in the surface of the epitaxial layer and comprise regions of semiconductor material having a conductivity type opposite that of the substrate. The word lines have openings therethrough which are filled with the epitaxial layer material. Regions of semiconductor material having the same conductivity type as the substrate are formed in selected portions of the epitaxial layer material filling the openings through the word lines. A plurality of bit lines overlie and intersect the word lines and contact the regions of semiconductor material formed in the selected portions of the epitaxial layer material filling the openings of the word lines.

Abstract: In a semiconductor memory device of the type having PNPN elements for transferring checking and programming currents to a memory cell, and a trigger circuit for activating the PNPN elements at a predetermined potential, a voltage limiting circuit is provided to activate the PNPN elements prior to achieving the triggering potential so that large voltage spikes through the memory elements during the memory checking operation can be prevented.

Abstract: In accordance with this invention, a dynamic RAM cell comprises a substrate of one conductivity type in which is formed a first region of a second and opposite conductivity type and a first pocket of this second conductivity type. The first pocket has formed therein a second pocket of the same conductivity type as the substrate but of a higher doping concentration than the substrate. By forming a channel between the first region and the first pocket, the charge in this first pocket can be controlled to represent a selected bit of information. The magnitude of charge stored in this first pocket can then be determined by forming a channel across this first pocket to the second pocket from the substrate. The time rate of change of the potential in the second pocket then is representative of the stored charge of information in the first pocket due to the fact that the impedance of the channel formed across the first pocket is directly related to the amount of charge stored in the first pocket.

Abstract: A memory circuit comprising a memory cell for storing information, constituted of semiconductor circuit elements and the associated circuit elements, and a control input section provided on the input side of the memory cell for controlling the memory cell, constituted of transistor means and current control means, wherein one of ON and OFF states is selected and also held in accordance with more than two logic input signals supplied to the control input section and no power is consumed to hold the OFF state.

Abstract: Semiconductor storage switching circuits and integrated circuit storage array devices that employ them are characterized by the fact that each individual cell of the storage array requires only a single active device, each such active device consisting of a three terminal, controlled-inversion device of metal, non-linear resistor, and semiconductor layers, the active device having controllable switching characteristics through the use of silicon dioxide, polycrystalline silicon, or nitrides of silicon in its non-linear resistive layer. Control circuits associated with the memory arrays make possible the unique selection of any one predetermined cell to write, erase, or read its content. Grounded base and grounded emitter forms of the storage devices are provided, as well as random access memory devices.

Abstract: A memory for non-volatile recording, lasting a long time, of fast signals. It comprises two storage stages:The first stage enables the input signal to be recorded by the production of depletion zones in a semiconductor;The second stage is formed by an MIIS type element whose charge is controlled by the extent of the preceding depletion zone, and ensures long recording of the signal.

Abstract: A memory for the non-volatile, long recording of fast signals. It is formed by two memory stages:A first stage, containing in particular a capacitor (C) and a diode (D), which records the input signal (V.sub.s) by charge accumulation for a time long enough for the signal to be transferred to the second stage;A second stage, formed by an MIIS type element (E), which ensures a non-volatile, long recording of these charges and, hence, of the signal V.sub.s.

Abstract: A nonvolatile (MNOS) memory array using varactor boosted select signals is disclosed. The memory utilizes a varactor circuit to boost the row select during the erase and write modes of operation.

Abstract: A memory circuit is comprised of a memory cell of PNPN- equivalent 4-layer construction, a selective input circuit composed of a pair of an NPN transistor and a PNP transistor, and a read-out circuit for reading the information stored in the memory cell. The emitters of the transistors included in the selective input circuit are connected to one of the selective input terminals, the bases thereof to the other selective input terminal, the collector of one of the transistors to the write input terminal of the memory cell, and the collector of the other transistor to the input terminal of the read-out circuit. Thus, both the writing and reading operations are controlled from the same selective input terminal, and power consumption of the selective input circuit in the holding mode is substantially zero.