Abstract: A non-volatile storage system is configured to reclaim bad blocks. One embodiment includes determining that a block of non-volatile memory cells is a bad block, leaving the block idle for a period of time to allow for self-curing of the block, verifying success of the self-curing, refreshing the block, verifying that the refresh was successful and subsequently using the block to store host data.

Abstract: A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period.

Abstract: A non-volatile storage system is configured to reclaim bad blocks. One embodiment includes determining that a block of non-volatile memory cells is a bad block, leaving the block idle for a period of time to allow for self-curing of the block, verifying success of the self-curing, refreshing the block, verifying that the refresh was successful and subsequently using the block to store host data.

Abstract: Provided herein may be a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, control logic, a status storage unit, and an operating characteristic checking unit. The memory cell array may include memory cells. The peripheral circuit may perform an operation for writing data to the memory cell array, reading data from the memory cell array, or erasing data written to the memory cell array. The control logic may control the peripheral circuit so that a data write operation, a data read operation or a data erase operation is performed. The status storage unit may store an operational status of the memory cell array as a first status value. The operating characteristic checking unit may receive an operating characteristic value, and generate a second status value via a comparison with an operation threshold value.

Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

Abstract: According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality of second conducting layer, and an electric charge accumulating layer. The first conducting layer is disposed on the semiconductor substrate via an insulating layer. The semiconductor layer is disposed on the first conducting layer and extends in a first direction above the semiconductor substrate. The plurality of the second conducting layers extends in a second direction intersecting with the first direction, and is laminated along the first direction via an insulating layer, and is disposed on the first conducting layer. The electric charge accumulating layer is disposed between the semiconductor layer and the plurality of second conducting layer. The semiconductor substrate includes an n type semiconductor region facing an end portion of the semiconductor layer.

Abstract: Attributing consumed storage capacity among entities storing data in a storage array includes: identifying a data object stored in the storage array and shared by a plurality of entities, where the data object occupies an amount of storage capacity of the storage array; and attributing to each entity a fractional portion of the amount of storage capacity occupied by the data object.

Abstract: A memory system may include: a memory device including a plurality of memory blocks each memory block having a plurality of pages; and a controller suitable for performing a plurality of operations to first memory blocks among the memory blocks at a first time, recording a checkpoint information for the operations in the memory blocks, selecting second memory blocks among the first memory blocks through the checkpoint information at a second time after a power-off in the memory system while performing the operations, and performing a dummy write operation to the second memory blocks.

Abstract: The present invention discloses a CNFET double-edge pulse JKL flip-flop, comprising a double-edge pulse signal generator, 31 CNFET tubes, 6 NTI gate circuits having the same circuit structure, 6 PTI gate circuits having the same circuit structure as well as the 1st and 2nd two-value inverters having the same circuit structure; it features in correct logic functions as well as high-speed and low power consumption.

Abstract: A nonvolatile memory including: a memory cell array including a plurality of nonvolatile memory cells; a decoder connected to the memory cell array through a plurality of word lines; a data input/output (I/O) circuit connected to the memory cell array through a plurality of bit lines; and control logic configured to control the decoder and the data I/O circuit in response to a change in a power supply voltage to clear or maintain individual pieces of page data. The control logic includes a page management unit that determines whether to clear data included in the individual pieces of page data based on a value of a set flag respectively corresponding to the individual pieces of page data.

Abstract: A structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode connected to the word-line, a first gate dielectric underlying the first gate electrode, a drain region connected to the bit-line, and a source region. The first gate dielectric has a first thickness. The drain region and the source region are on opposite sides of the first gate electrode. The anti-fuse cell further includes a programming device including a second gate electrode connected to the word-line, and a second gate dielectric underlying the second gate electrode. The second gate dielectric has a second thickness smaller than the first thickness. The programming device further includes a source/drain region connected to the source region of the reading device.

Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage.

Abstract: A method for tracking and transitioning flash memory modes, performed by a storage system, is provided. The method includes tracking memory modes of a plurality of portions of flash memory, on a per portion basis, in a data structure in a first memory and determining, based on the data structure, whether the tracked memory mode of a portion of flash memory matches a memory mode for an I/O (input/output) command relating to the flash memory. The method includes sending at least one command to the flash memory to change the memory mode of the portion of flash memory, responsive to determining the tracked memory mode does not match the memory mode for the I/O command, and performing the I/O command with the memory mode of the portion of flash memory changed to match the memory mode for the I/O command.

Abstract: An applicator for applying a cosmetic make-up or cosmetic care product to the eyelashes and/or the eyebrows, said applicator comprising a rod and an application member at one end of the rod, the application member being produced by molding a material and comprising a non-twisted core extending along a longitudinal axis and application elements carried by the core and arranged in a plurality of helical rows about the longitudinal axis of the core, the application member having at least one helical strip extending over more than half a revolution about the longitudinal axis of the core, which strip is free of application elements and delimited by two consecutive helical rows of application elements extending parallel to each other, the gap between said two consecutive helical rows of application elements being greater than the average gap between the application elements within said helical rows.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for program sequencing. An apparatus includes a block of non-volatile storage cells having a plurality of word lines. The word lines are organized into a monotonically increasing sequence. The apparatus includes a controller for the block. The controller is configured to program a set of storage cells of a word line to one or more storage states above a predetermined threshold and to program a set of storage cells of a previous word line adjacent to and before the word line in the sequence, to one or more storage states below the predetermined threshold after programming the set or storage cells of the word line to the one or more storage states above the predetermined threshold.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a global line pair including a global bit line and a global source line; a plurality of cell matrices coupled between the global bit line and the global source line, each cell matrix including a plurality of local line pairs and a plurality of storage cells that are coupled to the plurality of local line pairs, wherein each storage cell is operable to store data and is coupled between local lines of a corresponding local line pair; and a plurality of isolation switch pairs that couple the plurality of cell matrices to the global bit line and the global source line of the global line pair, one isolation switch pair per cell matrix.

Abstract: According to one embodiment, in a memory system, a controller is configured to write first data in a page in a block in response to a write request from a host, and update second information used to manage a correspondence between a logical address designated by the write request and a second physical address which is a storage location in the first memory. The controller is configured to perform a first process of updating the first information with the second information and storing the updated information in the first memory. The controller is configured to acquire the first physical address associated to a logical address designated by the write request from the first information. The controller is configured to store, in the first memory, third information including information in which the acquired first physical address and the second physical address are associated.

Abstract: A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.

Abstract: Attributing consumed storage capacity among entities storing data in a storage array includes: identifying a data object stored in the storage array and shared by a plurality of entities, where the data object occupies an amount of storage capacity of the storage array; and attributing to each entity a fractional portion of the amount of storage capacity occupied by the data object.

Abstract: A method for starting up electric or electronic devices, in particular devices in or for an aircraft or spacecraft, including: supplying at least one location identification which contains at least one piece of information about the location of a respective device; detecting a supplied location identification for one device in each case; transmitting the detected location identification to the respective device; and parameterizing the respective device by means of the transmitted location identification. The present invention also provides a start-up apparatus, a server system and a system.

Abstract: A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on.

Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.

Abstract: A storage device and method for enabling hidden functionality are provided. In one embodiment, a storage device is provided comprising an interface a memory, and a controller. The controller is configured to receive a series of read and/or write commands to the memory from the host device. If the series of read and/or write commands received from the host device matches an expected pattern of read and/or write commands, irrespective what data is being read or written by those commands, the controller enables a special functionality mode of the storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Abstract: Aspects of the invention relate to test access architecture for stacked memory and logic dies. A test access interface for a logic die that is stacked under a memory die is disclosed. The disclosed test access interface can control testing logic core, interconnections with the memory die and with another logic die. The controlling of testing interconnections with the memory die is through a memory boundary scan register controller in the test access interface.

Abstract: A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After that, the memory copies the data from the third data latch to a third word line. In another embodiment, a storage module is provided comprising a memory and an on-chip copy gather module. Other embodiments are provided.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: Embodiments extend the relational model and query language to recognize features of tables and higher level entity-relationship models (ERMs). Extension language is implemented in the data design language (DDL) to incorporate tables, entities (and views) having custom-defined/semantic structure, rather than being limited to primitive types (e.g. flat tables as in standard SQL). The extension language includes an indication that a query is to include all active elements for each table extension or entity extension that is active. The extension language can be chained to extend a table or entity that has been extended.

Abstract: Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.

Abstract: Exposing a geometry of a storage device, including: sending, by the storage device, information describing the layout of memory in the storage device; receiving, by the storage device, a write request, the write request associated with an amount of data sized in dependence upon the layout of memory in the storage device; and writing, by the storage device, the data to a memory unit, the data written to a location within the memory unit in dependence upon the layout of memory in the storage device.

Abstract: A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate. The first material layers include a plurality of control gate electrodes and the second material layers include an insulating material and the plurality of control gate electrodes extend in a first direction. The NAND string also includes a semiconductor channel, a blocking dielectric, and a plurality of vertically spaced apart floating gates. Each of the plurality of vertically spaced apart floating gates or each of the second material layers includes a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness.

Abstract: A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.

Abstract: Methods, systems, and devices related to memory, including read or write performance of a phase change memory, are described. A plurality of memory cells of a memory array may be read. A total number of read errors resulting from the read operation of the plurality of memory cells may be determined, and reference read currents may be adjusted if the total number of read errors exceeds an error threshold. In some examples, adjusting reference read currents includes reading a reference memory cell, determining a current shift for the reference memory cell, and adjusting read currents for other memory cells of the memory array by a current delta based at least in part on the current shift.

Abstract: The present invention discloses a memory card access device, the control method thereof and a memory card access system. Said device comprises: a memory card interface circuit to generate card-read data according to a card-read signal or generate a card-writing signal according to card-writing data; a host interface circuit to generate host-read data according to a host-read signal or generate the host-writing signal according to host-writing data; and a control circuit, coupled to the memory card and host interface circuits respectively, operable to generate the host-writing data by processing the card-read data according to a predetermined cache protocol or generating the card-writing data by processing the host-read data according to the predetermined cache protocol, so as to treat a memory card as a cache device.

Abstract: A device includes a cell array including cells. A sense node transmits logic of data stored in the cell selected by a WL and a BL. A verify read in a data program sequence includes a first read and a second read. In a time period of shifting from the first read to the second read, a charge state of the sense node is maintained.

Abstract: Provided is a semiconductor device. The semiconductor device includes memory blocks including select transistors electrically coupled to local select lines and memory cells electrically coupled to local word lines, a first connection circuit configured to electrically couple the local select lines of a selected memory block and global select lines according to a block select signal, and formed in a first well region of a substrate, and a second connection circuit configured to electrically couple the local word lines of the selected memory block and global word lines according to the block selection signal, and formed in a second well region of the substrate.

Abstract: A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (Cv) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I1, I2) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (Vx) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract: The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Abstract: Word lines are formed from a stack of layers that includes a metal (e.g. tungsten) layer with an overlying multi-layer cap structure. The multi-layer cap structure includes a layer with a low etch rate to protect metal from damage during anisotropic etching. The multi-layer cap structure includes a layer with stress (e.g. tensile) that is opposite to the stress of the metal (e.g. compressive) to provide low combined stress.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The non-volatile memory includes a memory cell array and an access control unit. The access control unit performs a program operation for changing threshold voltages of memory cells and a read operation for reading data from the memory cells. The memory controller includes a read/write control unit having a first program parameter set and a second program parameter set. The read/write control unit causes the access control unit to perform a program operation based on the first program parameter set, and when a predetermined condition is satisfied, performs switching from the first program parameter set to the second program parameter set and causes the access control unit to perform a program operation based on the second program parameter set.

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.