Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Abstract: A method and a circuit for controlling the access to at least one resource of an electronic circuit, in which a test of the value of a counter over at least one bit conditions the access to the resource, the counter being automatically reset after a time period independent from whether the circuit is powered or not.

Abstract: A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge operations may include an erase operation in which the storage devices are erased, a sanitization operation in which a pattern is written to the storage devices, and/or a destroy operation in which the storage devices are physically damaged via application of a high voltage. The command set preferably enables the host system to specify how many of the storage devices are to be purged at a time during a purge operation. The host system can thereby control the amount of time, and the current level, needed to complete the purge operation. In some embodiments, the number of storage devices that are purged at a time may additionally or alternatively be selectable by a controller of the storage system.

Abstract: A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.

Abstract: A circuit arrangement having complementary data lines of a dual rail data bus, wherein in a regular operating phase the complementary data lines carry complementary signals, and in a precharge phase the complementary data lines assume an identical logic state or the same electrical potential. The circuit arrangement also has a device for detecting manipulation attempts, the device having a detector circuit, which outputs an alarm signal upon the occurrence of an identical logic state on both data lines in the regular operating phase.

Abstract: Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it loses its power connection to the host system.

Abstract: A semiconductor device includes a first memory unit, a second memory unit, and a determination unit receiving a first signal permitting a write operation to one of the first memory unit and the second memory unit, and a second signal indicating whether the write operation of information to the first memory unit is finished, wherein the determination unit outputs a signal prohibiting a write operation to the second memory unit, if the second signal indicates the write operation of the information is finished.

Abstract: A method and a circuit for protecting data contained in an electronic circuit against a disturbance of its operation, in which a detection of a disturbance conditions the incrementing or the decrementing of a counter over at least one bit, the counter being automatically reset at the end of a time period independent from the fact that the circuit is or not powered.

Abstract: A method and a circuit for protecting at least one piece of information contained in an electronic circuit by disabling at least one function of the circuit in case of detection of a number of abnormal operations greater than a threshold, in which the disabling of the function is temporary, of a duration independent from whether the circuit is powered or not.

Abstract: The present invention relates to an apparatus and method for easily, quickly and permanently decommissioning an electronic data storage device by thoroughly exposing the device to a strong field of microwave energy thereby eliminating any possibility of retrieving data from the device. The magnetron is operated as peak power and pulsed for the time needed to assure data destruction.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Abstract: Some embodiments of the present invention provide a memory device including a first memory array having a first word line and a comparator circuit having a first terminal coupled to a reference voltage and a second terminal coupled to a first switch selectively coupling the first word line to a power source or the second terminal. In an embodiment, the reference voltage is selected for identifying a leakage condition associated with the first word line. In another embodiment, the first switch is configured to couple the first word line to the power source for a first predetermined period of time to allow charging of the first word line. In another embodiment, the first switch is configured to couple the first word line to the second terminal of the comparator for at least a second predetermined period of time.

Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.

Abstract: A nonvolatile memory having a non-power of two memory capacity is provided. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device.

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Abstract: Systems and methods to control one time programmable (OTP) memory are included. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.

Abstract: A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The input/output module may be in electrical communication with the input/output device (e.g., electrically coupled) and/or signal communication with the input/output device (e.g., wireless and/or optical communication).

Abstract: Various data protection techniques are provided. In one embodiment, a method includes manufacturing a memory component of an electronic system. Manufacturing the memory component may include disposing a memory array on a substrate and coupling a control circuit to the memory array. The control circuit may be configured to selectively prevent access to data stored within the memory array upon removal of the memory component from the electronic system. Various additional methods, devices, and systems are also provided.

Abstract: Securing an integrated circuit, including fabricating the integrated circuit to include a multiplicity of unblown efuses, at least one surrogate efuse that emulates a blown efuse, non-volatile data representing the blown state of the surrogate efuse, and security circuitry; and setting, by the security circuitry when power is first applied to the integrated circuit, a security state of the integrated circuit in dependence upon whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse.

Abstract: Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.

Abstract: A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period.

Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Abstract: A system includes a volatile storage, a persistent storage, a capacitor-based power supply, and a controller coupled to the capacitor-based power supply. The controller detects interruption of main power, and in response to detecting the interruption of main power, begins backup copying of data from the volatile storage to the persistent storage. After beginning the backup copying of data, the controller checks whether the main power has resumed prior to depletion of the capacitor-based power supply. In response to detecting that main power has resumed prior to depletion of the capacitor-based power supply, the controller resumes operation using content of the volatile storage without restoring data from the persistent storage.

Abstract: A method and apparatus for automatically securing non-volatile (NV) storage in an integrated circuit provides improved resistance to code copying and reverse-engineering attacks. External interfaces that provide read access to the NV storage are be disabled, for a predetermined time after a reset or other initialization signal is received. An internal lock state bit or key is checked as well as an external lock prevent indication. If the lock prevent indication is not received, or the internal lock state bit is already set, then the integrated circuit is operated under a locked condition, in which external access to the NV storage values is prevented. The lock prevent indication may be a signal provided during reset of the integrated circuit on a terminal that is used for another purpose after initialization of the integrated circuit.

Abstract: Techniques are described to monitor charging of an integrated circuit during manufacturing processes. In one example, an integrated circuit includes first and second pads adapted to be charged by charge carriers during manufacture of the integrated circuit. The integrated circuit also includes a reference nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate is coupled to the first pad. The integrated circuit further includes a charging protection device coupled to the control gate of the reference memory cell and adapted to limit the gate voltage of the control gate induced by the charge carriers. In addition, the integrated circuit includes a charging monitor nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate is coupled to the second pad but not to a charging protection device adapted to limit the gate voltage of the control gate.

Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1?, D1?) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.

Abstract: An information storage arrangement that combines higher-endurance (or performance) storage with lower-endurance (or performance) storage is managed in a manner that makes judicious use of the lower-endurance (or performance) storage. It is therefore possible to exploit the economic advantage associated with lower-endurance (or performance) storage, while also avoiding storage capacity losses that would otherwise be associated with lower-endurance (or performance) storage.

Abstract: Methods and devices are disclosed herein to provide improved techniques for securing configuration data stored in non-volatile memories of programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a plurality of configuration data. A plurality of security fuses are adapted to store a plurality of logic states. Control logic is adapted to selectively secure the configuration data within the non-volatile memory based on the logic states stored in the plurality of security fuses.

Abstract: A memory cell array has a first and a second storage area. The first storage area has a memory element selected by an address signal. The second storage area has a memory element selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Abstract: A flash memory device and a related method of write protecting data are disclosed. The flash memory device includes a protection controller having a latch circuit storing temporary protected/accessible data, a cell array storing persistent protected/accessible data, a write controller altering the persistent protected/accessible data, and a latch controller altering the temporary protected/accessible data.

Abstract: A system for providing a pre-programmed integrated circuit including programmable logic, and method for providing same. The system includes: nonvolatile memory capable of having first data stored therein and an integrated circuit coupled with the nonvolatile memory. The first data is associated with a predetermined design, and the integrated circuit includes programmable logic having a user region and a reserved region. The integrated circuit is configured to obtain the first data from the nonvolatile memory for instantiation of the predetermined design in the reserved region.

Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it looses its power connection to the host system.

Abstract: A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits, a suspend pin coupled to receive a suspend signal, a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal; and an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode.

Abstract: In a SIM card having a flash memory chip, a memory controller chip, and contact/contactless card interfaces, the memory controller chip has a function of executing user authentication of a host equipment, executes processing of data transmitted through the contactless IC card interface (executing reading or writing of data to the flash memory chip) using power supplied from the host equipment to the contact IC card interface, and executes initialization of the flash memory chip between activation of the host equipment and completion of user authentication instructed by the host equipment.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state.

Abstract: The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.

Abstract: A data storage includes a part of functioning for, when data reading operation is carried out on a storage part storing data for a case where the data storage is handled in a predetermined manner, causing predetermined data different from target data to be read out instead of the target data.

Abstract: A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period.

Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it looses its power connection to the host system.

Abstract: When a first reset signal is inputted, the reset control section outputs a second reset signal and an input/output control signal. The second reset signal is at a first logical level, and switches to a second logical level after a first period has passed. The input/output control signal is activated for a second period, before the first period has passed. The input/output port is connected with a controlled device and a mode identification signal generation unit which generates a mode identification signal corresponding to the controlled device. The input/output port functions as an input port only in the second period, to which the mode identification signal is inputted, and functions as an output port outside in the second period. The access control section implements switching of the operation mode and implements control of access to the controlled device on the basis of the mode identification signal from the input/output port.

Abstract: A two-step matching technique is embodied in a video-copy-detection algorithm that detects copies of video sequences. The two-step matching technique uses ordinal signatures of frame partitions and their differences from partition mean values. The algorithm of this invention is not only robust to intensity/color variations it can also effectively handle various format conversions, thereby providing robustness regardless of the video dynamics of the frame shots.

Abstract: Securing an integrated circuit, including fabricating the integrated circuit so that the integrated circuit includes at least one efuse that is intended to be always blown during operation of the integrated circuit and the integrated circuit includes security circuitry capable of blowing the efuse and of performing other security related functions; blowing, by the security circuitry of the integrated circuit, the efuse when power is applied to the integrated circuit and prior to performing any other security related functions; and setting, by the security circuitry after blowing the efuse, a security state of the integrated circuit in dependence upon a sensed state of the efuse.

Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.

Abstract: A memory cell comprising an electrically floating body transistor including a source region, a drain region, a body region disposed therebetween, wherein the body region is electrically floating, and a gate disposed over the body region and separated therefrom by a gate dielectric. The memory cell includes a first data state representative of a first charge in the body region and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing carriers from the body region through the gate. Thus, a memory cell may be programmed to a logic low by, for example, causing, forcing and/or inducing carriers in the floating body of the transistor to tunnel through or traverse the gate dielectric to the gate of the electrically floating body transistor (and, in many array configurations, the word line of a memory cell array).

Abstract: Memory cell can stores a multi-valued value more than a binary value in a single storage cell by changing the amount of electric charge to be stored. Data logic stores storage data, each digit of which is binary as a binary value in each memory cell for each digit. Furthermore, the data logic determines whether a read request for storage data is legal. If the read request is legal, the data logic relates the amount of electric charge stored in the memory cell to a binary value. If it is illegal, the data logic relates the amount of electric charge stored in the memory cell to the above-mentioned multi-valued value. Then, the data logic outputs data obtained by arraying the related values in each digit as the requested storage data.

Abstract: A method for operating a memory device is disclosed. In one embodiment, the method includes receiving authorized operating parameters of the memory device and comparing sensed operational parameters to the authorized operating parameters. Access to data stored within the memory device may be prevented if the operational parameters are outside the authorized operating parameters. A memory device and method of manufacturing such a device are also provided.

Abstract: A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer.