Particular Connection Patents (Class 365/185.05)
  • Patent number: 10367001
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10354736
    Abstract: The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an uncertainty prediction circuit coupled to the memory cells, and a data conversion circuit coupled to the memory cells. The uncertainty prediction circuit is configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state. The data conversion circuit is configured to apply a data conversion to a portion of data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Pitamber Shukla
  • Patent number: 10312248
    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 4, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
  • Patent number: 10310972
    Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 4, 2019
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Yong Ju Kim, Do Sun Hong
  • Patent number: 10304541
    Abstract: A memory device includes a memory cell array including a first switch cell, a second switch cell, and a plurality of memory cells disposed between the first the second switch cells and connected to a plurality of word lines, and a control circuit configured to perform a program operation by providing a program voltage to a first word line among the plurality of word lines, a switch voltage to a second word line among the plurality of word lines, and a pass voltage to remaining word lines among the plurality of word lines, wherein the control circuit is configured to turn off the first switch cell and the second switch cell in a first section of the program operation, and configured to turn on the first switch cell and increase the switch voltage in a second section of the program operation later than the first section.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Gyung Hwang, Byoung Taek Kim, Yong Seok Kim, Ju Seok Lee
  • Patent number: 10285274
    Abstract: A circuit structure is provided to which an electronic component can be easily mounted (electrical connection of terminals). A circuit structure that includes a substrate provided with a conductive pattern on one face thereof; a conductive member fixed to the other face of the substrate; an electronic component that has first terminals and of a plurality of terminals, that are electrically connected to the conductive member, and a second terminal of the plurality of terminals that is electrically connected to the conductive pattern provided on the substrate; and a relay member for electrically connecting the second terminal and the conductive pattern provided on the substrate, at least a portion of the relay member being fixed to the conductive member via an insulating material.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: May 7, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Arinobu Nakamura, Tou Chin
  • Patent number: 10269435
    Abstract: A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells is decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 10262975
    Abstract: A system can include a first semiconductor device including a first capacitor with a first terminal coupled to receive a power supply potential; and a second semiconductor device including a first voltage generator coupled to the first terminal of the first capacitor, the first voltage generator provides a first voltage generator output potential at an output terminal. The first capacitor can include a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include at least one substantially vertically formed conductive portion in a substrate of the first semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node is electrically connected to the first terminal of the first capacitor.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: April 16, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10263002
    Abstract: In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 16, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Hideo Kasai, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Kosuke Okuyama
  • Patent number: 10262976
    Abstract: A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. A first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate, separated from one another by at least one capacitor dielectric. A first capacitor node can be electrically connected to the first terminal of the first capacitor. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The at least one essentially vertically formed conductive portion can comprise polysilicon.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: April 16, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10242997
    Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Min Choi, Ju-Young Lim, Su-Jin Ahn
  • Patent number: 10223255
    Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: March 5, 2019
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Yong Ju Kim, Do Sun Hong
  • Patent number: 10211259
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Oga, Mutsumi Okajima, Natsuki Fukuda, Takeshi Yamaguchi, Toshiharu Tanaka, Hiroyuki Ode
  • Patent number: 10199387
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Patent number: 10199104
    Abstract: A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: February 5, 2019
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 10192875
    Abstract: A non-volatile memory including following elements is provided. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor. The stress-releasing transistor has a stress release ratio represented by formula (1). A lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed. An upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed. The stress release ratio=a channel length of the stress-releasing transistor/a gate dielectric layer thickness of the stress-releasing transistor??(1).
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: January 29, 2019
    Assignee: eMemory Technology Inc.
    Inventor: Te-Hsun Hsu
  • Patent number: 10177121
    Abstract: A system can include a first semiconductor device, a second semiconductor device and a first semiconductor memory device. The first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate. The first capacitor node can be coupled to receive a power supply potential. At least one conductive data path is coupled between the first semiconductor memory device and the second semiconductor device.
    Type: Grant
    Filed: September 15, 2018
    Date of Patent: January 8, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10170488
    Abstract: A semiconductor device includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, a first floating gate structure, a second floating gate structure, a first word line, a common source, a second word line, a first spacer and a second spacer. The first floating gate structure and the second floating gate structure are recessed in the substrate at two opposite sides of the erase gate structure. The first word line and the second word line are respectively adjacent to the first floating gate structure and the second floating gate structure. The common source is disposed in the substrate under the erase gate structure. The first spacer and the second spacer are respectively disposed between the first floating gate structure and the first word line and between the second floating gate structure and the second word line.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANFACTURING CO., LTD.
    Inventors: Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 10163514
    Abstract: Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage while applying the first voltage to a second access line, the first access line coupled to a target memory cell of the programming operation and an unselected memory cell not targeted for the programming operation, and the second access line coupled to memory cells not targeted for the programming operation. After increasing the voltage applied to the first access line, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage and increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage and lower than the third voltage.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Yogesh Luthra, Kim-Fung Chan, Xiaojiang Guo
  • Patent number: 10163928
    Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10157674
    Abstract: A soft erase method of a memory device including applying a program voltage to a first memory cell in at least one of program loops when a plurality of program loops are performed to program the first memory cell into a Nth programming state, wherein the first memory cell is included in a selected memory cell string connected to a selected first bit line and is connected to a selected word line; and soft erasing a second memory cell by applying, in a first verification interval, a read voltage for verifying a programming state of the first memory cell to the selected word line and applying a first prepulse to a gate of a string select transistor of each of a plurality of unselected memory cell strings connected to the first bin line and a plurality of unselected memory cell strings connected to an unselected second bit line.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 18, 2018
    Assignee: Samsung Electronics. Co., Ltd.
    Inventors: Doo-hyun Kim, Il-han Park, Jong-hoon Lee
  • Patent number: 10134485
    Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device outputs address signals. The first semiconductor device may receive or output data. The second semiconductor device may perform an impedance calibration operation and outputs pull-up codes and pull-down codes generated by the impedance calibration operation. The third semiconductor device may output internal data selected by the address signals as the data or store the data during a write operation or a read operation.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae Il Kim
  • Patent number: 10121546
    Abstract: When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device and a second storage device to have threshold voltages, respectively, both increased, and the control circuit thereafter controls performing an erase process to allow the first storage device and the second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit has received a second erase command, the control circuit controls performing a second pre-write process to allow one of the first storage device and the second storage device to have its threshold voltage increased, and control circuit subsequently controls performing the erase process.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Kunio Tani
  • Patent number: 10115710
    Abstract: A package can include a number of stacked dynamic random access memory (DRAM) semiconductor devices and an interposer. Wirings can be formed in the interposer to provide electric connections essentially orthogonal between the first and second surfaces of the interposer to external connections. Through vias can provide electrical connections between surfaces of the DRAM semiconductor devices, and interface connections can provide electrical connections between through vias of adjacent DRAM semiconductor devices. External connections can receive a power supply potential and a data signal.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 30, 2018
    Inventor: Darryl G. Walker
  • Patent number: 10115440
    Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Qui Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Jason Li, Tai-Yuan Tseng, Jong Yuh
  • Patent number: 10096614
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10090067
    Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 2, 2018
    Assignee: Seagate Technology LLC
    Inventors: Timothy Canepa, Mark Ish, David S. Ebsen
  • Patent number: 10079064
    Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string, and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Aaron Yip
  • Patent number: 10074661
    Abstract: Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: September 11, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Yusuke Ikawa
  • Patent number: 10073982
    Abstract: A scramble unit subjects data to be written into twin cells in a first storage unit to scramble processing with the use of scramble data. A write unit writes write data subjected to the scramble processing into the twin cells in the first storage unit. A write unit writes scramble data into a memory cell in a second storage unit. A descramble unit subjects the data read from the first storage unit to descramble processing with the use of scramble data read from the second storage unit.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Seiji Sawada
  • Patent number: 10074430
    Abstract: Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10074434
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: September 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Patent number: 10068916
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Yoshihisa Iwata
  • Patent number: 10056403
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: August 21, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Patent number: 10056907
    Abstract: A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: August 21, 2018
    Assignee: CROSSBAR, INC.
    Inventors: Mehdi Asnaashari, Hagop Nazarian, Sang Nguyen
  • Patent number: 10049742
    Abstract: A shared floating gate device, the device including an nFET including an nFET gate dielectric, a pFET including a pFET gate dielectric, and a floating gate, where the nFET and the pFET are connected in parallel and share the floating gate.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tak Ning, Jeng-Bang Yau
  • Patent number: 10026493
    Abstract: Described herein is a ROM architecture featuring a ROM bitcell without a transistor, a ROM architecture wherein the bitcell device gate goes to a column address and the local bitline is sensed per row per mux, a ROM architecture wherein the bitcell device gate goes to the column address and the full row of bitcells is enabled by a row enable signal, and a ROM architecture wherein the bitcell device gate goes to the row address and the full column of bitcells is enabled by a column enable signal. The presently described architectures provide large advantages in terms of PPA.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 17, 2018
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Patent number: 10020056
    Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10008280
    Abstract: Described herein is a ROM architecture featuring a ROM bitcell without a transistor, a ROM architecture wherein the bitcell device gate goes to a column address and the local bitline is sensed per row per mux, a ROM architecture wherein the bitcell device gate goes to the column address and the full row of bitcells is enabled by a row enable signal, and a ROM architecture wherein the bitcell device gate goes to the row address and the full column of bitcells is enabled by a column enable signal. The presently described architectures provide large advantages in terms of PPA.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 26, 2018
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Patent number: 10001963
    Abstract: A dynamic random access memory, including a main body, a processing unit, a display screen and a transmit port. The main body has a substrate and a shell portion disposed by two opposite side faces of the substrate, the substrate is provided with a memory module; the processing unit is disposed in the main body; the display screen is attached to the main body and viewable from outside of the dynamic random access memory, the display screen is electrically connected with the processing unit, the processing unit can control a display state of the display screen; and the transmit port is disposed on the substrate, and the transmit port is electrically connected with the memory module.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 19, 2018
    Assignee: Alson Technology Limited
    Inventors: Han-Hung Cheng, Chi-Fen Kuo
  • Patent number: 9997250
    Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventors: Kang-Woo Park, Eun-Ji Choi
  • Patent number: 9991226
    Abstract: A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: June 5, 2018
    Assignee: SK hynix Inc.
    Inventor: Jin Kyoung Park
  • Patent number: 9978454
    Abstract: A nonvolatile memory includes a plurality of memory blocks and an address decoder. The address decoder is configured to activate a block word line corresponding to the memory blocks in common when one memory block is selected among the memory blocks, supply voltages to word lines of the selected memory block among the memory blocks, and float word lines of an unselected memory block among the memory blocks.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won-Taeck Jung
  • Patent number: 9972632
    Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 15, 2018
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chunming Wang, Nhan Do
  • Patent number: 9966148
    Abstract: A data storage device includes a nonvolatile memory device including word lines each including one or more pages; and a controller suitable for, in the case where recovery is made to a normal state from a power-off state, searching a word line including an erased page among the word lines, and selecting, when all pages of the word line including the erased page are erased pages, the corresponding word line as a reliability verification word line.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 8, 2018
    Assignee: SK Hynix Inc.
    Inventor: Min Kee Kim
  • Patent number: 9947677
    Abstract: A memory array includes an N×M array of memory cells, each memory cell having a first transistor connected to a first terminal and a second transistor connected in parallel to the first transistor and a second terminal, where the first and second transistors share a common floating gate and a common output node. Each memory cell further includes an access transistor connected in series to the common output node and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate. The first transistor is an n-type transistor and the second transistor is a p-type transistor.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning, Jeng-bang Yau
  • Patent number: 9929127
    Abstract: A package can include first, second, and third dynamic random access memory (DRAM) semiconductor devices having first, second and third through vias, respectively, and stacked above an interposer. First, second, and third interface connections can be formed between the DRAM semiconductor devices. A first wiring of the interposer can be connected at a central portion of a first external connection that receives a first power supply potential. A second wiring of the interposer can be connected to a second external connection that receives a first data signal.
    Type: Grant
    Filed: December 9, 2017
    Date of Patent: March 27, 2018
    Inventor: Darryl G. Walker
  • Patent number: 9927993
    Abstract: A semiconductor memory device includes a memory cell array including a block of memory cells, gates of which are connected to a plurality of word lines, and a control unit configured to perform a writing operation in response to a command received from the outside, the writing operation including applying a program level voltage to at least two word lines at the same time.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: March 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yusuke Ochi, Masanobu Shirakawa
  • Patent number: 9928885
    Abstract: A nonvolatile memory device may include a nonvolatile memory device may include a nonvolatile memory cell array; a peripheral circuit suitable for: activating an operation voltage in response to an operation voltage activation command, performing an operation to the nonvolatile memory cell array using the activated operation voltage in response to an operation command, and deactivating the activated operation voltage in response to an operation voltage deactivation command after the performing of the operation; and a control circuit suitable for controlling the peripheral circuit to execute an intervening operation during the activating of the operation voltage, the performing of the operation, and the deactivating of the activated operation voltage.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: March 27, 2018
    Assignee: SK Hynix Inc.
    Inventor: Sung-Hyun Jung
  • Patent number: 9922712
    Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
    Type: Grant
    Filed: February 19, 2017
    Date of Patent: March 20, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Julien Delalleau