Particular Connection Patents (Class 365/185.05)
  • Patent number: 11176989
    Abstract: A semiconductor memory device includes a plurality of bit lines extending in a first direction, and arranged in a second direction intersecting with the first direction, a page buffer high-voltage circuit divided into a plurality of page buffer high-voltage regions arranged in the first direction, each of the plurality of page buffer high-voltage regions including a plurality of page buffer high-voltage elements, each page buffer high-voltage element coupled to one of the plurality of bit lines, and a contact pad unit including a plurality of contact pads, each contact pad coupled to one of the plurality of page buffer high-voltage elements. The contact pad unit is arranged, in the first direction, between two of the plurality of page buffer high-voltage regions.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Sung Lae Oh
  • Patent number: 11127717
    Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 21, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Tomoya Sanuki
  • Patent number: 11127460
    Abstract: Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 21, 2021
    Assignee: Crossbar, Inc.
    Inventors: Mehdi Asnaashari, Hagop Nazarian, Christophe Sucur, Sylvain Dubois
  • Patent number: 11107511
    Abstract: A CAM device includes a cell array including a plurality of CAM cells, a search line driving circuit connected to the cell array through a plurality of search lines, and a match line sensing circuit connected to the cell array through a plurality of match lines. Each of the CAM cells includes a first half CAM cell connected to a first match line and a second half CAM cell connected to a second match line different from the first match line. The first match line connected to the first half CAM cell is precharged in a first phase, and the second match line connected to the second half CAM cell is precharged in a second phase after the first phase. Thus, power consumption of the CAM device is reduced and delay is minimized.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 31, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jongsun Park, Woong Choi, Geon Ko
  • Patent number: 11101798
    Abstract: A random bit cell includes a selection transistor, a first P-type transistor, and a second P-type transistor. The selection transistor has a first terminal coupled to a source line, a second terminal coupled to a common node, and a control terminal coupled to a word line. The first P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a floating gate. The second P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a floating gate. During an enroll operation, one of the first P-type transistor and the second P-type transistor is programmed by channel hot electron injection.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 24, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Ying-Je Chen, Wein-Town Sun, Wei-Ming Ku
  • Patent number: 11069704
    Abstract: A memory device comprises a plurality of stacks of bit lines alternating with insulating strips over an insulating layer on a substrate, and a plurality of vertical gate structures disposed between the stacks. Vertical channel structures and memory elements are disposed between outside surfaces of the vertical gate structures and sidewalls of insulating strips in the stacks of bit lines. The vertical channel structures provide channels between adjacent bit lines in the stacks. A plurality of word line transistors is disposed over and connected to respective vertical gate structures. A plurality of word lines is disposed over and connected to the word line transistors. The memory device comprises circuitry connected to the bit lines to apply bit line and source line voltages to the bit lines.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: July 20, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 11048552
    Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Anton Leyrer, William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide
  • Patent number: 11037953
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Bo Shim, Jung Dal Choi
  • Patent number: 10991422
    Abstract: High-efficiency control technology for non-volatile memory. A non-volatile memory has single level cells (SLCs) and multiple level cells (e.g., MLCs or TLCs) and is controlled by a controller. According to the controller at the device end, a host allocates a system memory to provide a host memory buffer (HMB). The controller at the device end uses the HMB to buffer write data issued by the host, and then flushes the write data from the HMB to multi-level cells of the non-volatile memory without passing single level cells of the non-volatile memory to reduce write amplification problems due to the frequent use of the single-level cells.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: April 27, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Ting Huang, Liang-Cheng Chen
  • Patent number: 10984864
    Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
  • Patent number: 10957399
    Abstract: A memory is disclosed. A memory cell comprises three gate structures sequentially arrayed between a first source-drain region and a second source-drain region. A first gate structure and a third gate structure are formed by superposition of a first gate dielectric layer, a floating gate, a second gate dielectric layer and a polysilicon control gate, so that two memory bits and two control gates are formed. A second gate structure is located between the first gate structure and the third gate structure and serves as a select gate. Erasing and programming operations on the two memory bits formed by the floating gates are realized by FN tunneling. During erasing and programming, the first source-drain region and the second source-drain region are grounded, so that the memory bits can be selected and then erased or programmed only by controlling voltages of the first control gate, the select gate and the second control gate. An operation method of a memory is further disclosed.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Guangjun Yang
  • Patent number: 10922020
    Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ameen D. Akel, Sean S. Eilert
  • Patent number: 10902918
    Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: January 26, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 10903327
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: January 26, 2021
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Patent number: 10885986
    Abstract: The disclosed technology teaches a memory device with memory cells, each with a sense circuit with an input node in current flow communication, a BLC transistor, a transfer transistor, a current source transistor, and an output circuit to generate data based on a voltage on the sensing node. Also disclosed is a sensing sequence in which control circuits apply BLC voltage to the BLC transistor, transfer voltage to the transfer transistor and current control voltage to the current source transistor to provide a charging current to the BL, and to adjust the current control voltage to provide a keeping current on the BL from the current source transistor, and to apply a read voltage to a selected memory cell on the bit line. Additionally included is applying a timing signal to the output circuit to generate the data based on a voltage on the sensing node.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: January 5, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Ji-Yu Hung
  • Patent number: 10854604
    Abstract: Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: ChihWei Kuo, Haining Yang, Jun Yuan, Kern Rim
  • Patent number: 10839905
    Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 17, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 10783095
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a page-reading portion which selects a page of the memory cell array, reads data of the selected page, and transmits the read data to a data-holding portion, and a control portion which controls continuous reading of pages. When a command related to termination of the continuous reading is input, the control portion terminates the continuous reading. When the command related to the termination of the continuous reading is not input, the continuous reading terminates. During a period in which the continuous reading is performed continuously, even if a chip selection signal is toggled, the continuous reading can be performed continuously without inputting a page-data read command.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 22, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Takehiro Kaminaga, Katsutoshi Suito
  • Patent number: 10777245
    Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Andrea Redaelli
  • Patent number: 10770157
    Abstract: Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 8, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Wei Zhao, Henry Chin
  • Patent number: 10741264
    Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 11, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari
  • Patent number: 10706931
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Maejima
  • Patent number: 10684981
    Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Radu Pitigoi-Aron, Sharon Graif, Richard Dominic Wietfeldt
  • Patent number: 10672787
    Abstract: An electrode structure includes a plurality of electrodes vertically stacked on a substrate. Each of the plurality of electrodes includes an electrode portion, a pad portion and a protrusion. The electrode portion is parallel to a top surface of the substrate, extending in a first direction. The pad portion extends from the electrode portion in an inclined direction with respect to the top surface of the substrate. The protrusion protrudes from a portion of the pad portion in a direction parallel to the inclined direction. Protrusions of the plurality of electrodes are arranged in a direction diagonal to the first direction when viewed from a plan view.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Hwang, Sunghoi Hur
  • Patent number: 10650897
    Abstract: A storage device may perform a reprogram operation on a page on which a program operation is interrupted due to a sudden power off. The storage device may include a memory device including a plurality of memory blocks, each of which includes a plurality of pages, and a memory controller configured to perform a reprogram operation on a page in which a program operation is suspended using reprogram data that is set depending on threshold voltages of memory cells included in the page on which the program operation is interrupted, among the plurality of pages.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventor: Beom Ju Shin
  • Patent number: 10636812
    Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips. The plurality of stacks of conductive strips includes a plurality of intermediate levels of conductive strips configured as word lines and an upper level of conductive strips configured as string select lines. A plurality of first patterned conductors is disposed above the plurality of stacks of conductive strips. A plurality of linking elements connects conductive strips in respective intermediate levels in the plurality of intermediate levels of conductive strips to first patterned conductors in the plurality of first patterned conductors. The linking elements in the plurality of linking elements include switches responsive to signals in conductive strips in the upper level of conductive strips.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: April 28, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10622372
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Patent number: 10608008
    Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 31, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Raul Adrian Cernea
  • Patent number: 10607703
    Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 31, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hsuan Liang, Jeng-Wei Yang, Man-Tang Wu, Nhan Do, Hieu Van Tran
  • Patent number: 10580476
    Abstract: A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ryan P. King, Stephen Glancy, John S. Bialas, Jr.
  • Patent number: 10566039
    Abstract: A memory device includes a memory cell array including a plurality of word lines, a first string select line above the plurality of word lines, and a second string select line between the first string select line and the plurality of word lines, and a controller. During an operation of reading data of a first memory cell connected to a first word line among the plurality of word lines, the controller is to supply a first voltage to the first string select line and to supply a second voltage to the second string select line, the second voltage being greater than the first voltage.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Wan Nam, Dong Hun Kwak, Wan Dong Kim, Chi Weon Yoon
  • Patent number: 10552510
    Abstract: Systems and methods for a vector-by-matrix multiplier (VMM) module having a three-dimensional memory matrix of nonvolatile memory devices each having a charge storage, an activation input, a signal input and an output signal in a range that is based on a stored charge and an input signal during assertion of the activation signal. The memory devices are arranged in two dimensional (XY) layers that are vertically disposed along (Z) columns. The activation inputs of each layer are connected to a same activation signal, the memory devices of rows in a first dimension (X) of each layer have signal inputs connected to different input signals and have signal outputs connected in series to a common output. The memory devices of rows in a second dimension (Y) of each layer have signal inputs connected to a set of the same inputs along the first dimension.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: February 4, 2020
    Assignee: MENTIUM TECHNOLOGIES INC.
    Inventors: Farnood Merrikh Bayat, Mirko Prezioso
  • Patent number: 10504908
    Abstract: A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube, a second MOS tube and an anti-fuse element, wherein a gate end of the first MOS tube is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube and a voltage limiting device, and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second MOS tube is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device and the second connecting end of the first MOS tube.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 10, 2019
    Assignee: SICHUAN KILOWAY ELECTRONICS INC.
    Inventors: Jack Z. Peng, Junhua Mao, Xuyang Liao
  • Patent number: 10482025
    Abstract: According to one embodiment, for each area having a first size, a number of accesses to the area is recorded in first information. In units of sub areas each having a second size smaller than the first size, access information for the sub area is recorded in the second information. In the first information, the number of accesses to an area to which a sub area in which duplicate accesses occur belongs is updated.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: November 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Kohei Oikawa
  • Patent number: 10468081
    Abstract: A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL to the sense amplifier. The decoder includes first and second multiplexers. The first multiplexer includes a first n-type transistor and a first p-type transistor. The first n-type transistor is connected to the first BL and capable of applying a first voltage for writing a first logic or a non-select voltage for not writing data to the first BL. The first p-type transistor is connected to the first BL and capable of applying a second voltage for writing a second logic or the non-select voltage to the first BL. The second multiplexer is connected between the first multiplexer and the sense amplifier and transmits the first voltage or the non-select voltage to the first n-type transistor and transmits the second voltage or the non-select voltage to the first p-type transistor.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yusuke Niki
  • Patent number: 10453823
    Abstract: A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. The first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate. The first capacitor node can be electrically connected to a first terminal, which is electrically connected to receive a power supply potential from a power supply terminal. The second semiconductor device can receive the power supply potential from the power supply terminal. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The first capacitor node includes at least one essentially vertically formed conductive portion disposed in the substrate of the first semiconductor device and through at least half of a vertical thickness of the first semiconductor device.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Darryl G. Walker
  • Patent number: 10453535
    Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Shantanu R. Rajwade, Akira Goda, Pranav Kalavade, Krishna K. Parat, Hiroyuki Sanda
  • Patent number: 10453847
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 22, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10446257
    Abstract: Provided herein may be a storage device having improved operating speed and a method of operating the same. The storage device may include a memory controller configured to control the plurality of dies, each including two or more planes. The memory controller may include a reserved block information storage unit configured to store reserved block information that is information related to reserved blocks included in the plurality of dies; and a bad block management control unit configured to set, when a bad block occurs among memory blocks respectively included in the plurality of dies, a reserved block to replace the bad block depending on whether any one of available reserved blocks are included in a plane to which the bad block belongs, among the two or more planes included in a die including the bad block, based on the reserved block information.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventor: Min Kee Kim
  • Patent number: 10431308
    Abstract: Scalable Logic Gate Non-Volatile Memory (LGNVM) NOR-type arrays fabricated by the standard CMOS logic technologies have been applied for the embedded flash solutions in digital circuitries. To significantly reduce the memory array sizes from the previous fabrications, we have applied the topological regularity of memory cells in the arrays and a self-aligned etch process step to eliminate the gate end-caps in the memory areas. Without scarifying the memory array yields, the minimal unit cell size of 12 F2 for the LGNVM NOR flash arrays can be achieved by this method, where F is the minimal feature size for a specific CMOS logic process technology node.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 1, 2019
    Assignee: Flashsilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 10367001
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10354736
    Abstract: The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an uncertainty prediction circuit coupled to the memory cells, and a data conversion circuit coupled to the memory cells. The uncertainty prediction circuit is configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state. The data conversion circuit is configured to apply a data conversion to a portion of data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Pitamber Shukla
  • Patent number: 10310972
    Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 4, 2019
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Yong Ju Kim, Do Sun Hong
  • Patent number: 10312248
    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 4, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
  • Patent number: 10304541
    Abstract: A memory device includes a memory cell array including a first switch cell, a second switch cell, and a plurality of memory cells disposed between the first the second switch cells and connected to a plurality of word lines, and a control circuit configured to perform a program operation by providing a program voltage to a first word line among the plurality of word lines, a switch voltage to a second word line among the plurality of word lines, and a pass voltage to remaining word lines among the plurality of word lines, wherein the control circuit is configured to turn off the first switch cell and the second switch cell in a first section of the program operation, and configured to turn on the first switch cell and increase the switch voltage in a second section of the program operation later than the first section.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Gyung Hwang, Byoung Taek Kim, Yong Seok Kim, Ju Seok Lee
  • Patent number: 10285274
    Abstract: A circuit structure is provided to which an electronic component can be easily mounted (electrical connection of terminals). A circuit structure that includes a substrate provided with a conductive pattern on one face thereof; a conductive member fixed to the other face of the substrate; an electronic component that has first terminals and of a plurality of terminals, that are electrically connected to the conductive member, and a second terminal of the plurality of terminals that is electrically connected to the conductive pattern provided on the substrate; and a relay member for electrically connecting the second terminal and the conductive pattern provided on the substrate, at least a portion of the relay member being fixed to the conductive member via an insulating material.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: May 7, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Arinobu Nakamura, Tou Chin
  • Patent number: 10269435
    Abstract: A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells is decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 10262975
    Abstract: A system can include a first semiconductor device including a first capacitor with a first terminal coupled to receive a power supply potential; and a second semiconductor device including a first voltage generator coupled to the first terminal of the first capacitor, the first voltage generator provides a first voltage generator output potential at an output terminal. The first capacitor can include a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include at least one substantially vertically formed conductive portion in a substrate of the first semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node is electrically connected to the first terminal of the first capacitor.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: April 16, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10262976
    Abstract: A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. A first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate, separated from one another by at least one capacitor dielectric. A first capacitor node can be electrically connected to the first terminal of the first capacitor. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The at least one essentially vertically formed conductive portion can comprise polysilicon.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: April 16, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10263002
    Abstract: In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 16, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Hideo Kasai, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Kosuke Okuyama