Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.

Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string, and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.

Abstract: Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.

Abstract: A scramble unit subjects data to be written into twin cells in a first storage unit to scramble processing with the use of scramble data. A write unit writes write data subjected to the scramble processing into the twin cells in the first storage unit. A write unit writes scramble data into a memory cell in a second storage unit. A descramble unit subjects the data read from the first storage unit to descramble processing with the use of scramble data read from the second storage unit.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

Abstract: A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.

Abstract: A shared floating gate device, the device including an nFET including an nFET gate dielectric, a pFET including a pFET gate dielectric, and a floating gate, where the nFET and the pFET are connected in parallel and share the floating gate.

Abstract: Described herein is a ROM architecture featuring a ROM bitcell without a transistor, a ROM architecture wherein the bitcell device gate goes to a column address and the local bitline is sensed per row per mux, a ROM architecture wherein the bitcell device gate goes to the column address and the full row of bitcells is enabled by a row enable signal, and a ROM architecture wherein the bitcell device gate goes to the row address and the full column of bitcells is enabled by a column enable signal. The presently described architectures provide large advantages in terms of PPA.

Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

Abstract: Described herein is a ROM architecture featuring a ROM bitcell without a transistor, a ROM architecture wherein the bitcell device gate goes to a column address and the local bitline is sensed per row per mux, a ROM architecture wherein the bitcell device gate goes to the column address and the full row of bitcells is enabled by a row enable signal, and a ROM architecture wherein the bitcell device gate goes to the row address and the full column of bitcells is enabled by a column enable signal. The presently described architectures provide large advantages in terms of PPA.

Abstract: A dynamic random access memory, including a main body, a processing unit, a display screen and a transmit port. The main body has a substrate and a shell portion disposed by two opposite side faces of the substrate, the substrate is provided with a memory module; the processing unit is disposed in the main body; the display screen is attached to the main body and viewable from outside of the dynamic random access memory, the display screen is electrically connected with the processing unit, the processing unit can control a display state of the display screen; and the transmit port is disposed on the substrate, and the transmit port is electrically connected with the memory module.

Abstract: A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache latch to the pair of the input/output lines, when the corresponding cache latch is selected among the plurality of cache latches; a pre-charger suitable for pre-charging the pair of the input/output lines; and a sense-amplifier suitable for sensing and amplifying the data of the pair of the input/output lines, wherein the sense-amplifier operates with a first power source voltage, and the plurality of the cache latches, the plurality of the switches, and the pre-charger operate with a second power source voltage having a voltage level that is higher than the voltage level of the first power source voltage.

Abstract: A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.

Abstract: A nonvolatile memory includes a plurality of memory blocks and an address decoder. The address decoder is configured to activate a block word line corresponding to the memory blocks in common when one memory block is selected among the memory blocks, supply voltages to word lines of the selected memory block among the memory blocks, and float word lines of an unselected memory block among the memory blocks.

Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

Abstract: A data storage device includes a nonvolatile memory device including word lines each including one or more pages; and a controller suitable for, in the case where recovery is made to a normal state from a power-off state, searching a word line including an erased page among the word lines, and selecting, when all pages of the word line including the erased page are erased pages, the corresponding word line as a reliability verification word line.

Abstract: A memory array includes an N×M array of memory cells, each memory cell having a first transistor connected to a first terminal and a second transistor connected in parallel to the first transistor and a second terminal, where the first and second transistors share a common floating gate and a common output node. Each memory cell further includes an access transistor connected in series to the common output node and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate. The first transistor is an n-type transistor and the second transistor is a p-type transistor.

Abstract: A semiconductor memory device includes a memory cell array including a block of memory cells, gates of which are connected to a plurality of word lines, and a control unit configured to perform a writing operation in response to a command received from the outside, the writing operation including applying a program level voltage to at least two word lines at the same time.

Abstract: A package can include first, second, and third dynamic random access memory (DRAM) semiconductor devices having first, second and third through vias, respectively, and stacked above an interposer. First, second, and third interface connections can be formed between the DRAM semiconductor devices. A first wiring of the interposer can be connected at a central portion of a first external connection that receives a first power supply potential. A second wiring of the interposer can be connected to a second external connection that receives a first data signal.

Abstract: A nonvolatile memory device may include a nonvolatile memory device may include a nonvolatile memory cell array; a peripheral circuit suitable for: activating an operation voltage in response to an operation voltage activation command, performing an operation to the nonvolatile memory cell array using the activated operation voltage in response to an operation command, and deactivating the activated operation voltage in response to an operation voltage deactivation command after the performing of the operation; and a control circuit suitable for controlling the peripheral circuit to execute an intervening operation during the activating of the operation voltage, the performing of the operation, and the deactivating of the activated operation voltage.

Abstract: An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor.

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

Abstract: A semiconductor device that can store multilevel data is provided. A circuit includes a transistor. The circuit includes another circuit including a terminal, for example. The terminal is connected to a gate of the transistor. One of a source and a drain of the transistor is connected to a wiring, and the other of the source and the drain is connected to another wiring.

Abstract: A nonvolatile memory device includes a memory cell array, an address decoder, a read & write circuit and control logic. The memory cell array includes a plurality of memory blocks including a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate. The control logic controls operations so that in a program operation, when the selected word line satisfies a precharge condition, a program voltage to be applied to the selected word line is applied before a pass voltage to be applied to an unselected word line.

Abstract: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

Abstract: A package can include first and second semiconductor devices stacked in a first direction. The first semiconductor device can include a first circuit formed on the first semiconductor device that provides a first potential greater than a ground potential at a first circuit output, and a second circuit coupled to receive the first circuit output. The second semiconductor device can include a first through via providing a first electrical connection between a first side and a second side of the second semiconductor device, and a third circuit. The first circuit output can be electrically connected to the first through via at the first side of the first semiconductor device and the third circuit can be electrically connected to the first through via at the second side of the first semiconductor device to receive the first potential.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.

Abstract: A voltage switching circuit includes: a control signal generation block configured to include a high voltage switching block which controls an electric current flowing according to a high voltage in response to a voltage level of a low voltage control signal and generates complementary high voltage control signals; and a high voltage transfer block configured to be driven according to the complementary high voltage control signals, and generate a switching signal, the voltage level of which is raised based on the high voltage so that the switching signal has substantially the same level as the high voltage.

Abstract: A data storage device includes a semiconductor structure including a first conductive-type region having a first-type conductivity, a second conductive-type region spaced apart from the first conductive-type region and having a second-type conductivity opposite to the first-type conductivity, and a semiconductor region between the first conductive-type region and the second conductive-type region and including a neighboring portion adjacent to the second conductive-type region; a mode select transistor including a gate electrode aligned with the neighboring portion and an insulation layer between the gate electrode and the neighboring portion; a plurality of memory cell transistors including a plurality of control gate electrodes aligned with the semiconductor region, and a data storage layer interposed between the plurality of control gate electrodes and the semiconductor region; a first wire electrically connected to the first conductive-type region; and a second wire including an ambipolar contact having a

Abstract: In a method of programming a non-volatile memory device, a first voltage is applied to a selected memory cell for programming, and a second voltage is applied to a non-selected memory cell. Before the second voltage rises to a predetermined voltage level, which is less than a program voltage level, the first voltage is greater than the second voltage or the second voltage is maintained at greater than a ground voltage level. Related non-volatile memory devices and memory systems are also discussed.

Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Abstract: A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract: Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory cells, where individual strings may have memory cells that correspond to different memory blocks (e.g., multiple memory blocks per string). For example, a first set of memory cells of a string may be included in a first memory block, and a second set of memory cells of the string may be included in a second memory block. The memory device may include separator wordlines disposed between wordlines associated with the first memory block and wordlines associated with the second memory block. The separator wordlines may receive different bias voltages during various operations of the memory device. Additionally, a wordline biasing scheme may be selected to program the first memory block based on whether the second memory block is programmed. Other embodiments may be described and/or claimed.

Abstract: A novel semiconductor device, a semiconductor device capable of operating at high speed, or a semiconductor device with low power consumption is provided. The semiconductor device includes a memory cell, a first circuit, a second circuit, and a wiring. The memory cell has a function of storing first data and has a function of supplying a first current corresponding to the first data to the wiring. The first circuit has a function of supplying a second current corresponding to second data to the wiring input from the outside. The second circuit has a function of performing correction of a current flowing in the wiring in the case where a value of the first current and a value of the second current are different from each other. The second circuit has a function of generating a signal including information on whether the correction is performed or not.

Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.

Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Abstract: In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.

Abstract: A non-volatile semiconductor memory device includes a first memory cell above a substrate and electrically connected to a first word line, a second memory cell above the first memory cell and electrically connected to a second word line, and a controller. The controller is configured to execute a write operation that includes a first step in which a first voltage is applied to a selected word line and to a non-selected word line, a second step after the first step in which a program voltage is applied to the selected word line, and a third step after the second step in which a second voltage higher than the first voltage is applied to the non-selected word line. A time period between a start of the second step and a start of the third step is different depending on whether the first or second memory cell is being written.

Abstract: An apparatus is provided which comprises: a bi-directional switch; and a comparator coupled to the bi-directional switch, the comparator having: a first input coupled to a first terminal of the bi-directional switch; a second input coupled to a second terminal of the bi-directional switch; and an output coupled to a body or substrate of the bi-directional switch.

Abstract: A semiconductor memory, including: a plurality of data terminals for transmitting data; a plurality of buffer circuits, each being coupled to a corresponding one of the data terminals; and a control circuit receiving an access command, that controls reading data from a memory cell array or writing data to the memory cell array, and a terminal setting information issued with each access command, and controlling the buffer circuits based on the access command and the terminal setting information, wherein, when the terminal setting information indicates a first mode, all of the buffer circuits function as input buffer circuits or output buffer circuits based on the access command, and wherein, when the terminal setting information indicates a second mode, a part of the buffer circuits functions as the input buffer circuits and a remaining part of the buffer circuits functions as the output buffer circuits.

Abstract: A reading method for a cell string using multiple pass voltages includes a pre-charging step and a reading step to read a selected word line cell WL[k]. The pre-charging step comprises applying a positive pass voltage (Vpass1) to the selected word line (WL[k]), the upper word lines (Upper WL) of the selected word line (WL[k]), at least one the lower word lines adjacent to the selected word line (WL[k]); and applying a negative pass voltage (Vpass2) to the remaining lower word lines (Lower WL) except for WL[k?1]. The reading step comprises applying sequentially a first voltage which is lower than a read voltage (Vverify) and the read voltage (Vverify) to the selected word line WL[k], applying a second voltage to a common source line CSL and the unselected word lines and sensing a current or a voltage of the selected word line WL[k], thereby reading information stored in the selected word line WL[k].

Abstract: A semiconductor device and a method for forming the same. The semiconductor device includes a tunnel insulating layer, a charge storage layer including a dopant, and a diffusion barrier layer including at least one of carbon, nitrogen, or oxygen interposed between the tunnel insulating layer and the charge storage layer.

Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.