Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.

Abstract: The present technology relates to an electronic device. A memory controller controls a memory device such that a life of the memory device is increased. The memory controller that controls the memory device includes a flash translation layer configured to generate a device health descriptor based on device information received from the memory device, and a bad block controller configured to generate a bad block table based on bad block information received from the memory device, and generate recycling information for recycling pages in bad blocks recorded in the bad block table based on the device health descriptor.

Abstract: Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.

Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.

Abstract: A memory system includes a memory device including a memory cell array including a plurality of memory cell groups, and a controller for selectively activating or inactivating one of the memory cell groups.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory, a sensor measuring temperature, and a controller controlling the nonvolatile memory in accordance with the temperature measured by the sensor. The controller selects a write scheme based on the temperature measured by the sensor at a time of a write process of data with respect to the nonvolatile memory, generates management data including the write scheme with respect to the data, writes the data to the nonvolatile memory in accordance with the write scheme, obtains the write scheme with respect to the data from the management data at a time of a read process of the data, and reads the data from the nonvolatile memory in accordance with the write scheme.

Abstract: A memory controller includes a control circuit. The control circuit configures a plurality of physical blocks in a flash memory into a group. The control circuit allocates the plurality of physical blocks constituting the group to a data block and a redundant block. The control circuit writes data required to be saved into the data block. The control circuit writes redundant data based on the data required to be saved into the redundant block belonging to the same group as the data block. When all the data required to be saved are successfully written into the data block, the control circuit releases from the group at least one redundant block belonging to the same group as the data block.

Abstract: A key-value storage architecture with data compression is shown. A computing unit is configured to estimate the average compression rate factor of a non-volatile memory. The computing unit is further configured to estimate storage space consumption of the non-volatile memory based on the average compression rate factor, and programming of the non-volatile memory is prohibited if to the storage space consumption exceeds a predefined threshold. The average compression rate factor is dynamically updated, and is a weighted result of compression rate factors of several storage units of the non-volatile memory.

Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.

Abstract: A method used in a flash memory controller includes: using a watchdog timer to automatically count a number and to generate a reset trigger signal to a processor if the number counted by the watchdog timer is higher than a threshold; after receiving the reset trigger signal from the watchdog timer, using the processor to copy registry information from at least one of processor, flash memory interface controller, and protocol controller, and then to control the memory controller to write the copied registry information into the dynamic random access memory device without rebooting a system of the flash memory controller.

Abstract: An electronic device is provided. A page buffer includes at least one data latch, a sensing latch, and a bit line voltage controller. At least one data latch stores a program verification result of a previous program loop among a plurality of program loops and program data to be stored in a memory cell. The sensing latch stores a program verification result of a current program loop among the plurality of program loops. The bit line voltage controller updates the program verification result of the previous program loop which is stored in the at least one data latch to the sensing latch during a program operation of a next program loop of the current program loop among the plurality of program loops.

Abstract: Memory devices are disclosed. A memory device may include a memory array including a number of column planes and at least one circuit coupled to the memory array. The at least one circuit may generate test result data for a column address for each column plane of the number of column planes. The at least one circuit may further convert the test result data to a first result responsive to two or more of the column planes failing the test. The at least one circuit may also convert the test result data to a second result responsive to no column planes failing the test. Further, the at least one circuit may convert the test result data to a third result responsive to one column plane failing the test. The third result may identify the one column plane. Methods of testing a memory device, and electronic systems are also disclosed.

Abstract: The present invention is notably directed to methods for estimating a degradation of an electronically controlled electro-mechanical switch. The methods comprise determining a change of state of the contactor. They also comprise, computing, for each determined change of state, a wear increment WI of the contactor by: identifying a wear coefficient using a mapping between a last measured current through the contactor and a current range associated with a given wear coefficient; computing the actual wear WN of the contactor by adding the computed wear increment WI to a former known wear WI?1 of the contactor.

Abstract: Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Abstract: The present technology relates to an electronic device. A memory controller instructs to perform a dummy read operation on a shared block after an operation is performed on a target block. The memory controller that controls a memory device including a plurality of memory blocks may include a flash translation layer that translates a logical block address received from a host into a physical block address and generates translation information on the translated physical block address and a dummy read controller configured to output, to the memory device, a dummy read command to perform a dummy read operation on a sharing block selected together with a target block after an operation corresponding to a request received from the host is performed on the target block among the plurality of memory blocks, based on the received request and the translation information.

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

Abstract: A processing device in a memory system determines sensitivity value of a memory page in the memory system. The processing device assigns the memory page to a sensitivity tier of a plurality of sensitivity tiers based on a corresponding sensitivity value, wherein each sensitivity tier has a corresponding range of sensitivity values. The processing device further determines a targeted scan interval for each sensitivity tier of the plurality of sensitivity tiers and scans a subset of a plurality of memory pages in the memory component, wherein the subset comprises a number of memory pages from each sensitivity tier determined according to the corresponding targeted scan interval of each sensitivity tier.

Abstract: Placing data within a storage device, including: receiving, by a storage device, information describing an expected longevity of data stored on the storage device; determining, by the storage device, a location for storing the data in dependence upon the expected longevity of the data; adjusting a garbage collection schedule in dependence upon data placement; and providing, to a storage array controller, garbage collection statistics.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a CAM block configured to store CAM data required for various operations, a page buffer group configured to store the CAM data read from the CAM block through a CAM read operation, an extra register configured to store extra data generated by performing an operation on the CAM data, an operation logic configured to perform an operation of checking a defect in the extra register, registers configured to sequentially store operation data generated through the defect check operation, a fixed register configured to store fixed data obtained through an operation performed to check an error in the CAM data, and core circuits configured to perform the CAM read operation and transmit the operation data and the CAM data to the extra register, the registers, and the fixed register.

Abstract: Disclosed are devices, systems, apparatus, methods, products, and other implementations, including a method that includes determining whether an operation to access a memory location containing executable code comprises a general-purpose memory access operation, and changing content of the memory location in response to a determination that the operation to access the memory location containing the executable code comprises the general-purpose memory access operation to the memory location.

Abstract: Methods, systems and computer program products for providing access to a spare memory array element (“MAE”) are provided. Aspects include storing a row number a column number associated with a defective MAE of a plurality of MAEs. The plurality of MAEs are logically arranged in a plurality of rows and a plurality of columns. Aspects also include receiving a command to access a cache line. The cache line corresponds to a selected row of MAEs of the plurality of MAEs. Responsive to determining that the selected row matches the row number that is associated with the defective MAE, aspects include activating one or more column shifters to prevent access to the defective MAE and provide access to a spare MAE when accessing the cache line. The activation of the one of more column shifters is based on the column number that is associated with the defective MAE.

Abstract: A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.

Abstract: Provided are a computer program product, system, and method for using a machine learning module to determine when to perform error checking of a storage unit. Input on attributes of at least one storage device comprising the storage unit are provided to a machine learning module to produce an output value. An error check frequency is determined from the output value. A determination is made as to whether the error check frequency indicates to perform an error checking operation with respect to the storage unit. The error checking operation is performed in response to determining that the error checking frequency indicates to perform the error checking operation.

Abstract: A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including memory cells that are programmed into a plurality of program states, a peripheral circuit configured to perform a read operation on the memory cell array, and control logic configured to control the peripheral circuit to perform the read operation and to control the peripheral circuit to perform a masking process on first memory cells having a threshold voltage level higher than a first read level and second memory cells having a threshold voltage level lower than a second read level among the memory cells during the read operation.

Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is operable to measure a first threshold voltage (VT) of a memory cell under a first parameter at a read temperature and measure a second VT of the memory cell under a second parameter at the read temperature in which the first parameter is different from the second parameter. A VT correction term for the memory cell is determined based upon the first VT measurement and the second VT measurement. A read VT of the memory cell is adjusted by using the VT correction term.

Abstract: A nonvolatile memory device capable of minimizing monitoring overhead associated with read disturb is provided. The nonvolatile memory device includes a memory cell array which includes a first cell string comprising a plurality of memory cells connected in series, wherein the plurality of memory cells includes a first monitoring cell, a first memory cell, and a second memory cell, and a row decoder which provides a first read voltage to the first memory cell and a first monitoring voltage to the first monitoring cell when reading the first memory cell among the memory cells and provides the first read voltage to the second memory cell and a second monitoring voltage different from the first monitoring voltage to the first monitoring cell when reading the second memory cell.

Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.

Abstract: A memory device protection manager determines an estimated remaining life of a physical memory device. By comparing the estimated remaining life of the physical memory device to a threshold value, the memory device protection manager determines whether a drive protection condition has been triggered. When the drive protection condition is triggered, the memory device protection manager modifies a write performance for subsequent data units to a modified write performance rate. The modified write performance rate is an upper limit on the write performance for the subsequent data units.

Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

Abstract: A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

Abstract: A non-volatile memory and a data writing method are provided. The non-volatile memory includes a memory array and a memory controller. The memory array has a plurality of memory cells. The memory controller is configured to perform a data write operation on a plurality of selected memory cells. In the data write operation, the memory controller records a total number of times that a data write pulse is supplied, compares the total number of times of the data write pulse to a preset threshold value to obtain an indication value, and adjusts an absolute value of a voltage of the data write pulse according to the indication value.

Abstract: A decoding system and method of a non-volatile memory are provided in which information regarding a characteristic of a non-volatile memory is used to determine an initial log-likelihood-ratio (LLR) table from among a number of LLR tables. The decoding is then performed using the determined initial LLR table.

Abstract: A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, and a P-well. The control circuit performs an erasing and verification method, wherein the erasing and verification method includes erasing the selected memory block during an erasing stage; and maintaining the bottom select gate to be turned on during a maintaining period before the top select gate are turned on during a verification stage.

Abstract: Aspects of a storage device including a controller are provided which recovers misidentified bad blocks that fail to erase due to charge leakage from a previously programmed open block. The controller programs an open block, and attempts to erase a plurality of closed blocks following the programming of the open block. When the closed blocks fail to erase, the controller marks the closed blocks as bad blocks. The controller then determines whether a number of consecutive erase failures after programming the open block meets a threshold, in response to which the controller resets a die including the closed blocks and reattempts to erase the closed blocks. The controller then unmarks as bad blocks the closed blocks which successfully erased in response to the re-attempt.

Abstract: An apparatus includes nonvolatile memory cells arranged in columns including a plurality of redundant columns with control circuits coupled to the nonvolatile memory cells. The control circuits are configured to maintain an ordered list of bad columns replaced by redundant columns. The control circuits are configured to detect an out-of-order entry in the ordered list of bad columns replaced by redundant columns.

Abstract: A leakage measuring circuit includes a bias input node control circuit and provides a signal indicative of a leakage current through the bias input node. The bias input node control circuit includes a first input to receive an indication of a reference voltage, a second input to receive an indication of a voltage of the bias input node, and an output to bias the bias input node at the reference voltage based on a relationship between the first and second input. A well voltage bias circuit provides a well bias voltage and includes a well bias control circuit including a first input to receive the signal indicative of the leakage current, a second input to receive a signal indicative of a reference leakage current value, and an output for controlling the well bias voltage based on a relationship between the first and second input of the well bias control circuit.

Abstract: A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.

Abstract: A program method capable of reducing a peak current of a program operation is provided. The program method of a flash memory includes following steps: charging selective bit lines and non-selective bit lines by using a virtual voltage with weak driving ability during the time from t0 to t1 and a virtual voltage with strong driving ability during the time from t1 to t2, switching at least the non-selective bit lines to use the virtual voltage with weak driving ability for charging during at least the time from t2 to t3 when starting to discharge the selective bit lines connected to selective storage cells to a GND voltage level at time t2, and then applying program voltages to selective word lines.

Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks.

Abstract: A memory system includes a memory device including a test region; and a processor configured to write pattern data transferred from a host device to a pattern data region included in the test region, read test data from the test region, and transmit the read test data to the host device. A position of the pattern data region may be adjustable in the test region.

Abstract: A computer-implemented method, according to one embodiment, includes: detecting that a calibration of a first page group has been triggered, and evaluating a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.

Abstract: There are provided a memory controller and a memory system including the same. The memory controller includes: a processor for generating a command and an address in response to a request from a host, and generating a bin label and a Log Likelihood Ratio (LLR), based on data received from memory devices; a buffer memory for temporarily storing the data, the bin label, and the LLR; and an error correction circuit for performing error correction decoding on the data, using the LLR.

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

Abstract: A storage device includes a first nonvolatile memory chip; a second nonvolatile memory chip; and a controller. The controller may include a processor configured to execute a flash translation layer (FTL) loaded onto an on-chip memory; an ECC engine configured to generate first parity bits for data and to selectively generate second parity bits for the data, under control of the processor; and a nonvolatile memory interface circuit configured to transmit the data and the first parity bits to the first nonvolatile memory chip, and to selectively transmit the second parity bits selectively generated to the second nonvolatile memory chip.

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device according to the present embodiment comprises: an STT-MRAM memory array which includes a data storage unit for storing data, a defect area address storage unit for storing an address of a defect area, and a spare area for storing data of a failed area; and a bypass determination unit which includes a volatile information storage element for storing the address of the defect area, stored in the defect area address storage unit and provided thereto, and when memory array access occurs, compares an access address with the address of the defect area stored in the volatile information storage element and causes the memory array access to bypass to the spare area.

Abstract: A controller for controlling an operation of a semiconductor memory device includes an error correction block and a block manager. The error correction block may perform an error correction operation on read data received from the semiconductor memory device. The block manager may analyze a result of the error correction operation and selectively perform defect processing on a target memory block in which the read data is stored, based on a number of error correction units in which an error correction failure has occurred, among a plurality of error correction units included in the read data.

Abstract: An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

Abstract: A memory sub-system can be determined to be operating within a target operating characteristic based on a threshold success rate associated with error control operations using a particular parameter. Upon determining that the memory sub-system is operating within the target operating characteristic, a sticky read mode is entered by performing subsequent read operations using the particular parameter. It is determined that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode. Upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, the sticky read mode is exited by performing further read operations using a default parameter associated with the memory sub-system.