Abstract: ABSTRACT A semiconductor memory device provides a first memory cell array including a plurality of first memory blocks, a second memory cell array comprising a plurality of second memory blocks, and a voltage supply line electrically connected to the plurality of first memory blocks and the plurality of second memory blocks. Moreover, this semiconductor memory device is configured to execute a write operation. At a first timing of this write operation, the voltage supply line is not electrically continuous with the first and second memory blocks. Moreover, a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first and second memory blocks is larger than a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first memory block.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

Abstract: An ephemeral peripheral system includes an ephemeral memory system and controller circuit for securing user data for a smartphone application. Different secure operating modes are provided for customizing user security requirements across end-to-end communications links, including in exchanges of electronic data between smartphone devices.

Abstract: A memory device includes a cell group including a plurality of non-volatile memory cells capable of storing data and a control circuit configured to perform plural program loops for storing the data, each program loop including a program voltage application operation and a verification operation. During the respective program loop, the control circuit performs the verification operation for an N target level, an N?1 target level lower than the N target level, and an N+1 higher than the N target level, in response to the program voltage application operation for the N target level. When a quantity of non-volatile memory cells having threshold voltages over the N+1 target level satisfies a preset criterion, the control circuit skips a next verification for a target level lower than the N+1 target level, in response to a next program voltage application operation for the N+1 target level.

Abstract: Various embodiments provide for erasing of one or more partially-programmed memory units of a memory device. In particular, various embodiments provide for monitoring (e.g., tracking) of partial program/erase cycles for a memory unit (e.g., block) of a memory device, and performing an erasure of the memory unit based on the monitoring.

Abstract: The semiconductor memory device includes a memory block including a plurality of memory strings, a pass circuit connected between local word lines of the memory block and global word lines and configured to connect the local word lines to the global word lines in response to a block selection signal, and a voltage providing circuit configured to generate an operation voltage during a program or read operation, apply the operation voltage to the global word lines, and discharge the global word lines when the program operation or the read operation is completed, and the pass circuit is configured to control the local word lines to be in a floating state after the program operation or the read operation is completed and before discharging the global word lines.

Abstract: A method includes transferring data out of a first buffer coupled to a first plane of a plurality of planes of a memory component, where the data was previously transferred from the first plane to the first buffer responsive to an access request to sense data stored in the plurality of planes of the memory component. The method further includes transferring, subsequent to transferring the data out of the first buffer and independently of a command from a processing device, data out of a second buffer coupled to a second plane of the plurality of planes of the memory component, where the data transferred out of the second buffer was previously transferred from the second plane to the second buffer responsive to the access request.

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.

Abstract: A memory system includes a nonvolatile memory that stores table data and a memory controller for writing and reading data to and from the nonvolatile memory. The memory controller includes a volatile memory that can be in either a retention state during which power is supplied thereto or a power down state during which the power supplied thereto is cut off, a timer that measures elapsed time starting from when the memory system transitions to the low power state, and a register in which previously measured elapsed times are stored, and in which a current measured elapsed time is stored when the memory system wakes up from the low power state. The controller controls the transitioning of the volatile memory from the retention state to the power down state, if the measured elapsed time is greater than a threshold value, which is calculated based on the previously measured elapsed times.

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: evaluating a read disturbance level of an open block in a memory, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, managing each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.

Abstract: In a method of operating a nonvolatile memory device, the nonvolatile memory device includes a memory block that includes a plurality of memory cells and is connected to a plurality of wordlines. A data write command is received. Based on the data write command, a first program operation is performed on some wordlines among the plurality of wordlines connected to the memory block. At least one of the some wordlines on which the first program operation is performed is detected as a no-coupled wordline. Without the data write command, a second program operation is performed on an open wordline on which the first program operation is not performed and adjacent to the no-coupled wordline.

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: A flash memory controller includes a read only memory (ROM) and a microprocessor. The ROM is arranged to store a program code. The microprocessor is arranged to execute the program code to control access of a flash memory module. When executing the program code, the microprocessor is arranged to perform operations of: monitoring data retention state of one or more blocks in the flash memory module by reading a last page of the one or more blocks to obtain time information regarding the one or more blocks, which is generated by the flash memory controller; and arranging a specific block to a garbage collection process if time information obtained from the last page of the specific block exceeds a threshold.

Abstract: Various embodiments provide for adjusting (or adapting) a program voltage step used to program a memory cell by a program algorithm after the program algorithm resumes from a suspension, where the program voltage step is adjusted (or adapted) based on one or more factors.

Abstract: Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.

Abstract: There is provided a nonvolatile storage element having excellent charge holding characteristics capable of reducing variations in electric characteristics and an analog circuit provided with the same. A nonvolatile storage element is provided with a charge holding region and an insulator surrounding the entire surface of the charge holding region and having halogen distributed in at least one part of a region surrounding the entire surface.

Abstract: Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving a sequence of read commands from a memory sub-system controller; retrieving first data by executing a first read command of the set of read commands; storing the first data in a first portion of a cache of the memory device; responsive to determining that the memory device is in a suspended state, determining whether a first address range specified by the first read command overlaps with a second address range specified by a second read command of the set of read commands; responsive to determining that the first address range does not overlap with the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; transferring the first and second data to the controller.

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: A first logical page type and a second logical page type each comprising a plurality of programming distributions of a memory device are identified. A determination is made that the bit error rate (BER) for the first logical page type is less than a BER for the second logical page type. A set of rules corresponding to a determination that the BER for the first logical page type is less than the BER for the second logical page type is identified. A program targeting rule of the set of rules is determined based on a valley between an erase distribution and a programming distribution adjacent to the erase distribution having a lowest valley margin of a plurality of valley margins corresponding to the plurality of programming distributions of the memory device. Based on the program targeting rule, a program targeting operation is performed to adjust a voltage associated with one or more programming distributions of the memory device.

Abstract: Systems and methods are disclosed for the intelligent scheduling of garbage collection operations on a solid state memory. In certain embodiments, a method may comprise initiating a garbage collection process for a solid state memory (SSM) having a multiple die architecture, determining an order of die access for the garbage collection process based on an activity table indicating a use of one or more die in the multiple die architecture, and performing the garbage collection process based on the determined order of die access. Garbage collection reads may be directed to idle die to avoid conflicts with die busy performing other operations, thereby improving system performance.

Abstract: Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode, data is not written to memory cells in a sub-block that contains SGS transistors whose Vt does not meet the criterion. Hence, the possibility of data loss due to defective SGS transistors is avoided. However, in the sub-block mode, data is written to memory cells in a sub-block that does not contain SGS transistors whose Vt does not meet the criterion. Hence, data capacity is preserved.

Abstract: Apparatuses and techniques are described for programming memory cells with a reduced number of program pulses. A program operation includes a first, foggy program pass followed by a second, fine program pass. The number of program loops in the foggy program pass is minimized while providing relatively narrow Vth distributions for the foggy states. The program loops include one or more checkpoint program loops in which a program speed of the memory cells is determined through a read operation. In a next program loop, the fast-programming memory cells are inhibited from programming while the slow-programming memory cells are programmed with a reduced speed by applying a program speed-reducing bit line voltage. This brings the threshold voltage of the slow-programming memory cells into alignment with the threshold voltage of the fast-programming memory cells.

Abstract: The present technology relates to an electronic device. A memory device that controls a voltage applied to each line to prevent or mitigate a channel negative boosting phenomenon during a sensing operation includes a memory block connected to a plurality of lines, a peripheral circuit configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines, and control logic configured to control voltages applied to drain select lines, source select lines, and word lines between the drain select lines and the source select lines among the plurality of lines, during the sensing operation and an equalizing operation performed after the sensing operation. The control logic controls a voltage applied to an unselected drain select line according to whether a cell string is shared with a selected drain select line among the drain select lines, during the sensing operation.

Abstract: In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may comprise flash storage for data, the flash storage organized into a plurality of blocks. A controller may manage reading data from and writing data to the flash storage. Metadata storage may store device-based log data for errors in the SSD. Identification firmware may identify a block responsive to the device-based log data. In some embodiments of the inventive concept, verification firmware may determine whether the suspect block is predicted to fail responsive to both precise block-based data and the device-based log data.

Abstract: A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

Abstract: The semiconductor device 1 comprises a processor 2, a memory connected to the processor and a control circuit, and comprises an active operation mode and a standby operation mode. The memory comprises a normal mode and a RS mode lower power consumption than the normal mode. The memory comprises SRAMs 7_0 to 7_5 which includes a mode terminal RS_T supplied with mode instruction signals RS1_0 to RS1_5 specifying the normal mode or the RS mode, respectively. The control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_0 to 7_2 in transition period which the semiconductor device transitions from the standby operation mode to the active operation mode. And the control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_3 to 7_5 after transition to the active operation mode.

Abstract: A memory includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) lines, and second signal lines. A memory cell array includes memory cells. (m+2) or more global signal lines are configured to apply a selection voltage to any of the first signal lines. First transistors are provided to correspond to each of the first signal lines in one-to-one correspondence and are connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups, and are each connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. The first signal lines located at both ends of each of any two of the groups which are adjacent to each other are connected to mutually different ones of the global signal lines.

Abstract: A storage apparatus includes an interface and storage circuitry. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple programming levels. The storage circuitry configured to program data to a first group of multiple memory cells in a number of programming levels larger than two, using a One-Pass Programming (OPP) scheme that results in a first readout reliability level. After programming the data, the storage circuitry is further configured to read the data from the first group, and program the data read from the first group to a second group of the memory cells, in a number of programming levels larger than two, using a Multi-Pass Programming (MPP) scheme that results in a second readout reliability higher than the first reliability level, and reading the data from the second group of the memory cells.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: sub-blocks divided with respect to a buffer page in which buffer cells are included; a voltage generator for, in a program operation of a selected sub-block among the sub-blocks, applying a first pass voltage to unselected word lines connected to the selected sub-block, and applying a second pass voltage lower than the first pass voltage to unselected word lines connected to an unselected sub-block; and a buffer line circuit for selectively turning on or turning off the buffer cells by selectively applying a turn-on voltage or a turn-off voltage to buffer lines connected to the buffer cells. A position of the buffer page is set as a default according to a physical structure of memory cells included in the sub-blocks, and is reset according to an electrical characteristic of the memory cells.

Abstract: Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.

Abstract: Image encoding within a pixelated privacy mask area is adapted in order to reduce flickering during movement of a camera. Motion vectors are set equal to the movement of the camera, and residuals are set to zero, thereby encoding pixel blocks within the privacy mask area as copies of corresponding pixel blocks in a reference image.

Abstract: A semiconductor memory device includes a memory string and a control logic. The memory string is connected between a common source line and a bit line and includes at least one first select transistor, a plurality of memory cells, and a plurality of second select transistors. The control logic is configured to apply a first voltage to a first group among second select lines respectively connected to the second select transistors, float a second group among the second select lines and then apply an erase voltage to the common source line, during an erase operation.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

Abstract: A memory device is provided. The memory device includes an array of memory cells arranged, a plurality of word lines, and a peripheral circuit configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells, perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation; and at a same time, perform a NGS operation on a memory cell in an unselected row of memory cells coupled to an unselected word line of the word lines. The unselected word line is adjacent to the selected word line.

Abstract: A data storage device including, in one implementation, a non-volatile memory and a controller. The non-volatile memory includes a memory block. The memory block includes a plurality of word lines that are written sequentially from a first end of the memory block to a second end of the memory block. The controller is coupled to the non-volatile memory. The controller is configured to determine a last written word line of the memory block. The controller is also configured to set a non-selected word line voltage based on the last written word line of the memory block. The controller is further configured to apply the non-selected word line voltage to non-selected word lines of the memory block.

Abstract: A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, a first bit line, a second bit line and a first source line. The first bit lines extends in a first direction, and is coupled to the first memory cell, the second memory cell and the first select transistor. The second bit line extends in the first direction, and is coupled to the first select transistor. The first source line extends in the first direction, is coupled to the first memory cell and the second memory cell, and is separated from the first bit line in a second direction different from the first direction.

Abstract: Disclosed is a data transfer system capable of accelerating data transmission between two chips. The data transfer system includes: a master system-on-a-chip (SoC) including a master transmission circular buffer and a master reception circular buffer; and a slave SoC including a slave reception circular buffer and a slave transmission circular buffer. The slave/master reception circular buffer is a duplicate of the master/slave transmission circular buffer; accordingly, the write pointers of the two corresponding buffers are substantially synchronous and the read pointers of the two corresponding buffers are substantially synchronous as well. In light of the above, the read and write operations of the master/slave transmission circular buffer can be treated as the read and write operations of the slave/master reception circular buffer; therefore some conventional data reproducing procedure(s) for the data transmission can be omitted and the data transmission is accelerated.