Abstract: A memory device that includes a memory array, a program circuit, a verify circuit and a controller is introduced. The program circuit is configured to apply a program pulse to at least one memory cell to set the at least one memory cell to a target state. The verify circuit is configured to perform a verify operation to determine whether the at least one memory cell reaches the predetermine threshold and to determine a number of failed memory cells among the at least one memory cell in response to determining that at least one of the at least one memory cell does not reach the target state. The controller is configured to adjust the program pulse according to the number of the failed memory cells to generate an adjusted program pulse that is applied to the failed memory cells to set the failed memory cells to the target state.

Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.

Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprising performing a read operation of one or more memory cells neighboring a target memory cell, thereby determining a data pattern of the one or more neighboring memory cells, storing the data pattern and, during a program operation of the target memory cell, adjusting a verify voltage level according to the stored data pattern of the one or more neighboring memory cells.

Abstract: A memory device includes a plurality of planes, a row driver and a controller. A method of programming the memory device includes in a program operation, the row driver applying a program pulse to a plurality of memory cells of a first plane of the plurality of planes; after the row driver applies the program pulse to the plurality of memory cells, the controller verifying if the plurality of memory cells have reached a predetermined program state; and if a preset number of the plurality of memory cells have failed to reach the predetermined program state after the plurality of memory cells have been verified for a predetermined number of times, the controller disabling the first plane.

Abstract: A data storage device includes a memory cell array comprising a plurality of pages each including K memory cells of which each stores N bits therein, where N and K are positive numbers greater than or equal to 2, wherein each of the pages stores one page data constituted by N subpage data each having K bits; a cache buffer receiving and caching N subpage data of first page data from a controller; and a page buffer sequentially buffering the respective cached N subpage data of the first page data and store the respective buffered N subpage data of the first page data in the memory cell array, wherein when a write operation for Mth subpage data of the first page data is completed, the cache buffer receives and caches Mth subpage data of second page data from the controller, where M is a positive number less than N.

Abstract: Provided herein may be a memory device and a memory system including the same. The memory device may include a logic group configured to generate and output driver control signals based on data received from an external device; and an internal power supply circuit configured to control current corresponding to an internal power supply voltage in response to the driver control signals, wherein the internal power supply circuit increases the current corresponding to the internal power supply voltage as the number of first data in the received data increases.

Abstract: The present disclosure provides a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a memory cell, a first logic transistor, and a second logic transistor. The semiconductor substrate includes a memory region and a logic region. The memory cell is disposed in the memory region. The first logic transistor is disposed in the memory region and disposed adjacent to the memory cell. The second logic transistor is disposed in the logic region. The first logic transistor is configured to control operation of the memory cell in response to a memory control signal provided by the second logic transistor.

Abstract: A request can be received to perform a read operation to retrieve data at a memory sub-system. A time to perform the read operation can be determined. A time a write operation was performed to store the data at the memory sub-system can be determined. An amount of time that has elapsed since the time the performance of the write operation until the time to perform the read operation can be determined. A read voltage from a plurality of read voltages can be selected based on the amount of time that has elapsed. The read operation can be performed to retrieve the data by using the read voltage.

Abstract: A method for operating a plurality of memory cells includes performing a read operation to each of the plurality of memory cells. If at least one memory cell of the plurality of memory cells is determined to be in a programmed state, perform an erasing test operation to the at least one memory cell with an initial erase voltage being applied to the erase line, and perform a verification operation to the at least one memory cell. If the cell current is smaller than the reference current, generate an intermediate erase voltage by adding a step voltage to an erase voltage currently used, and perform the erasing test operation to the at least one memory cell with the intermediate erase voltage being applied to the erase line. Performing the verification operation to the at least one memory cell again.

Abstract: According to one configuration, a monitor resource monitors conveyance of content streaming over a shared communication link between a server resource and a communication device, the communication device requesting segments of the content from a manifest file. Monitoring as described herein can include intercepting and inspecting data packets associated with conveyance of the content over the shared communication link. An analyzer resource analyzes bandwidth attributes of streaming the content over the shared communication link. Based on the attributes of streaming the content (such as bandwidth, adaptive bit rate, etc.) over the shared communication link, the monitor resource generates a report indicating a link quality provided to the communication device via the shared communication link conveying the stream of content.

Abstract: There are provided a memory controller for performing a program operation and a memory system having the memory controller. The memory system includes a memory device including first and second planes each including a plurality of m-bit (m is a natural number of 2 or more) multi-level cell (MLC) blocks; and a memory controller for allocating a first address corresponding to a first MLC block of the m-bit MLC blocks in which first m-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the m-bit MLC blocks in which second m-bit MLC data is to be programmed, and transmitting the allocated addresses and logical page data included in the m-bit MLC data to the memory device. The memory controller differently determines a transmission sequence of the logical page data according to whether the addresses correspond to the same plane among the planes.

Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Abstract: According to an embodiment, a semiconductor memory device includes first and second memory cells and a controller. In a program operation, the controller applies a first voltage to a select gate line at a first timing, applies a second voltage to a select gate line at a second timing, applies a third voltage to a word line at a third timing, and applies a fifth voltage to a word line at a fifth timing. In a program operation when the first memory cell is selected, a time between the second timing and the third timing is a first time. In a program operation when the second memory cell is selected, a time between the second timing and the third timing is a second time different from the first time.

Abstract: Methods of operating a memory, and memory configured to perform similar methods, may include applying a first plurality of programming pulses to control gates of a plurality of memory cells during a particular programming operation and applying a second plurality of programming pulses to the control gates of the plurality of memory cells during a subsequent programming operation, wherein the first plurality of programming pulses have a particular slope, and wherein the second plurality of programming pulses have a different slope less than the particular slope. Methods of configuring a memory may include characterizing a read window budget for a programming operation of the memory as a function of a programming step voltage for a plurality of memory cell ages.

Abstract: A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.

Abstract: Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device, before a second programming pass of the programming operation is performed on the memory cell, determines information about a first programming distribution and a second programming distribution of the memory cell, the first programming distribution corresponding to a first page type and the second programming distribution corresponding to a second page type. The processing device adjusts, using the information, a placement of the first programming distribution relative to the second programming distribution that balances a bit error rate (BER) between the first page type and the second page type.

Abstract: In one aspect of programmed state verification in accordance with the present description, the voltage levels on bitlines of non-target storage cells are each boosted by applying a non-zero offset or delta value, ?V, to the bitlines of non-target storage cells during a precharge subinterval. A bitline verification voltage applied to a bitline of a target storage cell causes the voltage of the bitline to ramp up from the boosted ?V value. As a result, starting from an initial value which is the higher or boosted ?V value, the bitline voltage ramps up more quickly during the precharge subinterval to the bitline verification voltage level to improve system performance. In addition, the bitline verification voltage applied to bitlines of target storage cells during the precharge subinterval, can be at a relatively high value to maintain the accuracy of program state verification.

Abstract: A controller for controlling a non-volatile memory apparatus including page groups each including a plurality of pages is configured to select a target page group from the page groups, wherein the target page group includes at least one invalid page and at least one valid page, select, as a target threshold voltage distribution, a lower threshold voltage distribution of two adjacent threshold voltage distributions distinguished by an invalid read voltage, wherein the invalid read voltage is a read voltage for distinguishing between data stored in the invalid page, select, as a target memory cell, a memory cell located in the target threshold voltage distribution among a plurality of memory cells configuring the target page group, and control the non-volatile memory apparatus to perform an adjustment program operation for raising a threshold voltage of the target memory cell as much as a first voltage.

Abstract: A method for programming a non-volatile memory in a programming operation is provided. The non-volatile memory has a number of cells and each of part of the cells store data having at least 2 bits at least corresponding to a first page and a second page. The method includes the following steps. At least one programming pulse is provided. At least one first program-verify pulse is provided. A program-fail-reference signal is enabled. At least one second program-verify pulse is provided after enabling the program-fail-reference signal.

Abstract: An electro-optical device includes a first signal line, a second signal line, and a third signal line, a signal line drive circuit configured to supply a first image signal, a polarity of which is inverted with reference to a predetermined voltage in a predetermined cycle, to the first signal line in a first writing period, supply a second image signal to the second signal line in a second writing period, and supply a third image signal to the third signal line in a third writing period, a pre-charge circuit that includes a one-channel type transistor and is configured to supply a pre-charge signal to the third signal line in a pre-charge period overlapping the second writing period, and a timing control circuit configured to change a start timing of the pre-charge period in accordance with a polarity of the first image signal.

Abstract: Techniques are provided to implement intelligent test case management for system integration testing in a continuous development and integration environment. For example, a system integration testing (SIT) tool obtains feature information regarding features within a feature space of a computing system and an operational status of the features. The SIT tool obtains a plurality of test cases associated with a given feature of the computing system, wherein each test case is mapped to a set of one or more features within the feature space, which are utilized by the test case to execute a test procedure to test the given feature. The SIT tool selects each test case among the plurality of test cases, which is mapped to features that have an active operational status. The SIT tool executes the selected test cases to test the given feature.

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads and a memory cell array, and a peripheral circuit region including second metal pads, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted. The peripheral circuit region is vertically connected to the memory cell region by the metal pads directly.

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

Abstract: A data storage apparatus includes a nonvolatile memory device including a plurality of memory blocks in which a plurality of word lines to which one or more pages are coupled are arranged, a data buffer configured to buffer data to be stored in the one or more pages of the nonvolatile memory device, and a processor configured to detect, when a sudden power off (SPO) occurs, one or more first pages in which an interference has occurred in a memory block in use and store data corresponding to the one or more first pages in which the interference has occurred among the data buffered in the data buffer in a backup memory block of the nonvolatile memory device.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

Abstract: Methods, systems, and devices for memory device with a dynamic fuse array are described. Techniques and apparatus are described herein for storing an address of a set of the array of latches that is associated with a set of the array of fuses. A se of an array of fuses may include a first portion for indicating the value of the parameter and a second portion for indicating an address of a set of the array of latches that is to receive the parameter stored in the first portion. An enabled set of fuses may indicate that the block is storing a value of a parameter for operating the memory device. By storing the address for the set of the array latches in the set of the array of fuses, a memory device may have a dynamic mapping between the array of latches and the array of fuses. Such a dynamic mapping may reduce an area used by the array of fuses and may make some parameters modifiable.

Abstract: A memory device and an operating method thereof are provided. A memory device includes a memory cell array including a plurality of strings, a voltage generating circuit configured to apply a turn-on voltage to the plurality of strings during a predetermined time period during a channel initialization operation of a read operation of a selected string among the plurality of strings, and control logic configured to set the predetermined time period of applying the turn-on voltage to the plurality of strings and to control the voltage generating circuit to apply the turn-on voltage to the plurality of strings during the predetermined time period, wherein the control logic sets the predetermined time period corresponding to the selected string as a first time period and the predetermined time period corresponding to unselected strings among the plurality of strings to be shorter than the first time period.

Abstract: A nonvolatile memory device includes a memory cell array that includes memory cells arranged in rows and columns, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines and includes first transistors configured to sense voltages of the bit lines and second transistors configured to invert and sense the voltages of the bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted.

Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

Abstract: Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.

Abstract: A fail bit number counting circuit includes a data transfer circuit configured by a series circuit in which switch elements turned on for calculation result data indicating a pass bit from each page buffer portion and turned off for calculation result data indicating a fail bit are connected in series; a control circuit inputs a counting enable signal to one input terminal of the data transfer circuit, and sequentially transfers the counting enable signal till the next switch element being turned off via the series circuit corresponding to a clock with a prescribed cycle; and the fail bit number counting circuit includes a clock counter by which the number of clocks till the counting enable signal reaches the other output terminal of the data transfer circuit after the counting enable signal is input to one input terminal of the data transfer circuit is counted as a fail bit number.

Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

Abstract: According to an embodiment, a memory system including: a semiconductor memory configured to store data, a memory controller configured to issue a first command to suspend a first operation to the semiconductor memory which is executing the first operation, wherein the memory controller is configured to prohibit the issuance of the first command until a time in which the first operation is executed passes a first threshold, acquire a status of the semiconductor memory which is executing the first operation, and update the first threshold to a second threshold in accordance with the status.

Abstract: A semiconductor memory device includes memory cells, a word line, and a controller. The controller is configured to: execute a first program operation in which a first program voltage is applied to the word line; execute a second program operation in which the first program voltage is applied to the word line, when a resumed first verify operation ends; and execute a third program operation in which a second program voltage higher than the first program voltage is applied to the word line, after a resumed second verify operation.

Abstract: Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells.

Abstract: A semiconductor device 50 of the invention includes a supply voltage VCC, a plurality of registers 14, a PMOS transistor P, an AND gate 12, and a determination circuit 16. The registers 14 include a first register and a second register. The first register can keep data, and the second register can keep a check bit. The PMOS transistor P and the AND gate 12 are both connected between the supply voltage VCC and the registers 14, and both control the supply from the supply voltage VCC to the registers 14. The determination circuit 16 determines whether the check bit kept in the second register is correct or not in a DPD (deep-power-down) mode. An operating margin of the second register is worse than that of the first register. While the determination circuit 16 determines that the check bit kept in the second register is incorrect, the PMOS transistor P provides the supply voltage VCC to the registers 14.

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

Abstract: A semiconductor memory device includes a first memory transistor, a first wiring connected to a gate electrode of the first memory transistor, a connection transistor connected to the first wiring, and a second wiring connected to the connection transistor. In a first write operation for the first memory transistor, during a first time period, a voltage of the first wiring increases to a first voltage and a voltage of the second wiring increases to a second voltage larger than the first voltage, and during a second time period directly after the first time period and directly after the connection transistor is turned ON, the voltage of the first wiring increases to a third voltage larger than the first voltage and smaller than the second voltage, and the voltage of the second wiring decreases to a fourth voltage larger than the first voltage and smaller than the second voltage.

Abstract: Provided herein may be a memory device and a memory system including the same. The memory device may include a logic group configured to generate and output driver control signals based on data received from an external device; and an internal power supply circuit configured to control current corresponding to an internal power supply voltage in response to the driver control signals, wherein the internal power supply circuit increases the current corresponding to the internal power supply voltage as the number of first data in the received data increases.

Abstract: Method of operating an integrated circuit device might include applying a first voltage level to a first conductor while applying a second voltage level to a second conductor, applying a third voltage level to the first conductor while applying a fourth voltage level to the second conductor, and applying a fifth voltage level to the first conductor while applying the second voltage level to the second conductor. The second voltage level might correspond to a target voltage level for the second conductor. A difference between the third voltage level and the first voltage level might have a polarity opposite the polarity of a difference between the fourth voltage level and the second voltage level, and the same polarity of a difference between the fifth voltage level and the first voltage level. The fifth voltage level might correspond to a target voltage level for the first conductor.

Abstract: A memory system includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to apply a read voltage to a selected word line coupled to a selected memory cell among the memory cells, and apply a pass voltage to unselected word lines coupled to unselected memory cells other than the selected memory cell among the memory cells, during a read operation; and a controller configured to control the peripheral circuit, and apply a variable voltage level of the pass voltage based on status information of a target memory block which is the target of the read operation.

Abstract: The system may include a digital-to-analog converter configured to convert a digital signal to an analog signal. The system may include sample/hold circuits configured to receive and store the analog signal. The system may include an address controller configured to regulate which sample/hold circuits propagate the analog signal. The sample/hold circuits may be configured to feed the analog signal to devices of a memory array. The system may include an output circuit configured to program the devices by comparing currents of the devices to a target current. In response to one or more of the currents of the devices being within a threshold range, the output circuit may discontinue programming the corresponding devices. In response to one or more of the currents of the devices not being within the threshold range, the output circuit may continue programming the corresponding devices.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.

Abstract: A control device for a non-volatile memory express (NVMe) over fabric architecture is provided. The control device comprises a network adapter and a processor coupled to the network adapter by a bus. Data is transmitted between the control device and a storage device in the NVMe over fabric architecture. The processor is configured to obtain an available storage space of the storage device, determine whether a storage space required by a first data to be transmitted according to a first data read/write command is equal to or less than the available storage space, and send the first data read/write command to the storage device if the storage space required by the first data is equal or less than to the available storage space and suspend sending of the first data read/write command if the storage space occupied by the first data is greater than the available storage space.

Abstract: There are provided a memory device and an operating method thereof. A memory device includes: a peripheral circuit for decreasing threshold voltages of memory cells included in a selected memory block and then performing an erase verify operation for detecting a threshold voltage distribution of the memory cells, wherein the peripheral circuit applies an erase pulse to a well, bit lines or source line in which the selected memory block is included a preset number of times; and a control logic for outputting a voltage setup code according to the threshold voltage distribution of an erase status, which is detected by the erase verify operation.

Abstract: A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.

Abstract: An electro-optical device includes a pre-charge circuit configured to supply a pre-charge signal to a first and second signal line at different timings based on a pre-charge control signal, and an inspection circuit configured to output, to the pre-charge circuit, an inspection control signal indicating whether a target is to be inspected in an inspection operation. The pre-charge circuit includes a first switch, an electrical coupling state between the first signal line and a pre-charge power supply line based on a first coupling control signal, a second switch, an electrical coupling state between the second signal line and the pre-charge power supply line based on a second coupling control signal, a first signal to output the first coupling control signal to the first switch, and a second signal to output the second coupling control signal to the second switch based on the inspection control signal and the pre-charge control signal.