Abstract: A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line.

Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.

Abstract: A method of operation in a non-volatile memory device, including executing a memory operation with respect to a portion of a non-volatile memory device, and measuring a current corresponding to current drawn by at least the portion of the non-volatile memory device during the memory operation. An age metric is determined for at least the portion of the non-volatile memory device based on age criteria including a characteristic of the measured current. In accordance with a determination that the age metric satisfies one or more predefined threshold criteria, one or more configuration parameters associated with the non-volatile memory device are adjusted. After the adjusting, data is read from and data to the portion of the non-volatile memory device according to the one or more adjusted configuration parameters.

Abstract: A data storage device includes a memory including a plurality of storage elements. The memory is configured to read a group of the storage elements using a first read voltage to obtain a first plurality of bit values. A controller is coupled to the memory. The controller is configured to initiate a first error correction code (ECC) procedure on the first plurality of bit values. In response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values, and to change one or more values of the first plurality of bit values to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.

Abstract: A system including a state set module to arrange states of a memory cell in three sets. The memory cell stores three bits when programmed to a state. Each set includes three rows of bits. In a set, a row includes one of the three bits of the states. The first, second, and third rows of the first, second, and third sets include a first number of state transitions. The second, third, and first rows of the first, second, and third sets include a second number of state transitions. The third, first, and second rows of the first, second, and third sets include a third number of state transitions. A write module writes first, second, and third portions of data to a plurality of memory cells, each memory cell storing the three bits when programmed to a state, using states selected respectively from the first, second, and third sets.

Abstract: Devices, methods, and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row driver to turn on and drive appropriate voltages to the matrix array.

Abstract: A high voltage switch operates in response to a first drive voltage and a second drive voltage higher than the first drive voltage. The high voltage switch comprises a PMOS transistor transmitting the second drive voltage to an output terminal according to a voltage applied to its gate, a first depletion mode transistor providing the second drive voltage to the PMOS transistor according to an output signal fed back from the output terminal, a second depletion mode transistor receiving the second drive voltage through one end and providing a switching voltage to another end according to a switching control signal, and a level shifter providing the switching voltage to a gate of the PMOS transistor according to an enable signal and a reverse enable signal.

Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

Abstract: A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.

Abstract: A data transfer circuit includes a plurality of first lines, a second line suitable for receiving data from a first line selected among the first lines, a third line suitable for transferring data to the first line selected among the first lines, a plurality of driving units, each suitable for driving the second line based on the data from the corresponding first line in a first operation, and a plurality of connection units, each suitable for coupling the third line to the corresponding first line when the corresponding first line is selected in a second operation.

Abstract: A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.

Abstract: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.

Abstract: Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.

Abstract: A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a discontinuous channel in at least one string. The system may include NAND flash memory cells composed of junctionless transistors, and has a set of wordlines. During program operation, a selected wordline of the set of wordlines is biased at a program voltage, and wordline voltage low enough to suppress the formation of source/drains is applied on at least one word line on a source side of the selected wordline such that a channel isolation occurs thereby causing the discontinuous channel in the at least string.

Abstract: A semiconductor device comprises a memory cell array comprising memory cells coupled to word lines and bit lines, a voltage generator suitable for generating a drive voltage to be applied to a selected word line, and a control logic suitable for detecting the number of pulses of a program voltage received from the memory cell array in a program operation, storing bias information corresponding to the detected number of pulses in a register, and controlling a level of the program voltage for a subsequent program operation based on the bias information.

Abstract: A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second type are different, and the controller is configured to control the first memory and the second memory according to substantially the same command sequence.

Abstract: A method for erasing a first sub-block of a plurality of sub-blocks included in a block of a non-volatile memory device, wherein the first sub-block includes at least one word line, includes applying an erase voltage to a substrate, applying a third voltage lower than the erase voltage to the word line of the first sub-block, applying a first voltage at least one word line adjacent to the word line of the first sub-block, and applying a second voltage that is the same as or similar to the erase voltage to the other word lines, where the first voltage has a level between the third voltage and the second voltage.

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Abstract: A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit. The data read detector generates a detection signal according to transition points of a sense amplifier enable signal and a sense amplifier latch signal. The cut-off signal generator delays the detection signal a delay time to generate a cut-off signal, wherein a start-up time of the cut-off signal is decided by the detection signal and the delay time. The output stage circuit starts or stops to provide a bias-voltage providing signal according to the cut-off signal.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells. The staircase voltage generator generates a staircase voltage having a staircase waveform that varies in at least two steps. The decode and level shift circuit selects one of said plurality of bit lines and applies the staircase voltage as a program voltage to the selected bit line.

Abstract: Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.

Abstract: According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output potentials of the potential generating circuit by receiving a first control signal and apply the selected output potential to a first signal line. The second potential selection circuit applies a potential of the first signal line to a second signal line connected to the row decoder by receiving a second control signal. The first discharge circuit is arranged in the first potential selection circuit. The second discharge circuit is arranged in the second potential selection circuit.

Abstract: Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.

Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.

Abstract: A nonvolatile memory device includes a discharge circuit configured to selectively connect circuit nodes to discharge terminals through corresponding discharge paths, and an accumulation device for accumulating electric charge. A driving circuit is for driving the discharge circuit in such a way to connect at least a part of such circuit nodes to the discharge terminals if the value of the external supply voltage falls below a corresponding threshold. A supply circuit is for supplying the driving circuit with an intermediate supply voltage. Each one of the intermediate supply voltages is the corresponding external supply voltage when the value of the external supply voltage is higher than the corresponding threshold, or it is an internal voltage locally generated by the supply circuit by exploiting the electric charge stored by the accumulation device when the value of the external supply voltage is lower than the corresponding threshold.

Abstract: A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.

Abstract: A semiconductor memory device configured to apply a temperature-compensated word line voltage to a word line during a data read operation includes a memory cell array including a plurality of word lines, a plurality of non-volatile memory cells connected to the word lines, and a word line voltage application unit configured to apply a temperature-compensated read voltage to a selected word line and to apply a temperature-compensated pass voltage to at least one unselected word line during a read operation.

Abstract: A method for operating a semiconductor structure is provided. The semiconductor structure includes a first conductor extending in a first direction, a second conductor extending in a second direction different from the first direction, and a dielectric layer between the first conductor and the second conductor. The method for operating the semiconductor structure comprises following steps. A current is provided to flow in the first direction in the first conductor.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include two or more drain select lines, of which a first drain select line is coupled to a drain select transistor in a first sub-block of a first block and to a drain select transistor in a first sub-block of a second block. A second drain select line in the apparatus may be coupled to a drain select transistor in a second sub-block of the first block and to a drain select transistor in a second sub-block of the second block. Other apparatuses and methods are described.

Abstract: A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled, and an address decoder coupled to the global word lines and a block word line to which gates of the normal pass transistors are coupled in common, wherein the address decoder gradually increases a voltage, obtained by subtracting a voltage of the global word lines from a voltage of the block word line, when an erase voltage is provided to a channel of the plurality of memory cells.

Abstract: A semiconductor device including an internal command generator and a bias generator is provided. The internal command generator generates first to fourth internal command signals sequentially enabled in synchronization with pulses of an external program signal. The first internal command signal controls a read operation for reading out data stored in memory cells, and the second and third internal command signals control a program operation for programming the memory cells. The bias generator generates a read bias signal for controlling a level of an output voltage signal, which is applied to an internal circuit, in response to the first and fourth internal command signals.

Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

Abstract: Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.

Abstract: A first circuit is coupled to a second circuit, which is coupled to a third circuit. A high voltage value of a first input signal and of a first output signal of the first circuit are equal, and are less than a high voltage value of a second output signal of the second circuit. A low voltage value of the first input signal is higher than a low voltage value of the first output signal. A high voltage value of the second output signal and of a third output signal of the third circuit are equal. The low voltage value of the first output signal, the second output signal, and the third output signal are equal.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.

Abstract: A transfer transistor includes a pair of first diffusion regions and a gate electrode layer. The pair of first diffusion regions are formed in a surface of a semiconductor substrate, and are each connected to a contact. The gate electrode layer is formed on the semiconductor substrate via a gate insulating layer and has a pair of openings each surrounding the contact.

Abstract: The present inventive concept provides a driving method of memory controller controlling nonvolatile memory device using variable resistive element. The memory controller may control a plurality of first memory devices and a second memory device. A number of write drivers in the second memory device may be driven when a number of first memory devices among the plurality of first memory devices are used. A different number of write drivers in the second memory device may be driven when a different number of first memory devices among the plurality of first memory devices are used.

Abstract: In a method for boosting a word line signal, the word line signal is transitioned from a first voltage value of the word line signal to a second voltage value of the word line signal, thereby turning on a first transistor. The first transistor and a second transistor turn on a third transistor. The third transistor causes the word line signal at a first terminal of the third transistor to reach a voltage value at a second terminal of the third transistor, thereby causing the word line signal to reach the voltage value faster than without the third transistor. The first transistor and the second transistor are coupled in series.

Abstract: A method includes, in a data storage device, receiving a read command to read a portion of a wordline of a memory. The method also includes determining a first and a last storage element of the wordline to identify a set of storage elements. The method includes determining a first set and a second set of sense amplifiers of multiple sense amplifiers coupled to the wordline. The first set of sense amplifiers is coupled to the set of storage elements and the second set of sense amplifiers is coupled to one or more storage elements of the wordline other than the first set of storage elements. The method includes reading data by applying a read voltage to the wordline and providing a sense enable signal to each sense amplifier of the first set of sense amplifiers while each sense amplifier of the second set of sense amplifiers is disabled.

Abstract: Writing data to a thermally sensitive memory device, including: receiving a physical layout of the thermally sensitive memory device; receiving the direction of airflow across the thermally sensitive memory device; selecting an address for writing data to the thermally sensitive memory device in dependence upon the physical layout of the thermally sensitive memory device and the direction of airflow across the thermally sensitive memory device; and writing data to the selected address of the thermally sensitive memory device.

Abstract: A level shift circuit includes: a latch circuit (Q5, Q6, Q7, Q8) including first (Q5, Q7) and second (Q6, Q8) inverter circuits; a first input MOS transistor (Q1) operating in accordance with an input signal; a second input MOS transistor (Q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control MOS transistor (Q9). The latch circuit (Q5, Q6, Q7, Q8) outputs a voltage having been converted from the input voltage in level. Each of the first and second input MOS transistors (Q1, Q2) receives the input signal at its gate terminal, and drives the latch circuit (Q5, Q6, Q7, Q8) in accordance with the input signal. The current-voltage control MOS transistor (Q9) is provided between the input MOS transistor (Q1, Q2) and the latch circuit (Q5, Q6, Q7, Q8), and is driven in accordance with an inversion operation of the latch circuit by receiving an input of the control voltage at its gate terminal.

Abstract: The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.

Abstract: A semiconductor device having a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell, so that the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.

Abstract: A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources.

Abstract: A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.

Abstract: Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage.

Abstract: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.

Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.