Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

Abstract: A method for writing data to a memory module, the method may include determining to write a representation of a data unit to a retired group of memory cells; searching for a selected retired group of memory cells that can store a representation of the data unit without being erased; and writing the representation of the data unit to the selected retired group of memory cells.

Abstract: Apparatuses, systems, and methods are disclosed for dynamic read operations. An on-die controller monitors one or more read statistics during a read operation for data of a non-volatile memory die. An on-die controller determines whether one or more read statistics satisfy a threshold for a read operation. An on-die controller dynamically modifies a read operation based on determining that one or more read statistics fail to satisfy a threshold.

Abstract: A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.

Abstract: A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data.

Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.

Abstract: A decoding method and a storage controller for a rewritable non-volatile memory module are provided. The method includes choosing a target word line among a plurality of word lines, wherein a plurality of target memory cells of the target word-line are programmed; reading the target memory cells by respectively using different X read voltage sets, so as to obtain X Gray code count deviation summations, wherein the X read voltage sets and the corresponding X Gray code count deviation summations are all ordered based on a first predefined order; and choosing one of the X read voltage sets as an optimized read voltage set according to the X Gray code count deviation summations.

Abstract: A data storage device includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.

Abstract: Disclosed herein is a method for trimming a voltage regulator by a trimming circuit comprising a voltage divider configured to divide a divide reference voltage according to a divider code and to output a first divider output voltage, a comparator configured to receive the first divider output voltage and a compare reference voltage and to output an output voltage of the comparator by comparing the first divider output voltage and the compare reference voltage and a logic unit configured to output the divider code to the voltage divider and to determine a final divider code based on the output voltage of the comparator.

Abstract: A memory device includes a plurality of memory blocks, each block with multiple memory cells. Each memory block has an address and a block read threshold. The plurality of memory blocks is partitioned into clusters based on block read thresholds. The memory device also has a look-up table for storing information associating each cluster of memory blocks with a corresponding cluster read threshold. The look-up table further includes cluster boundaries defined in values of device status parameters. The memory device is configured to receive a read command to read a memory block with a read address and identify a cluster for the memory block with the read address. The memory device is also configured to select a cluster read threshold for the identified cluster from the look-up table, and use the selected cluster read threshold to perform a read operation of the memory block.

Abstract: According to one embodiment, a memory device includes: a memory cell; a read driver configured to supply a read pulse to the memory cell at the time of a read operation for the memory cell; a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse; a hold circuit configured to hold a peak value of the second signal; and a sense amplifier circuit configured to read data from the memory cell based on the peak value.

Abstract: A machine-implemented method for managing a flash storage system includes determining a projected life value for each of a plurality of flash memory devices in the flash storage system, wherein the projected life value for at least one of the plurality of flash memory devices is higher than the projected life value of at least another one of the plurality of flash memory devices. The method also includes determining operating parameters for each of the plurality of flash memory devices based on the respective projected life values for the plurality of flash memory devices. The method also includes configuring the plurality of flash memory devices based on the determined operating parameters.

Abstract: The present disclosure includes apparatuses and methods related to refresh in memory. An apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage. The reference voltage can be determined by the threshold voltage being within a set margin of a second state.

Abstract: A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell.

Abstract: A semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines.

Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

Abstract: A system for characterising a NOR flash memory cell provided with a floating gate transistor, includes a voltage generator having an output connected to the gate electrode that generates as output an erase signal; and a dynamic measurement apparatus including a first channel connected to the gate electrode and a second channel connected to the drain electrode. The dynamic measurement apparatus generates on the first and second channels write signals and measures a current flowing in the drain electrode during the writing of the memory cell. Only the gate electrode of the floating gate transistor is connected to the voltage generator and to the dynamic measurement apparatus by a CMOS switch, which switches between a first position, where the output of the voltage generator is electrically coupled to the gate electrode, and a second position, where the first channel of the measurement device is electrically coupled to the gate electrode.

Abstract: A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. The floating gate is coupled to an array control gate/source line through the coupling capacitor. The first source is coupled to the array control gate/source line. The selection transistor has a selection gate, a second source, and a second drain. The selection gate is coupled to a word line. The second source is coupled to the first drain. The second drain is coupled to a bit line.

Abstract: A voltage regulator is provided that includes an error amplifier circuit having a reference voltage input port that receives a reference voltage, N input ports, N output ports, and N power transistors, where N is a positive integer that is greater than or equal to 2. Each of the power transistors has a gate that is connected to one of the N output ports. The error amplifier amplifies a difference between the reference voltage and each of N respective feedback voltages input to the N input ports, respectively, and outputs amplified voltages to the respective N output ports.

Abstract: Methods of operating a nonvolatile memory device include performing erase loops on a memory block using a first voltage, performing program loops on memory cells of the memory block using a second voltage, and increasing the first and second voltages based on program/erase cycle information for the memory cells. The first voltage may include an erase verification voltage and the second voltage may include a program voltage.

Abstract: A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.

Abstract: A method of programming a non-volatile memory device includes programming memory cells selected from the plurality of memory cells by increasing turn values of program loops based on an incremental step pulse program (ISPP) algorithm; detecting a first turn value of a first program loop wherein, in the first program loop, a first number or a first ratio of first unprogrammed memory cells is smaller than or equal to a first set value; calculating a second turn value of a second program loop based on the first turn value wherein, in the second program loop, a second number or a second ratio of second unprogrammed memory cells is expected to be smaller than or equal to a second set value, the second set value being smaller than the first set value; executing subsequent program loops on the unprogrammed memory cells up to the second program loop; detecting a third number or a third ratio of third unprogrammed memory cells in the second program loop; comparing the third number or the third ratio of the third unpro

Abstract: A system and method for separating clock recovery for a pseudowire communication. An incoming signal is received for a pseudowire communication. The incoming signal is separated into a first signal and a second signal. Packets within the first signal are ordered in a first register. A clock signal is extracted from the second signal in a second register to generate a modified clock signal. A delay is incurred during generating of the modified clock signal. The first signal is communicated utilizing the modified clock signal.

Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

Abstract: A monotonically increasing persistent counter is described that is persistent across reboots of a system in which it is incorporated. The described counter employs an event counter module that counts events that are generated by various event generators within the system. One type of event that can be counted by the described counter is a state change. In various implementations, the event counter module, when employed as a state change counter module, includes a state change counter that counts state changes, and a journal mode component which provides journaling functionality which makes it possible to accommodate large numbers of state changes while, at the same time, recover the counter in the event of a system failure. In at least some embodiments, one or both of the state change counter and the journal mode component are implemented using NOR flash memory.

Abstract: According to an exemplary embodiment, a III-nitride power conversion circuit includes a gate driver having a plurality of cascaded inverters, each of the plurality of cascaded inverters including at least one III-nitride transistor. At least one of the plurality of cascaded inverters has a cutoff switch and a III-nitride depletion mode load where the cutoff switch is configured to disconnect the III-nitride depletion mode load so as to prevent current from flowing from a supply voltage of the at least one of the plurality of cascaded inverters. The cutoff switch of the at least one of the plurality of cascaded inverters can be driven by one of the plurality of cascaded inverters. The III-nitride power conversion circuit can also include an output driver driven by the gate driver where the output driver has a segmented III-nitride transistor. Furthermore, a selector circuit can be configured to selectively disable at least one segment of the segmented III-nitride transistor.

Abstract: A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.

Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

Abstract: A circuit arrangement for measuring a load current provided to a load via a first load terminal of a load transistor is disclosed. In accordance with one example of the invention, the circuit arrangement includes a sense transistor coupled to the load transistor to provide a sense current representing the load current at a first load terminal of the sense transistor. The first load terminals of the load and the sense transistors are at respective floating electric potentials. A floating sense circuit coupled between the load terminals of sense transistor and load transistor, at least in one mode of operation the sense circuit receives the sense current and provides a floating signal representing the sense current. A non-floating measurement circuit is coupled to the sense circuit via a DC decoupling capacitor for transferring the floating signal representing the sense current to the non-floating measurement circuit.

Abstract: In a method of programming a nonvolatile memory device, a program operation is performed on a selected memory cell coupled to a selected word line in response to a program command, a negative bias voltage is applied to the selected word line, a verification pass voltage is applied to an unselected word line after the negative bias voltage is applied to the selected word line, and a first program verification voltage, which is higher than the negative bias voltage and lower than a ground voltage, is applied to the selected word line.

Abstract: A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an erase block for data retention based on the power-off decay rate.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: A semiconductor device includes a memory block including memory cells coupled between bit lines and a common source line and operated by voltages applied to word lines, and an operation control block suitable for performing an erase operation and a pre-program operation on the memory block, wherein the operation control block performs an erase level control operation after the erase operation is completed so that threshold voltages of the memory cells relatively close to the bit lines and threshold voltages of the memory cells relatively close to the common source line are distributed at different erase levels.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. The method includes, in response to one or more host read commands, reading data from a set of memory cells in a flash memory array in accordance with a first reading threshold voltage and performing an error correction process on the read data to produce error correction information. The method further includes determining, based on the error correction information, whether to adjust the first reading threshold voltage, and upon determining to adjust the first reading threshold voltage, setting the value of the first reading threshold voltage to a value greater or less than a current value of the first reading threshold voltage. In some implementations, the method further includes initiating a recalibration of the first reading threshold voltage when a predefined condition occurs.

Abstract: According to one embodiment, a semiconductor memory device includes: semiconductor member; electrode member; charge accumulation member; a memory unit; and a control unit. Memory cell is formed at each crossing portion of the semiconductor member and the electrode member. The memory unit retains information indicating that the memory cell belongs to first group or second group. The control unit performs first step and second step, when reducing the charge accumulated in the charge accumulation member. In the first step, first voltage is applied both between the semiconductor member and the electrode member of the first group and between the semiconductor member and the electrode member of the second group. In the second step, second voltage is applied between the semiconductor member and the electrode member constituting the memory cell belonging to the second group.

Abstract: A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of the memory storage module, wherein each of the plurality of lifetime specific LLR look-up tables comprises a plurality of LLRs representative of a specific point in the lifetime of the memory storage module for each of the plurality of soft-decision bits. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.

Abstract: Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

Abstract: In accordance with at least one embodiment, an onboard analog-to-digital converter (ADC) on a system-on-a-chip (SOC) is utilized to determine whether a charge pump output for a non-volatile memory (NVM) is correct or not. The SOC is directed to wait until the output is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the SOC such that the application can react to it.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a source line side a lower control voltage than that applied to a word line connected to a memory cell disposed most to a bit line side, of a plurality of word lines connected to at least a plurality of memory cells mutually written with data of an identical number of bits in a cell string.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs an external command signal. The semiconductor device compares the external command signal with a reference voltage signal to generate a refresh signal. The semiconductor device executes a refresh operation according to the refresh signal. The refresh signal is enabled if the reference voltage signal is not generated.

Abstract: A flash memory device uses a pair of parallely connected NMOS transistors with different voltage ratings to generate the reference current for the sense amplifier used in the read out operations. The reference current thus generated is temperature compensated with zero or near-zero temperature coefficient. In some embodiments, the pair of parallely connected NMOS transistors includes a high voltage NMOS transistor and a low voltage NMOS transistor or NMOS transistors with different gate oxide thicknesses.

Abstract: Provided are a semiconductor memory device, a memory system including the same, and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for reading least significant bit data and most significant bit data of neighboring memory cells adjacent to selected memory cells out of the plurality of memory cells, and generating pattern flag data using the least significant bit data and the most significant bit data and a control logic suitable for controlling the peripheral circuit to set a read voltage to be applied to the selected memory cells based on the pattern flag data.

Abstract: The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a number of program state combinations L corresponding to a group of memory cells configured to store a fractional number of data units per cell. The mapping can be based, at least partially, on a recursive expression performed in a number of operations, the number of operations based on a number of memory cells N within the group of memory cells and the number of program state combinations L.

Abstract: Methods and apparatuses for reduction of read disturb errors in a memory system utilizing modified or extra memory cells.

Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

Abstract: Apparatuses, systems, methods, and computer program products are provided for error correction. A soft read module is configured to obtain soft read information for a cell of a non-volatile memory medium. The soft read information may indicate a likelihood that a data value for the cell is correct. A reliability module is configured to associate the cell with a log-likelihood ratio (LLR) mapping from a plurality of LLR mappings based on one or more reliability characteristics for a set of cells that includes the cell. An LLR map module is configured to determine an LLR value based on the soft read information by using the LLR mapping.

Abstract: A semiconductor device includes a memory block including memory cells for storing program data and one or more flag cells for storing erase state information, an operation circuit suitable for performing a program operation, an erase operation, and a read operation on the memory cells and the flag cell, and a data conversion circuit suitable for encoding read data read from the memory cells based on the erase state information.

Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells, wherein the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to one of a number of program states, and wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states. A number of embodiments also include a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and determine soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.