Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

Abstract: Techniques are described for detecting a short circuit between a word line and a source line in a memory device, and to a method for recovering from such a short circuit. In one aspect, the short circuit is detected in a program operation when a selected word line completes programming after an unusually low number of program loops. A further check is performed to confirm that there is a short circuit. The short circuited word line is then erased and a recovery read is performed for previously-programmed word lines. In another aspect, a short circuit is detected in a read operation.

Abstract: A system stores data in data units in a cluster in a cloud computing system, the data stored in the data units being encrypted or unencrypted depending on whether encryption is enabled or disabled when storing data in the data units. The system identifies one or more data units to defragment and defragments the identified data units by writing the data from the identified data units to one or more new data units and by releasing the identified data units for storing new data. The system encrypts unencrypted data from the identified data units when writing the data from the identified data units to the one or more new data units.

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract: A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages coupled to word lines, respectively, peripheral circuits configured to, during a program operation, perform program, verify, and discharge operations on memory cells coupled to a word line selected from among the word lines, and a control logic configured to control the peripheral circuits such that, during the discharge operation performed after the verify operation, word lines, included in a region in which the program operation has not completed, and word lines, included in a region in which the program operation has completed, among the word lines, are discharged at different times.

Abstract: Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.

Abstract: A memory device is disclosed. The memory device includes a memory bit array comprising a plurality of memory bits, wherein each memory bit is configured to present an initial logic state when the memory device is powered on, and an erasion circuit, coupled to the memory bit array, and configured to alter an intrinsic characteristic of at least one of the memory bits so as to alter the initial logic state of the at least one memory bit.

Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.

Abstract: Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.

Abstract: A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.

Abstract: A semiconductor device includes a substrate, a dielectric layer and a floating gate. The dielectric layer disposed on the substrate. The floating gate disposed on the dielectric layer. After a first programming process, the floating gate is configured to store first electrons that are to be combined with ions from the dielectric layer. After a second programming process, the floating gate is configured to store second electrons, and a number of the second electrons is larger than a number of the first electrons.

Abstract: An erasing method of a single-gate non-volatile memory is provided. The single-gate non-volatile memory has a single floating gate. The erasing method includes applying a voltage to the drain without applying to the gate to create and control an inversion layer. Therefore the required erasing voltage is reduced and the erasing speed is improved to avoid the over-erase problem.

Abstract: Techniques for implementing a data management scheme for optimizing data storage are described herein. A deletion quantity or other metric relating to deletions of data within a first storage zone are tracked. Upon detection that the tracked deletion metric meets certain criteria, the data within the first storage zone are moved to a second storage zone. A verification of the data to be moved is also performed, and if such verification indicates that at least a portion of the data is corrupted, routines repairing and/or restoring at least the corrupted portion are initiated.

Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.

Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

Abstract: A method that allows integrating complementary metal oxide semiconductor (CMOS) transistors and a non-volatile memory (NVM) transistor on a single substrate is provided. The NVM transistor includes a gate stack containing a high-k tunneling gate dielectric, a floating gate electrode, a high-k control gate dielectric and a control gate electrode. The high-k tunneling gate dielectric is formed form a first high-k dielectric layer employed in formation of a gate dielectric for a p-type field effect transistor (FET), the floating gate electrode is formed from a capping material layer employed in annealing the first high-k dielectric layer, and the high-k control gate dielectric is formed from a second high-k dielectric layer employed in formation of a gate dielectric for an n-type FET.

Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.

Abstract: A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an output coupled to control gates of the NVM cells in a sector in the plurality of sectors. An address decoder is coupled to the control gate driver circuit. And a latch circuit is coupled between the address decoder and the control gate driver circuit. The latch circuit stores a first value, and based on the stored first value, the control gate driver circuit output is floating.

Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N?1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.

Abstract: A memory device includes a first memory string including a first selection transistor and a first memory cell, a second memory string including a second selection transistor and a second memory cell, a bit line electrically connected to the first memory string and the second memory string, and a control circuit configured to perform a collective write operation on the first memory cell and the second memory cell by applying a voltage to turn on the first transistor, a voltage to turn on the second transistor, and then a program voltage at the same time to gates of the first and second memory cells.

Abstract: Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.

Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract: Systems and methods are provided for unmapping unused logical addresses at mount-time of a file system. An electronic device, which includes a non-volatile memory (“NVM”), may implement a file system that, at mount-time of the NVM, identifies all of the logical addresses associated with the NVM that are unallocated. The file system may then pass this information on to a NVM manager, such as in one or more unmap requests. This can ensure that the NVM manager does not maintain data associated with a logical address that is no longer needed by the file system.

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to store a first page of data in a plurality of cells of the NAND flash memory in a first programming pass; and preserve the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.

Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.

Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier, a register, a controller. The memory cell array includes a memory cell. The sense amplifier connects to the bit line. The register holds write data, and a write voltage. The controller outputs a busy signal. The controller causes the register to hold the write data and the write voltage upon receiving the first command, and resumes the write operation based on the write data and the write voltage held in the register upon receiving the resumption command.

Abstract: A method of fabricating an embedded electronic device including charge trap memory cells that includes forming a tunnel insulation layer, a charge trap layer and a sacrificial insulation layer on a substrate having a first region and a second region. The tunnel insulation layer, the charge trap layer and the sacrificial insulation layer which are stacked on the second region of the substrate are selectively removed. A well region is formed in an upper region of the second region of the substrate. The sacrificial insulation layer remaining over the first region is removed to expose the charge trap layer remaining over the first region. A blocking insulation layer and a gate insulation layer are formed on the exposed charge trap layer over the first region and on the second region of the substrate, respectively.

Abstract: A method of operating a semiconductor memory device includes applying a read voltage to a selected word line on which a program operation is performed; applying a first pass voltage to at least one unselected word line adjacent to the selected word line; applying a second pass voltage to the at least one unselected word line when a first reference time elapses; and performing a read operation on memory cells connected to the selected word line according to the read voltage when a second reference time elapses.

Abstract: Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur.

Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area ?, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (?/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (?/pBL).

Abstract: A flash memory apparatus and an initialization method for programming operation thereof are provided. The initialization method includes: providing a plurality of increasing programming pulse voltages to operate a plurality of without program inhibit programming actions on memory cells of the flash memory, and operating a plurality of programming verification actions on the memory cells according to a programming verification voltage; obtaining a recorded programming voltage value according verified results of the programming verification actions; providing a plurality of increasing reading pulse voltages to operate a plurality of reading actions on the memory cells; obtaining a recorded reading voltage value according to read result of the reading actions; and obtaining an initial programming voltage and an incremental step programming pulse voltages according to the recorded programming voltage value, the recorded reading voltage value and a voltage value of the programming verification voltage.

Abstract: A semiconductor device includes a substrate having an element isolation region, a trench formed on the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on both ends of the gate electrode, wherein a pin is formed under the gate electrode between the active regions.

Abstract: A semiconductor device includes: a control block suitable for generating a clock control signal in response to a write training signal and a write-related information signal; and an input block suitable for receiving a data signal for a write training mode in response to the clock control signal and a clock signal.

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract: An information processing device includes a storage device that stores information, and a controller that adjusts a consumption of read time of reading information to be read per unit data amount according to the priority of the information to be read from the storage device and a permitted read time during which read of information from the storage device is permitted. The permitted read time varies according to the processing time of another control different from the control of the read.

Abstract: A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block.

Abstract: A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal.

Abstract: A memory device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom level of conductive strips, a plurality of intermediate levels of conductive strips, and a top level of conductive strips. A reference conductor is disposed in a level between the bottom level of conductive strips and a substrate, isolated from the substrate by a layer of insulating material, and isolated from the bottom level by another layer of insulating material. A plurality of vertical active strips is disposed between the plurality of stacks in electrical contact with the substrate, and with the reference conductor. Charge storage structures are disposed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate levels and the vertical active strips. A bias circuit is configured to provide different bias arrangements to the reference conductor and the substrate.

Abstract: A semiconductor device manufacturing method for etching a substrate having a multilayer film formed by alternately stacking a first film and a second film, and a photoresist layer to form a step-shaped structure is provided. The step-shaped structure is formed by repeatedly performing a first step of plasma-etching the first film by using the photoresist layer as a mask, a second step of exposing the photoresist layer formed on the substrate to a plasma generated from a processing gas containing argon gas and hydrogen gas by applying a high frequency power to a lower electrode while applying a negative DC voltage to an upper electrode, a third step of trimming the photoresist layer, and a fourth step of plasma-etching the second film.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A non-volatile memory includes a memory array, a row decoder, a column decoder, a write buffer and a sensing circuit. The column decoder includes a programming decoder and a reading decoder. The programming decoder is connected with n bit lines of the memory array. The reading decoder is connected with the n bit lines. During a program cycle, a programming control signal set is activated. Consequently, the programming decoder determines a selected memory cell, and a cell current generated by the selected memory cell flows to the write buffer through the programming decoder and a programming data line. During a read cycle, a reading control signal set is activated. Consequently, the reading decoder determines the selected memory cell, and the cell current generated by the selected memory cell flows to the sensing circuit through the reading decoder and a reading data line.

Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and includes a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.

Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.