Abstract: A fuse structure includes a substrate, a gate dielectric formed on the substrate, a gate electrode formed on the gate dielectric, and first and second source/drain regions formed on the substrate on opposite sides with respect to the gate electrode, wherein the gate dielectric is configured such that a plurality of oxygen vacancies trapping respective charges are formed upon application of a pulse to the gate electrode.

Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.

Abstract: A voltage control method and apparatus of a central bus in a power system are provided. The method comprises: S1: obtaining a predetermined voltage and a current voltage; S2: obtaining a first voltage adjustment of the generator and a second voltage adjustment of the dynamic reactive power compensation device; S3: sending the first voltage adjustment and the second voltage adjustment; S4: judging whether a current reactive power of the dynamic reactive power compensation device is between a first predetermined reactive power and a second predetermined reactive power; S5: if yes, obtaining a third voltage adjustment of the generator and a fourth voltage adjustment of the dynamic reactive power compensation device; S6: sending the third voltage adjustment and the fourth voltage adjustment; repeating steps S1-S7 after a predetermined period of time; S7: if no, repeating steps S1-S7 after the predetermined period of time.

Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.

Abstract: A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and first data corresponding to the first write command, and writing the first data into a third physical erasing unit in first physical erasing units; and if a usage frequency of a fourth physical erasing unit in the first physical erasing units is less than a predetermined value, performing a data arrangement operation corresponding to the first write command to copy second data stored by the fourth physical to at least one of second physical erasing units.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable multi-phase erasure in a storage device. The method includes performing an erase operation on a portion of one or more non-volatile memory devices, by performing a sequence of erase phase operations until an erase operation stop condition is satisfied. Each erase phase operation includes: performing an erase phase on the portion of the non-volatile memory devices using an erase voltage, and determining an erase phase statistic for the erase phase. For each erase phase operation in the sequence of erase phase operations, other than a first erase phase operation, the erase voltage used when performing the erase phase operation is equal to the erase voltage used when performing a prior erase phase operation in the sequence of erase phase operations plus an erase voltage increment based on the erase phase statistic for the prior erase phase operation.

Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.

Abstract: A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end connected to the substrate, has as its longer direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. Assuming at least one control gate electrode positioned in a lowermost layer of the plurality of control gate electrodes to be a first control gate electrode, the first control gate electrode comprises: a first portion; a second portion adjacent to the first portion; and a third portion connected to the first portion and the second portion.

Abstract: A semiconductor memory device includes a conductive layer on a source side; a first electrode layer provided on the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a semiconductor layer extending through the first electrode in a first direction from the conductive layer to the first electrode layer; a first semiconductor body provided between the conductive layer and the semiconductor layer, the first semiconductor body including first impurities; and a second semiconductor body provided between the conductive layer and the first semiconductor body, the second semiconductor body including second impurities with a higher concentration than a concentration of the first impurities in the first semiconductor body. A diffusion coefficient of the second impurities in the second semiconductor body is smaller than a diffusion coefficient of the second impurities in the first semiconductor body.

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Abstract: Technologies for clearing a page of memory include a memory device configured write a value to a block of memory cells in response to an activation signal. The memory device includes a row decoder responsive to a memory address to select a row of memory cells and a column decoder responsive to the activation signal to select one or more columns of memory cells. Additionally, a write driver of the memory device is configured to write a value to global input/output lines, which are connected to the selected memory cells in response to the activation signal and regardless of data received on a data input of the write driver.

Abstract: A semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate. The semiconductor device may include an operation circuit configured to perform an operation on memory cells included in the memory strings. The bit lines may be classified into a plurality of groups. The operation circuit may be configured to apply a voltage to bit lines of a selected group and set the common source line to a voltage level for the operation.

Abstract: Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a program operation, after the program voltage is applied to a selected one of the plurality of memory cells, the program voltage applied to the selected memory cell is discharged while the first pass voltage or the second pass voltage is applied to memory cells adjacent to the selected memory cell.

Abstract: A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.

Abstract: An operation method of a memory cell includes steps of applying a pre pulse before a read pulse is applied, wherein the pre pulse is larger than a maximum threshold voltage or less than a lowest threshold voltage.

Abstract: A memory device includes: a main block that includes a plurality of first pages that are accessible based on a multi-bit address; and a sub-block that includes a plurality of second pages that are accessible based on a portion of bits of the multi-bit address, and stores a replacement data for replacing entire or a portion of the data of an accessed first page among the plurality of the first pages in a second page that stores the same tags as the other bits of the multi-bit address among the accessed second pages.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar portion. The stacked body includes a first insulating layer provided on the substrate, a first electrode layer provided on the first insulating layer and including polycrystalline silicon, a second insulating layer provided on the first electrode layer, and a second electrode layer provided on the second insulating layer. The columnar portion includes a semiconductor layer extending in a stacking direction of the stacked body and a memory layer provided between the semiconductor layer and the stacked body. The first and second electrode layers respectively have a first thickness and a second thickness in the stacking direction, and the first thickness of the first electrode layer is thicker than the second thickness of the second electrode layer.

Abstract: A synapse circuit to perform spike timing dependent plasticity (STDP) operation is provided. The synapse circuit includes a memristor having a resistance value, a transistor connected to the memristor, and the transistor configured to receive at least two input signals. The resistance value of the memristor is changed based on a time difference between the at least two input signals received by the transistor.

Abstract: A method is suggested for determining a state of a cell structure, wherein the cell structure includes several memory cells, the method includes: (i) detecting a first condition in a predetermined number of memory cells; and (ii) determining the state of the cell structure by assigning a second condition to the memory cells that do not show the first condition.

Abstract: An information processing apparatus including a removable storage device for storing data includes a control unit that determines whether communication is possible with the storage device and, if communication with the storage device is determined not to be possible, prohibit data from being written to the storage device. When the information processing apparatus is started up, the control unit again determines whether communication is possible with the storage device to which the control unit prohibits data writing and permits data writing to the storage device if communication with the storage device is determined to be possible.

Abstract: According to one embodiment, a semiconductor memory device includes a word line and a driver. The word line coupled to a memory cell. The driver is configured to apply a voltage to the word line. When a voltage applied to the word line is changed from a first voltage to a second voltage, the driver applies a third voltage according to a voltage difference between the first voltage and the second voltage to the word line.

Abstract: In a non-volatile memory system, a fast bulk secure erase method for erasing data includes, in response to a secure erase command: applying charge to a portion of non-volatile memory in the non-volatile memory system, and performing an erase operation sufficient to remove charge from the portion of non-volatile memory to below an erase threshold. The applied charge is sufficient to program memory cells in the portion of non-volatile memory to above a pre-erase program threshold.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for providing a normal erase command or a fine erase command to the nonvolatile memory device, wherein the nonvolatile memory device performs a first normal erase loop in which a first normal erase voltage and an erase verify voltage are applied to erase target memory cells, according to the normal erase command, and performs a first fine erase loop in which a first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, according to the fine erase command.

Abstract: A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.

Abstract: Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.

Abstract: Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing an erase operation on a memory block including bottom dummy cells, a plurality of memory cells, top dummy cells and selection transistors arranged in a vertical direction with respect to a pipe gate, increasing threshold voltages of the top and bottom dummy cells at substantially a same time by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cells and a second soft program voltage greater than the first soft program voltage to the top dummy word line coupled to the top dummy cells, verifying the top and bottom dummy cells, and repeatedly performing the erase operation and increasing the threshold voltages by gradually increasing the first and second soft program voltages until the verifying of the top and bottom dummy cells passes.

Abstract: The invention relates to retrieving data from a storage system. One embodiment of the invention comprises receiving a write operation, establishing a correspondence relationship between a logic block address and a physical block address of the write operation, and determining whether a valid data percentage in a mapping table is greater than a predetermined threshold after the correspondence relationship is added in stored metadata of stored metadata.

Abstract: Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (LUNs). Memory management circuitry can be coupled to the non-volatile memory control circuitry and configured to allocate a write block cluster for host writes based on an information width of a host bus and a protocol of the host bus. The write block cluster can include one block from fewer than all of the LUNs.

Abstract: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

Abstract: A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.

Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.

Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.

Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from the write operation. The method further comprises populating at least one of one or more coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks. Additionally, the method comprises selectively writing the difference information in the coalescing memory buffers to the storage devices, based on a determination of fullness of the coalescing memory buffers. The coalescing memory buffers are separate from the storage devices.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for providing a normal erase command or a fine erase command to the nonvolatile memory device, wherein the nonvolatile memory device performs a first normal erase loop in which a first normal erase voltage and an erase verify voltage are applied to erase target memory cells, according to the normal erase command, and performs a first fine erase loop in which a first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, according to the fine erase command.

Abstract: According to example embodiments, a table management method includes determining whether a table associated with a page in at least one nonvolatile memory device needs to be recovered, performing a block scan operation on a block in the at least one nonvolatile memory device if the table needs to be recovered, recovering the table using a time difference read from each of a plurality of pages in the block during the block scan operation, and updating the recovered table to the at least one nonvolatile memory device. The table is associated with a page among the plurality of pages in the block. The time difference is time elapsed until a current page is programmed from program time of a previous page among the plurality of pages.

Abstract: An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed.

Abstract: A system includes a memory buffer to cache a non-volatile memory. The non-volatile memory stores a plurality of valid and obsolete variables in a plurality of valid and obsolete regions, respectively. The system further includes a journal region to track movement of valid variables and valid regions within the memory buffer utilizing alternating pairs of structure pointers to indicate at least portions of the plurality of valid and obsolete regions indicative of from where and to where the valid variables move during a write event.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for storage operations for a non-volatile medium. A control module may be configured to divide a storage procedure into multiple portions. An execution module may be configured to execute multiple portions of a storage procedure independently. A storage request module may be configured to satisfy a storage request for one or more storage elements of a storage procedure between at least a pair of portions of a storage procedure.

Abstract: An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.

Abstract: A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based on the determined erase mode.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an interconnect layer, a stacked body, an insulating layer, a semiconductor pillar, a charge storage layer and a first conductive unit. The stacked body is separated from the interconnect layer in a first direction. The stacked body includes a memory unit and a selection gate provided between the memory unit and the interconnect layer. The insulating layer is provided between the interconnect layer and the stacked body. The semiconductor pillar pierces the stacked body in the first direction. The charge storage layer is provided between the semiconductor pillar and the memory unit. The first conductive unit connects the semiconductor pillar and the interconnect layer. A width of the first conductive unit along a second direction perpendicular to the first direction is wider than a width of the semiconductor pillar along the second direction.

Abstract: Disclosed is a detection system for detecting fail block using logic block address and data buffer address in a storage tester, which is capable of comparing data read from SSD test without expected data buffer. The system comprises a device driver for controlling HBA; a request processor for reading the request to Root Complex and transmitting the result to a data engine; and the data engine for generating data to be transmitted to SSD and comparing the read data.

Abstract: The level shifter of an embodiment includes a first level shifter configured to output an intermediate signal wherein a high voltage is a positive supply voltage or a positive voltage by inputting an input signal and a low voltage is a negative supply voltage, to an intermediate signal node and an inverted intermediate signal node and a second level shifter configured to output a low voltage to an output terminal and an inverted output terminal by receiving input of the intermediate signal and altering the low voltage to the negative supply voltage or a negative voltage.

Abstract: Systems, methods and/or devices are used to enable notification of a trigger condition to reduce declared capacity of a storage device. In one aspect, the method includes, at a storage device of a storage system, the storage device including non-volatile memory: (1) detecting a trigger condition for reducing declared capacity of the non-volatile memory of the storage device, and (2) notifying a host to which the storage device is operatively coupled of the trigger condition for reducing declared capacity of the non-volatile memory of the storage device, the trigger condition for enabling performance of an amelioration process to reduce declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices.

Abstract: Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including reducing a range of logical addresses of a logical address space available to a host. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host.

Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

Abstract: Systems, methods and/or devices are used to enable notification of a trigger condition to reduce declared capacity of a storage device in a multi-storage-device storage system. In one aspect, the method includes: (1) obtaining, for each storage device of a plurality of storage devices, one or more metrics of the storage device, the storage device including non-volatile memory, (2) detecting a trigger condition for reducing declared capacity of the non-volatile memory of a respective storage device of the plurality of storage devices, the trigger condition detected in accordance with the one or more metrics of two or more of the storage devices, and (3) notifying a host of the trigger condition for reducing declared capacity of the non-volatile memory of the respective storage device, the trigger condition for enabling performance of an amelioration process to reduce declared capacity of the non-volatile memory of the respective storage device.