Three Devices Per Bit Patents (Class 365/187)
  • Patent number: 10725495
    Abstract: A power gating system includes a logic circuit region including at least one logic gate configured to receive a first gating clock signal. The power gating system also includes a power gating control circuit configured to generate the first gating clock signal which is controlled to start transition after stabilization of an internal power voltage according to a chip select signal, a command/address signal, and an external clock signal.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Seung Hun Lee
  • Patent number: 10706250
    Abstract: A capacitive image sensing device is provided. The capacitive image sensing device includes a first charge amplifier, a second charge amplifier and a differential amplifier. The first charge amplifier is coupled to one of sensing electrodes of a sensor array. The differential amplifier has a first input terminal, a second input terminal and a differential output terminal pair. The first input terminal of the differential amplifier is coupled to the first charge amplifier. The second input terminal of the differential amplifier is coupled to the second charge amplifier.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 7, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventor: Chi-Ting Chen
  • Patent number: 10614875
    Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Glen E. Hush
  • Patent number: 10157669
    Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Adam Johnson
  • Patent number: 10152161
    Abstract: A touch screen controller is for a drive line emitting a periodic signal and capacitively intersecting sense lines. A selection circuit, for each of a number of portions of the periodic signal equal to a number of the sense lines, couples a first subset of the sense lines to a first output path, and couples a second subset of the sense lines to a second output path, the second subset being sense lines not included in the first subset. Processing circuitry, for each portion of the periodic signal, measures a capacitance of the first output path, measures a capacitance of the second output path, and sums the capacitance of the first output path and the capacitance of the second output path. The processing circuitry determines a capacitance between each sense line of the first and second subsets and the drive line as a function of the sums.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: December 11, 2018
    Assignee: STMICROELECTRONICS ASIA PACIFIC PTE LTD
    Inventor: Leonard Dinu
  • Patent number: 9564199
    Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 7, 2017
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 9001564
    Abstract: It is an object to reduce power consumption of a 2Tr1C type semiconductor memory device. The absolute value of the threshold voltage of a reading transistor is made larger than a fluctuation range of a data potential of a bit line (or the fluctuation range of the data potential of the bit line is made smaller than the absolute value of the threshold voltage of the reading transistor), whereby the potential of a source line can be fixed, a fluctuation in a potential of a writing word line can be made smaller, and a potential of a reading word line is fluctuated only at the time of reading. Further, a gate of such a transistor the absolute value of the threshold voltage of which is large is formed using a material having a high work function, such as indium nitride.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 8792284
    Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8780629
    Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuma Furutani, Yoshinori Ieda, Yuto Yakubo, Kiyoshi Kato, Shunpei Yamazaki
  • Patent number: 8773944
    Abstract: An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Chihtung Chen, Inyup Kang, Viraphol Chaiyakul
  • Patent number: 8760955
    Abstract: A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resistivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Li Liao, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Patent number: 8675394
    Abstract: An object is to provide a semiconductor device which can hold stored data even when not powered and which achieves high integration by reduction of the number of wirings. The semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, e.g., an oxide semiconductor material which is a wide bandgap semiconductor. When a semiconductor material which allows a sufficient reduction in the off-state current of a transistor is used, data can be held for a long period. One line serves as the word line for writing and the word line for reading and one line serves as the bit line for writing and the bit line for reading, whereby the number of wirings is reduced. Further, by reducing the number of source lines, the storage capacity per unit area is increased.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: March 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Patent number: 8587982
    Abstract: Embodiments include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 19, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Pill Kim, Hari M. Rao, Xiaochun Zhu, Xia Li, Seung H. Kang
  • Patent number: 8576636
    Abstract: A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: November 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Takanori Matsuzaki, Hiroki Inoue, Shuhei Nagatsuka
  • Patent number: 8411524
    Abstract: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Eric Carman
  • Patent number: 8391059
    Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 5, 2013
    Assignee: IMEC
    Inventors: Zhichao Lu, Nadine Collaert, Marc Aoulaiche, Malgorzata Jurczak
  • Patent number: 8385112
    Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: February 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8374016
    Abstract: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: February 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jeffrey A. Correll
  • Patent number: 8218372
    Abstract: According to one embodiment, a first node is connected to a gate of a second PMOS and a gate of a second NMOS, a second node is connected to a gate of a first PMOS and a gate of a first NMOS, a gate of the first transistor is connected to a first signal line, a source of a first transistor is connected to the first node, and a drain of the first transistor is connected to the second node, a gate of a second transistor is connected to the second node, a source of the second transistor is connected to a third node, and a drain of the second transistor is connected to a second signal line, and a gate of a third transistor is connected to a third signal line, a source of the third transistor is connected to a fourth signal line, and a drain of the third transistor is connected to the third node.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisaburo Takashima
  • Patent number: 8120989
    Abstract: An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: February 21, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Chihtung Chen, Inyup Kang, Viraphol Chaiyakul
  • Patent number: 7972920
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: July 5, 2011
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Electronics Corp.
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Patent number: 7916535
    Abstract: Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by setting a voltage level of a first memory cell to a first voltage level and setting a voltage level of a second memory cell to a second voltage level. In one embodiment, the first voltage level and the second voltage level are of opposite polarity. In one embodiment, to store a data bit having the value “0,” the first memory cell is set to a first voltage level and the second memory cell is set to a second voltage level of opposite polarity to the first voltage level, and to store a data bit having the value “1,” the first memory cell is set to a third voltage level and the second memory cell is set to a fourth voltage level of opposite polarity to the third voltage level.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: March 29, 2011
    Inventor: Esin Terzioglu
  • Patent number: 7876601
    Abstract: The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: January 25, 2011
    Assignee: Altera Corporation
    Inventor: David Lewis
  • Patent number: 7816721
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: October 19, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 7804714
    Abstract: A system and method are disclosed for providing an electrically programmable read only memory (EPROM) in which each memory cell comprises an NMOS select transistor with a thick gate oxide and a PMOS breakdown transistor with a thin gate oxide. The source of the NMOS transistor and the source, drain and N well of the PMOS transistor are connected. The gate of the PMOS transistor is grounded. Under the control of the NMOS transistor, a programming voltage pulse is passed to the N well of the PMOS transistor of a selected memory cell. The magnitude of the voltage is sufficient to break the thin gate oxide of the PMOS transistor without damaging the NMOS transistor. Because the memory state of the memory cell depends on the breakdown status of the PMOS transistor, the data may be retained in the memory cell for an unlimited period of time.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: September 28, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Jiankang Bu, William S. Belcher, David Courtney Parker
  • Patent number: 7675767
    Abstract: A semiconductor memory device is provided with a DRAM array and a control circuit. The DRAM array includes first and second storage areas. The control circuit controls an access to said DRAM array so that data hold characteristics of said first storage area are superior to those of said second storage area.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: March 9, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroyuki Takahashi
  • Patent number: 7602634
    Abstract: Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the chip. Data stored in DRAM cells is provided directly to the pass gates at the full supply voltage to prevent signal degradation. A p-channel transistor eliminates all N-type junctions from the storage node reducing the collection of particles that may cause soft errors.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: October 13, 2009
    Assignee: Altera Corporation
    Inventor: John Turner
  • Patent number: 7532496
    Abstract: A system and method are disclosed for providing an electrically programmable read only memory (EPROM) in which each memory cell comprises an NMOS select transistor and a PMOS program transistor with a thick gate oxide and a PMOS breakdown transistor with a thin gate oxide. The source of the NMOS transistor and the source, drain and N well of the PMOS breakdown transistor are connected. The gate of the PMOS breakdown transistor is connected to the PMOS program transistor. The memory cell is programmed by two voltage pulses that are passed to the N well of the PMOS breakdown transistor. The combined voltage of the two pulses is sufficient to break the thin gate oxide of the PMOS breakdown transistor. Because the memory state of the memory cell depends on the breakdown status of the PMOS breakdown transistor, the data may be retained in the memory cell for an unlimited period of time.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: May 12, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Jiankang Bu
  • Patent number: 7277316
    Abstract: Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the chip. Data stored in DRAM cells is provided directly to the pass gates at the full supply voltage to prevent signal degradation.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: October 2, 2007
    Assignee: Altera Corporation
    Inventor: John Turner
  • Patent number: 7245525
    Abstract: In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: July 17, 2007
    Assignee: T-Ram Semiconductor, Inc.
    Inventors: Zachary K. Lee, Farid Nemati, Scott Robins
  • Patent number: 7239558
    Abstract: A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell and a plurality of cascoded NMOS pass gates. The cell structure reduces total programming time and provides the flexibility of programming the entire cell array simultaneously or one row or sector of the array at a time.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: July 3, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Pavel Poplevine, Annie-Li-Keow Lum, Hengyang Lin, Andrew J. Franklin
  • Patent number: 7236391
    Abstract: A memory device includes a memory cell having a read margin that exceeds the MR ratio of the memory cell's MR element. The memory cell includes a MR element, a reference transistor, and an amplifying transistor. In some embodiments, the MR element can include a magnetic tunneling junction sandwiched between electrode layers. One of the electrode layers can be connected to an input node, which is also connected to the drain or source node of the reference transistor and the gate node of the amplifying transistor. The drain node of the amplifying transistor is connected to a sense amplifier via a conductive program line. The memory cell uses the current through the MR element to control the gate-source voltage of the amplifying transistor, and senses the state of the memory cell based on the voltage drop (or current loss) across the amplifying transistor.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: June 26, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 7221580
    Abstract: A memory cell includes: a charge storage element (e.g., capacitor); a switch constructed and arranged to selectively connect the charge storage element to a first data line, responsive to a first select signal; and a gain element having an input connected to receive a signal from the capacitor and constructed and arranged to selectively provide a corresponding output signal to a second data line, responsive to a second select signal. The switch can be a FET having a drain connected to the first data line, a source connected to the capacitor and a gate connected to the first select signal. The gain element can be a FET having a gate connected to the capacitor, a source connected to the second data line and a drain selectively connected to one of an upper power supply and a lower power supply. The switch can transfer a signal from the first data line onto the capacitor and can transfer a signal from the capacitor onto the first data line when selected by the first select signal.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: May 22, 2007
    Assignee: Analog Devices, Inc.
    Inventor: Robert A. Penchuk
  • Patent number: 7149940
    Abstract: A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. The multilevel memory cells are arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (n?2) number of bits (X1, X2,. . . , Xn). A logical address is converted into a physical address of the physical address space. A judgement is made as to whether a logical address space including the logical address matches the physical address space. When matched, the most significant bit X1 is specified by performing a single comparison operation using a reference value. The specified bit is output from one of the cells corresponding to the physical address. If not matched, the bits (X2, . . . , Xn) are specified by performing multiple comparison operations using different reference values.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: December 12, 2006
    Assignee: Pegre Semicondcutors LLC
    Inventor: Katsuki Hazama
  • Patent number: 7088606
    Abstract: Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the chip. Data stored in DRAM cells is provided directly to the pass gates at the full supply voltage to prevent signal degradation.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: August 8, 2006
    Assignee: Altera Corporation
    Inventor: John Turner
  • Patent number: 7027326
    Abstract: A memory cell comprises: (1) a write switch, the first terminal of the write switch coupled to an at least one bitline, the control terminal of the write switch coupled to the first control line; (2) a two terminal semiconductor, the first terminal of the two terminal semiconductor device coupled to the second terminal of the write switch, and the second terminal of the two terminal semiconductor device coupled to an at least one second control line, wherein the two terminal semiconductor device has a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and has a lower capacitance when the voltage on the first terminal relative to the second terminal is less than the threshold voltage; (3) a read select switch, the control terminal of the read select switch coupled to an at least one second control line, the first terminal of the read select switch coupled to the at least one bitline; and (4) a read switch, the control terminal of the read switch couple
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: April 11, 2006
    Assignee: International Business Machines Corporation
    Inventors: Wing K. Luk, Robert H. Dennard
  • Patent number: 7016246
    Abstract: A memory includes first circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bus coupling first circuit to second and third circuits. The second circuit outputs in response to second clock signal, first address signal to first circuit. The third circuit outputs in response to third clock signal, second address signal to first circuit. The first circuit includes refresh control circuit executing refresh operation for memory cells in response to fourth clock signal and address latch for storing first or second address signal in response to first clock signal. The first clock signal has frequency equal to or more than sum of frequencies respectively of second, third, and fourth clock signals.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: March 21, 2006
    Assignee: Hitachi Ltd.
    Inventors: Takao Watanabe, Hiroyuki Mizuno, Satoru Akiyama
  • Patent number: 7002874
    Abstract: An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: February 21, 2006
    Assignees: United Memories, Inc., Sony Corporation
    Inventors: Michael C. Parris, Douglas Blaine Butler, Oscar Frederick Jones, Jr.
  • Patent number: 6982897
    Abstract: A random access memory (RAM) circuit is coupled to a write control line, a read control line, and one or more bitlines, and includes a write switch having a control terminal and first and second terminals. The first terminal of the write switch is coupled to the one or more bitlines, and the control terminal of the write switch is coupled to the write control line. The circuit includes a charge-storage device having first and second terminals, wherein a first terminal of the charge-storage device is coupled to the second terminal of the write switch and a second terminal of the charge-storage device is coupled to the read control line. The circuit includes a read switch having a control terminal and first and second terminals. The control terminal of the read switch is coupled to the first terminal of the charge-storage device and is coupled to the second terminal of the write switch.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: January 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Wing K. Luk, Robert H. Dennard
  • Patent number: 6944051
    Abstract: In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: September 13, 2005
    Assignee: T-Ram, Inc.
    Inventors: Zachary K. Lee, Farid Nemati, Scott Robins
  • Patent number: 6912151
    Abstract: A memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs. Various embodiments using common or separate wells for such elements are illustrated to achieve superior body effect performance results, including a silicon-on-insulator (SOI) implementation.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 28, 2005
    Assignee: Synopsys, Inc.
    Inventor: Tsu-Jae King
  • Patent number: 6862205
    Abstract: The semiconductor memory device includes: a memory cell including a capacitor having a charge storage node and a first MIS transistor and a second MIS transistor each having a source connected to the charge storage node; a first word line and a first bit line respectively connected to the gate and the drain of the first MIS transistor; a second word line and a second bit line respectively connected to the gate and the drain of the second MIS transistor; and a timer circuit for generating a periodic signal having a predetermined period. The first word line or the second word line is activated in response to the periodic signal.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: March 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masashi Agata, Kazunari Takahashi
  • Patent number: 6847548
    Abstract: A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: January 25, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Craig T. Swift, Michael A. Sadd
  • Patent number: 6788565
    Abstract: A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: September 7, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masashi Agata, Kazunari Takahashi, Masanori Shirahama, Naoki Kuroda, Hiroyuki Sadakata, Ryuji Nishihara
  • Patent number: 6707697
    Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: March 16, 2004
    Assignee: STMicroelectronics SA
    Inventors: Cyrille Dray, Richard Fournel
  • Patent number: 6683813
    Abstract: There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is comprised of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integration and a lower electrical power as compared with those of the prior art device can be realized.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: January 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Hanzawa, Takeshi Sakata
  • Patent number: 6680864
    Abstract: A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body portion of the p-channel transistor is coupled to a second source/drain region of the MOSFET which serves as the gate for the JFET. The second source/drain region of the MOSFET is additionally coupled to a charge storage node. Together the second source/drain region and charge storage node provide a bias to the body of the JFET that varies as a function of the data stored by the memory cell. A non destructive read operation is achieved. The stored charge is sensed indirectly in that the stored charge modulates the conductivity of the JFET so that the JFET has a first turn-on threshold for a stored logic “1” condition and a second turn-on threshold for a stored logic “0” condition.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: January 20, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Wendell P. Noble
  • Patent number: 6678198
    Abstract: Present invention describes an efficient implementation of differential sensing in single ended DRAM arrays. According to one embodiment of the present invention, a respective local sense amplifier compares the accessed memory cell data with a dummy cell data in the opposite or adjacent block of the accessed block that is connected to a respective local bit line in the opposite block, amplifies the result of the comparison and puts the data on a global bit line. In one embodiment, the invention is process and temperature invariant using reference method and means for canceling cross coupling between read lines and write lines.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: January 13, 2004
    Assignee: Broadcom Corporation
    Inventors: Sami Issa, Morteza Cyrus Afghahi
  • Patent number: 6671210
    Abstract: A semiconductor device includes a plurality of DRAM memory cells each having first, second, and third MOS transistors; a plurality of first word lines coupled to the gates of the first MOS transistors; a plurality of second word lines coupled to the gates of the second MOS transistors; a plurality of first bit lines coupled to the source/drain paths of the first MOS transistors; and a plurality of second bit lines coupled to the source/drain paths of the second MOS transistors. The plurality of DRAM memory cells includes a series of such memory cells defining a plurality of groups of k memory cells, and the plurality of first word lines includes a group of k first word lines, each of which is coupled to a gate of a first MOS transistor only in every kth DRAM memory cell of the series, wherein k is greater than one.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: December 30, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takao Watanabe, Hiroyuki Mizuno, Satoru Akiyama