Including Signal Comparison Patents (Class 365/189.07)
  • Patent number: 9960759
    Abstract: Disclosed systems and methods relate to comparison of a first number and a second number. A comparator receives first and second single-ended inputs (i.e., not represented in differential format), which may be n-bits wide, wherein the first input is an inverted version of the first number and the second input is a true version of the second number. A partial match circuit is implemented to generate a partial match output based only on the first single-ended input and the second single-ended input. A partial mismatch circuit is implemented to generate a partial mismatch output based only on the first single-ended input and the second single-ended input. A comparison output circuit is implemented to generate a comparison output of the first and second numbers based on the partial match output and the partial mismatch output.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: May 1, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Manish Garg, Ramasamy Adaikkalavan
  • Patent number: 9947378
    Abstract: A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ).
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Ki Won Lee, Seung Jun Bae, Joon Young Park, Yong Cheol Bae
  • Patent number: 9940097
    Abstract: A registered synchronous FIFO has a tail register, internal registers, and a head register. The FIFO cannot be pushed if it is full and cannot be popped if it is empty, but otherwise can be pushed and/or popped. Within the FIFO, the internal signal fanout of incoming data circuitry and push control circuitry and is minimized and remains essentially constant regardless of the number of registers of the FIFO. The output delay of the output data also is essentially constant regardless of the number of registers of the FIFO. An incoming data value can only be written into the head or tail. If a data value is in the tail and one of the internal registers is empty, and if no push or pop is to be performed in a clock cycle, then nevertheless the data value in the tail is moved into the empty internal register in the cycle.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 10, 2018
    Assignee: Netronome Systems, Inc.
    Inventors: Ronald N. Fortino, Gavin J. Stark, Steven W. Zagorianakos
  • Patent number: 9922152
    Abstract: A computer-implemented system and method is provided for reducing failure-in-time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each sequential device of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 20, 2018
    Assignee: ARM Limited
    Inventors: Liangzhen Lai, Vikas Chandra
  • Patent number: 9922729
    Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: March 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Alan J. Wilson, Jeffrey Wright
  • Patent number: 9917573
    Abstract: To provide a voltage detection circuit which avoids unintentional on/off-control of an output transistor immediately after starting a power supply. A voltage detection circuit is configured to be equipped with a comparator which compares a detected voltage and a reference voltage, and an inverter which drives an output transistor, based on an output of the comparator and to supply the operating current of the inverter by a current source.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: March 13, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Masakazu Sugiura
  • Patent number: 9911492
    Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack R. Morrish
  • Patent number: 9899098
    Abstract: A semiconductor memory device includes a first word line and a second word line that are adjacent to each other, a first voltage boosting circuit configured to generate a first voltage based on a clock signal, a second voltage boosting circuit configured to generate a second voltage lower than the first voltage based on the clock signal, a counter, and a determination circuit. The counter counts a first number of clock cycles of the clock signal during a first period in which the first voltage boosting circuit generates the first voltage and applies the first voltage to the first word line while the second voltage boosting circuit generates the second voltage and applies the second voltage to the second word line, and a second number of clock cycles of the clock signal during a second period in which the first voltage boosting circuit generates the first voltage while the first word line is electrically disconnected from the first voltage boosting circuit.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 20, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Mizuki Kaneko, Junji Musha
  • Patent number: 9891842
    Abstract: A method includes comparing, in parallel, a data pattern with data stored into a plurality of columns of memory cells, and in response to detecting the data pattern in the data stored into a particular column of memory cells of the plurality of columns of memory cells, storing in a memory cell of the particular column a value indicative of at least one of an occurrence of the data pattern or a position of the data pattern in the data stored into the particular column.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 13, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Isom Lawrence Crawford, Jr.
  • Patent number: 9870235
    Abstract: Described embodiments provide for a method of recording events generated for performing a task through user equipment. In the method, an activation input may be received for activating an event recording mode. Upon the activation of the event recording mode, events generated in the user equipment may be recorded. Upon the receipt of an inactivation input for inactivating the event recording mode, an identification code may be assigned to a set of the recorded events. The set of the generated events may be stored with the assigned identification code.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: January 16, 2018
    Assignee: KT CORPORATION
    Inventors: Sung-Ho Byun, Jae-Won Byun
  • Patent number: 9859005
    Abstract: Disclosed is a method of selecting a data candidate having a maximum value from a plurality of data candidates stored in columns in a memory array. The method includes computing marker bit values for each row of data in the memory array, and performing a Boolean OR operation on the marker bit values to generate a responder signal value. Also disclosed is a memory device including a memory array of memory cells arranged in rows and columns, and responder signal circuitry to generate a responder signal responsive to positive identification of a data candidate in the memory array.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: January 2, 2018
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Eli Ehrman
  • Patent number: 9859006
    Abstract: The present disclosure relates to a content addressable memory (CAM), and more particularly, to an algorithmic ternary content addressable memory (TCAM) that instantiates multiple copies of X-Y TCAMs. The structure includes a content addressable memory (CAM) and an array which instantiates multiple replicated copies of the CAM in a row direction and a column direction of the array.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Michael T. Fragano, Robert Houle
  • Patent number: 9830975
    Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: November 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kiyotada Funane, Ken Shibata, Yasuhisa Shimazaki
  • Patent number: 9799392
    Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: October 24, 2017
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Neal Berger, Yuniarto Widjaja
  • Patent number: 9793008
    Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 17, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Alan J. Wilson, Jeffrey Wright
  • Patent number: 9792988
    Abstract: A parallel turbine ternary content addressable memory includes one or more atoms in each of one or more rows, wherein each of the one or more atoms includes a memory with N addresses and a width of M logical lookup entries, wherein N and M are integers, one or more result registers, each with a width of M, wherein a number of the one or more result registers equals a number of one or more keys each with a length of N, and a read pointer configured to cycle through a row of the N addresses per clock cycle for comparison between the M logical entries and the one or more keys with a result of the comparison stored in an associated result register for each of the one or more keys.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: October 17, 2017
    Assignee: Ciena Corporation
    Inventor: Richard Donald Maes, II
  • Patent number: 9778976
    Abstract: An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 3, 2017
    Assignee: Semiconducgtor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9779788
    Abstract: A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more circuits adapted to operate at sub- or near-threshold voltage levels. These low-power circuits are selectively activated or de-activated to balance power dissipation with the response time of the memory system required in particular applications.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 3, 2017
    Assignee: Ambiq Micro, Inc.
    Inventors: Christophe J. Chevallier, Daniel M. Cermak, Scott Hanson
  • Patent number: 9772366
    Abstract: A method of testing a device under test (DUT) connected between first and second DUT nodes includes generating a set of control signals, and in response to the set of control signals, disconnecting a first voltage node from a first DUT node, connecting a second voltage node to the first DUT node, periodically connecting and disconnecting a third voltage node to and from the second DUT node at a predetermined frequency, disconnecting a fourth voltage node from the second DUT node when the third voltage node is connected to the second DUT node, and connecting the fourth voltage node to the second DUT node when the third voltage node is disconnected from the second DUT node. A circuit that performs the method is also disclosed.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shuo-Chun Chou, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang
  • Patent number: 9772676
    Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: September 26, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen Kosonocky, Samuel Naffziger
  • Patent number: 9768179
    Abstract: An electronic circuit includes a Ternary Content-Addressable Memory (TCAM) array. The TCAM array includes a plurality of TCAM cells that include a first signal line. The first signal line is located in a first metal layer. The TCAM array includes a connection structure that includes a first metal landing pad. The first metal landing pad is located in a second metal layer different from the first metal layer. The electronic circuit includes a periphery circuit located near the TCAM array. The periphery circuit includes a first metal line located in the first metal layer. The first metal line extends in a direction parallel to the first signal line but is misaligned with the first signal line in a planar view. The first metal landing pad is electrically coupled to both the first signal line and the first metal line.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9767905
    Abstract: A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a pass value. When enabled by its token signal, the first scan block in a group is reset by a first clock signal. A second scan block in the group is enabled for reset after the first scan block indicates the pass value. The second scan block in the group is reset by a second clock signal having pulses that precede corresponding pulses from the first clock signal.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: September 19, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Kesheng Wang
  • Patent number: 9768111
    Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, an integrated circuit includes a series of layers. The series of layers include a plurality of pillar metals in each of the series of layers. Pillars within each of the series of layers are oriented to be parallel. Pillars in adjacent layers are aligned to be perpendicular. Each of the plurality of pillar metals is a rectangular segment of metal. The plurality of pillar metals form a reconvergent mesh grid. The series of layers includes a plurality of vias connecting the plurality of parallel pillar metals between the series of layers. Vias of the plurality of vias are located at intersections in the reconvergent mesh grid.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: September 19, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mark O'Brien, James G. Ballard, Kiran Vedantam, Mini Nanua, Salvatore Caruso
  • Patent number: 9755617
    Abstract: Methods and apparatuses are disclosed for driving a node to one or more elevated voltages. One example apparatus includes a first driver circuit configured to drive a node to a first voltage, and a second driver circuit configured to drive the node to a pumped voltage after the node reaches a voltage threshold. The apparatus also includes a controller circuit configured to disable the first driver circuit and enable the second driver circuit responsive to the node reaching the voltage threshold.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Marco Sforzin
  • Patent number: 9747981
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: August 29, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jeremy Hirst, Hernan Castro, Stephen Tang
  • Patent number: 9741434
    Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: August 22, 2017
    Assignees: SK HYNIX INC., KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Katayama, Masahiro Takahashi, Tsuneo Inaba, Hyuck Sang Yim, Dong Keun Kim, Byoung Chan Oh, Ji Wang Lee
  • Patent number: 9733939
    Abstract: A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Vijaykumar Balaram Kadgi, James D. Hadley, Avinash Sodani, Matthew C. Merten, Morris Marden, Joseph A. McMahon, Grace C. Lee, Laura A. Knauth, Robert S. Chappell, Fariborz Tabesh
  • Patent number: 9727415
    Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: August 8, 2017
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Jia Geng, Yuanpeng Wang, Ping Fan
  • Patent number: 9720491
    Abstract: Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Dean Mulla, Daniel G. Borkowski, Krishnakanth V. Sistla, Victor Wu, Manev Luthra
  • Patent number: 9710415
    Abstract: An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: July 18, 2017
    Assignee: NXP USA, INC.
    Inventors: Chanpreet Singh, Kshitij Bajaj, Abhineet Kumar Bhojak, Anisha Ladsaria, Tejbal Prasad
  • Patent number: 9712854
    Abstract: A capability is provided for determining a fraction of content item versions to cache for use in responding to requests for content items. The fraction of content item versions to cache is determined based on a popularity distribution of the content item versions and cost model information associated with the content item versions. The cost model information may include information indicative of a cost of storing one of the content item versions and at least one of a cost of transcoding one of the content item versions or a cost of transferring one of the content item versions. The fraction of content item versions to cache may be determined based a skewness factor of the popularity distribution of the content item versions.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: July 18, 2017
    Assignee: Alcatel Lucent
    Inventors: Moritz M. Steiner, Yao Liu
  • Patent number: 9704574
    Abstract: Aspects of the disclosure provide an apparatus that includes a key generator, a first memory, a second memory, and a controller. The key generator is configured to generate a first search key, and one or more second search keys in response to a pattern. The first memory is configured to compare the first search key to a plurality of entries populated in the first memory, and determine an index of a matching entry to the first search key. The second memory is configured to respectively retrieve one or more exact match indexes of the one or more second search keys from one or more exact match pattern groups populated in the second memory. The controller is configured to select a search result for the pattern from among the index output from the first memory and the one or more exact match indexes output from the second memory.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: July 11, 2017
    Assignee: Marvell International Ltd.
    Inventor: Michael Shamis
  • Patent number: 9704542
    Abstract: The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. The leakage measurement circuit may be operable to generate a reference current and to determine whether a leakage current on one of the plurality of word lines is acceptable relative to the reference current. In another embodiment, a method may include determining whether leakage on one of a plurality of word lines of a memory device is allowable using a circuit in the memory device.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: July 11, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 9697148
    Abstract: An apparatus for managing a memory having a plurality of command/address pins is provided. The apparatus includes a command generating module and a control module. The command generating module generates a set of target commands. The set of target commands include a plurality of command groups. Each of the command groups corresponds to at least one command/address pin of the plurality of command/address pins. It is known that the memory accesses the set of target commands from the plurality of command/address pins at a target time point. The control module controls the command groups to have different transition times prior to the target time points when the command groups are transmitted on the plurality of command/address pins.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: July 4, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yung Chang, Chen-Nan Lin, Chung-Ching Chen
  • Patent number: 9698832
    Abstract: Apparatus and methods for negative voltage generation with reduced clock feed-through are provided. In certain configurations, a method of negative voltage generation in a wireless device is provided. The method includes generating a regulated voltage from a battery voltage using a voltage regulator, powering a first charge pump and a second charge pump using the regulated voltage, generating a first negative voltage based on timing of a first clock phase using the first charge pump, generating a second negative voltage based on the first negative voltage and on timing of a second clock phase using the second charge pump, and generating the first clock phase and the second clock phase with different phases using a poly-phase oscillator such that the first charge pump and the second charge pump draw from the regulated voltage at different points in time.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 4, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Peter Harris Robert Popplewell, Jakub F. Pingot, Florinel G. Balteanu
  • Patent number: 9697141
    Abstract: A host access instruction is received from one of a plurality of channels which are served in parallel. The host access instruction includes an address range of one or more addresses and a type of access. The address range and type of access are compared against a table of stored address ranges and stored types of access associated with any pending host access instructions. It is determined whether to execute the host access instruction based at least in part on the comparison. If it is decided to execute the host access instruction, the host access instruction is forwarded for execution and the address range and the type of access from the host access instruction are stored in the table.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 4, 2017
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Shengkun Bao, Kevin Landin, Ananthanarayanan Nagarajan, Kin Ming Chan
  • Patent number: 9691491
    Abstract: An example method to track bit cell current in a memory architecture. An example method disclosed herein includes generating a first reference current dependent on bit cell temperature. The example method includes generating a second reference current dependent on bit cell voltage and supplying a third reference current of constant magnitude. In examples disclosed herein, the example method involves summing the first reference current, the second reference current, and the third reference current. The example method includes determining, with a sense amplifier, a bit cell logic state based on the first reference current, the second reference current, and the third reference current.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: June 27, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kurt Stephen Schwartz, Patrick Robert Smith
  • Patent number: 9690652
    Abstract: According to one embodiment, a search device includes a first comparison module, a determination module, a correction module, a second comparison module, and a search module. The first comparison module compares a received first key with a second key read from a nonvolatile memory. The determination module determines whether error correction is possible based on a first comparison result obtained by the first comparison module. The correction module generates a third key by applying an error correction process to the second key if the determination module determines that error correction is possible. The second comparison module compares the first key with the third key. The search module reads data associated with the second key in the nonvolatile memory if a second comparison result obtained by the second comparison module shows a match.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: June 27, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinichi Kanno
  • Patent number: 9679649
    Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: June 13, 2017
    Assignee: Commissariat √† l'√Čnergie Atomique et aux √Čnergies Alternatives
    Inventors: Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara, Olivier Thomas
  • Patent number: 9679642
    Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Zengtao T. Liu, Kirk D. Prall
  • Patent number: 9666265
    Abstract: A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 30, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takeshi Oshita, Takanori Hirota, Masato Suzuki
  • Patent number: 9659648
    Abstract: A semiconductor memory device includes a plurality of first memory cells included in a first memory cell group and coupled to a plurality of first bit lines, respectively, a plurality of first switches coupled to the first bit lines, respectively, and coupled to a voltage node, a driver configured to supply a constant voltage to the voltage node for a write operation, and a switch control unit configured to selectively turn on one or more of the first switches when the write operation is performed.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: May 23, 2017
    Assignee: SK hynix Inc.
    Inventors: In Soo Lee, Jung Hyuk Yoon
  • Patent number: 9652836
    Abstract: Provided are a method of clustering defects generated in bad samples shown on a defect map of bad samples including bad products, and an apparatus thereof. The defect cell clustering method includes generating a sample defect map showing a defect cell distribution by cell positions of bad samples comprised of products each including one or more defect cells among products each partitioned into a plurality of cells, selecting at least some cell positions having one or more defect cells as clustering targets from the sample defect map, selecting one or more suspected bad equipments for each of cell positions included in the clustering targets using pass equipment information for the product, and grouping the clustering targets into one or more clusters according to position coherence between a first cell position and a second cell position included in one cluster, the cell position and the second cell position each having at least one suspected bad equipment.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Kae Young Shin, Dae Jung Ahn, Ji Young Park, Ji Min Kang
  • Patent number: 9647838
    Abstract: This invention requires a slight modification to the Microprocessor with the addition of comparators and a latch, and the addition of a multidimensional array for what is in RAM. The Storage Device also has the addition of comparators and a multidimensional array for what has been passed to the Microprocessor and includes a pointer to the area of the Storage Device. There is an addition of an IEP card for handling Internet activity. The IEP card can help control advertising and serving WEB pages.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 9, 2017
    Inventor: Ralph John Hilla
  • Patent number: 9639501
    Abstract: Systems and techniques relating to processing of network communications include, according to an aspect, a network device that includes circuitry configured to receive value bits selected from a group consisting of a zero bit, a one bit, and a don't care bit; and circuitry configured to store encoded representations of the value bits for use in network packet routing, wherein the encoded representations are position bits selected from a group consisting of a zero bit and a one bit; wherein the circuitry configured to store includes a first memory location and a second memory location that each eliminate a different combination of the value bits from being available for storage respectively in the first memory location and the second memory location.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: May 2, 2017
    Assignee: FIRQUEST LLC
    Inventors: Hillel Gazit, Sohail Syed, Gevorg Torjyan
  • Patent number: 9639493
    Abstract: Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include or be coupled to a results buffer, which may have a plurality of records, a write-control module configured to write data relevant to search results in the plurality of records, and a read control module configured to read data from the plurality of records.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: May 2, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Patent number: 9627064
    Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: April 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Keith Alan Bowman, Francois Ibrahim Atallah, David Joseph Winston Hansquine, Jihoon Jeong, Hoan Huu Nguyen
  • Patent number: 9627899
    Abstract: A mobile terminal and an interface method thereof for connecting external devices, such as an adapter, a Universal Serial Bus (USB) cable, a docking station, an accessory, and the like, to the mobile terminal are provided. The mobile terminal includes a battery, a connector including a pin for data communication and first and second power pins for charging the battery, a memory for storing a reference voltage indicating a dedicated adapter of the battery, and a controller for receiving a voltage input from the first and second power pins, for recognizing an external device connected with the connector as the dedicated adapter when a voltage input from the pin for data communication is the reference voltage, and for charging the battery with power input to the first and second power pins.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Hyun Lee
  • Patent number: 9613720
    Abstract: A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kouichirou Yamaguchi, Makoto Miakashi, Hitoshi Shiga, Noboru Shibata
  • Patent number: 9608890
    Abstract: Notifications of events that take place within a virtual space and/or information related the notifications may be transmitted from a server which hosts an instance of the virtual space to the user device via which users may interact with the virtual space. Based on the received notifications and/or the information related to those notifications, the user device may transmit external notifications to one or more presentation control devices that are within the vicinity of the user device. Determining a particular presentation control device to which the user device should transmit the event notification may depend on whether the presentation control device is located within the vicinity of the user device, a predefined association between a user and the presentation control device, and/or whether the user is present at the presentation control device. The presentation control device may concurrently display notifications that belong to different users.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 28, 2017
    Assignee: Kabam, Inc.
    Inventors: Kent Wakeford, Clifford J. Harrington