Abstract: A sense amplifier, a nonvolatile memory device including the sense amplifier and a sensing method of the sense amplifier are provided. The sense amplifier includes a first comparator that generates a first comparison signal by comparing a first reference signal received from a first reference cell with a sensing target signal received from the selected memory cell, and generates a second comparison signal by comparing the sensing target signal with a second reference signal received from a second reference cell written in different state from the first reference cell, and a second comparator that senses data stored in the selected memory cell by comparing the first comparison signal and the second comparison signal.

Abstract: A memory includes a plurality of word lines, a measurement block suitable for measuring an active duration of an activated word line among the multiple word lines, and a refresh circuit suitable for controlling a refresh operation to refresh one or more of the multiple word lines adjacent to the activated word line when the active duration exceeds a predetermined threshold.

Abstract: A first first-in first-out (FIFO) circuit includes a storage circuit, a second first-in first-out (FIFO) circuit, and a third first-in first-out (FIFO) circuit. The storage circuit stores write data at a write address in response to a write clock signal. The storage circuit outputs read data from a read address in response to a read clock signal. A write pointer indicating the write address is synchronized with the write clock signal. A read pointer indicating the read address is synchronized with the read clock signal. The second first-in first-out (FIFO) circuit synchronizes the write pointer with the read clock signal. The third first-in first-out (FIFO) circuit synchronizes the read pointer with the write clock signal.

Abstract: A method, non-transitory computer readable medium and circuit for gating a strobe (DQS) signal are disclosed. The method sends a read command to a memory, sends a strobe clock signal after the read command is sent and before the DQS signal is received from the memory, wherein the strobe clock signal comprises a duration equal to a duration of the DQS signal, gates the DQS signal based on the strobe clock signal to generate a positively gated strobe signal for indicating a rising edge of the DQS signal, wherein the gating is performed during a pre-amble of the DQS signal and generates a negatively gated strobe signal based on the positively gated strobe signal for indicating a falling edge of the DQS signal.

Abstract: A method and apparatus for controlling the operation of flash memory are provided. The apparatus for controlling the operation of flash memory includes a control unit and a voltage adjustment unit. The control unit outputs a control signal adapted to change one or more of the program, erase and read voltage conditions for the flash memory to the voltage adjustment unit in response to the input of a PUF mode selection signal. The voltage adjustment unit changes the one or more of the program, erase and read voltage conditions for the flash memory in response to the input of the control signal.

Abstract: A DRAM wordline voltage control circuit includes a sensing module, an oscillator and a charging pump. The sensing module is configured to receive a first control signal and a feedback signal corresponding to a wordline voltage signal, and generate a second control signal according to the first control signal and the feedback signal corresponding to the wordline voltage signal. The oscillator is electrically connected with the sensing module. The oscillator is configured to receive the second control signal and output an oscillating signal when the second control signal is enabled. The charging pump is electrically connected with the oscillator. The charging pump is configured to increase a voltage value of the wordline voltage signal when the oscillator outputs the oscillating signal.

Abstract: A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.

Abstract: A circuit device includes an amplifier circuit to which a signal from a sensor is input and a control circuit which controls the sensor and the amplifier circuit. An intermittent operation of the sensor and an intermittent operation of the amplifier circuit are controlled by an intermittent operation control signal output from the control circuit.

Abstract: A repair system for a semiconductor apparatus includes a tester configured to generate memory repair data including a die identification information and repair addresses, and a command to perform a repair process; and a semiconductor apparatus including a plurality of dies configured to receive the memory repair data, wherein one of the dies corresponding to the die identification information performs a repair operation according to the repair addresses and the command.

Abstract: A memory device includes latching circuitry for receiving a latching value and for providing said latching value as an output. A path receives said latching value and passes said latching value to said latching circuitry. First storage circuitry provides a first stored value when said memory device is in a read mode of operation. A bit line is connected to said first storage circuitry. First control circuitry selectively connects said bit line to said path. Sensing circuitry, when an enable signal is active, detects a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and outputs a latching value, dependent on said voltage change, on said path. Second storage circuitry provides a second stored value in a test mode of operation and second control circuitry receives said second stored value and selectively outputs said second stored value as said latching value on said path.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Abstract: Disclosed is a method of preparing fluorescent nanoparticles of ZnSexS1?x(0<x<1) comprising: mixing selenium powders, and sulfur powders with octadecylene, heating and stirring the mixture to dissolve the selenium powders, and the sulfur powders, and then cooling the mixture to give a first precursor solution comprising selenium and sulfur elements; mixing zinc oxide, oleic acid or lauric acid, octadecylene, and benzophenone, heating and stirring the mixture to dissolve the zinc oxide to give a second precursor solution comprising zinc element; adding the first precursor solution into the second precursor solution to undergo a reaction at a temperature of from 270° C. to 290° C. for a time of from 5 min to 10 min; pouring the reaction solution into a polar organic solvent to precipitate a raw product; washing and isolating the precipitate by centrifugation, and then dissolving the isolated materials with a non-polar organic solvent to give nanoparticles of ZnSexS1?x (0<x<1).

Abstract: Disclosed is an organic light emitting display device including: plurality of data lines; a charging line formed in a direction crossing the plurality of data lines; and charging switches connected between the charging line and the data lines. The charging line inputs a charging voltage and the charging switches are individually controlled in data line.

Abstract: A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2n distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of the each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.

Abstract: DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane.

Abstract: Provided are a single-card multi-mode multi-operator authentication method and device. An MAML in an AP receives an authentication request from a user, and authenticates hybrid networks found by a UE. Under the condition of determining that the authentication on each network in the hybrid networks is passed, the MAML receives terminal position information sent by the UE, and determines whether the terminal position information is the same as operator area information registered by the UE in advance, if so, the MAML acquires signal strength of each network and determines whether the signal strength of each network falls within a signal strength range covered by a base station under the network, if so, determines that all the networks in the hybrid networks are authenticated successfully, otherwise, determines that the authentication fails. The security in using an SIM card by a valid user and secure network service are ensured.

Abstract: A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source line provided on a first end side; a plurality of bit line switches provided between the plurality of bit lines and the global bit line; a plurality of source line switches provided between the plurality of source lines and the global source line; a column decoder; a row decoder; a plurality of bit line ground switches provided between the plurality of bit lines and a ground line on a second end side; and a plurality of source line ground switches provided between the plurality of source lines and a ground line on the second end side.

Abstract: A display device is provided including a display unit including a plurality of color pixels; a scan driver that sequentially applies a gate-on voltage scan signal to a plurality of scan lines that are connected to the color pixels; a demux unit that is connected to a plurality of color data lines that are connected to the color pixels, and that sequentially selects the plurality color data lines at a predetermined time interval; and a data driver that applies a data signal to each of the plurality of color data lines that are sequentially selected in the demux unit, and that applies a previous data signal to at least one of the plurality of color data lines during the predetermined time interval, wherein the previous data signal has a same voltage as a voltage applied to one of the plurality of color data lines before the predetermined time interval.

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

Abstract: An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.

Abstract: A semiconductor memory apparatus includes a command processing block configured to generate a voltage generation start signal, a first write control signal, a second write control signal, a read signal, and an operation signal in response to a first control signal and a second control signal in a write operation, and a memory control block configured to electrically couple a memory block, which stores data, to a sense amplifier or apply a predetermined voltage to the memory block in response to the voltage generation start signal, the first write control signal, the second write control signal, the read signal, and the operation signal.

Abstract: A method of programming data in a nonvolatile memory device comprises receiving program data to be programmed in selected memory cells of the nonvolatile memory device, reading data from the selected memory cells, encoding the program data using at least one encoding scheme selected from among multiple encoding schemes according to a comparison of the program data and the read data, generating flag data including encoding information, and programming the encoded program data and the flag data in the selected memory cells.

Abstract: In one aspect, a method includes synchronizing a second storage volume to a first storage volume by synchronizing extents according to priority based on extent activity. In another aspect, an apparatus includes electronic hardware circuitry configured to synchronize a second storage volume to a first storage volume by synchronizing extents according to priority based on extent activity. In a further aspect, an article includes a non-transitory computer-readable medium that stores computer-executable instructions. The instructions cause a machine to synchronize a second storage volume to a first storage volume by synchronizing extents according to priority based on extent activity.

Abstract: A circuit includes a first line, a second line, a first sub-circuit, and a second sub-circuit. The first line has a first signal. The second line has a second signal. The first sub-circuit is configured to generate a first output signal. The second sub-circuit is configured to generate a second output signal. The first output signal and the second output signal have coupling effects if the first signal and the second signal have coupling effects based on the first line and the second line. The first output signal and the second output signal do not have coupling effects if the first signal and the second signal do not have coupling effects.

Abstract: An apparatus (10) and a method (200) for the manufacture of nanoparticles. The apparatus and the method allows for the nucleation and growth of nanoparticles at independent temperatures. The independent temperatures allow for the growth of nanoparticles in a controlled environment avoiding spontaneous nucleation and allowing particle sizes to be controlled and facilitating the manufacture of particles of a substantially uniform size. Furthermore the apparatus (10) allows for the manufacture of core-shell nanoparticles and core-shell-shell nanoparticles.

Abstract: A memory system is provided including a host configured to generate data bit inversion (DBI) information of data according to a major bit of the data, and a nonvolatile memory device configured to invert one or more bits of the data according to the DBI information, and to program the DBI information and the data. A control method of a memory system comprises generating DBI information according to the number of “1” bits of data relative to the number of “0” bits of the data, transferring the data and the DBI information, and inverting bits of the data according to the DBI information, the inverted bits of the data being programmed at the nonvolatile memory device.

Abstract: A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.

Abstract: A liquid crystal display and a method for driving the same, which improve image quality by increasing data line charge speed, are provided. In the display, a preparatory charging controller receives current image data to be provided to m current pixels of an nth horizontal line and a current vertical polarity-reversal control signal for vertically controlling polarities of the current image data, compares current image data with previous data provided to m corresponding previous pixels of an n?1th horizontal line, compares the current control signal with a previous one, and determines a logic value of a preparatory charging control signal based on the comparison. A data driver performs either a first operation for connecting and separating m data lines connected respectively to m current pixels, or a second operation for maintaining the m data lines separated, according to the logic value and provides the current data to the m pixels.

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A method for programmed-state detection in memristor stacks includes applying a first secondary switching voltage across a memristor stack to produce a first programmed-state-dependent secondary switching response in a memristor in the memristor stack. The programmed-state-dependent secondary switching response results in a detectable change in the electrical resistance of the memristor stack. The method also includes measuring a first electrical resistance of the memristor stack and inferring the programmed state of the memristor stack from the measured electrical resistance.

Abstract: A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain a maximum width between two cross points of the left edge and the right edge. A central reference voltage of a data signal outputted by the memory is obtained, and a data width between two cross points of the central reference voltage and a left edge and a right edge of a second waveform of the data signal is obtained. Whether a difference between the data width and the maximum width is greater than a threshold is determined; if the difference is greater than the threshold, the memory is determined to be damaged.

Abstract: An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.

Abstract: A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Abstract: An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to an input address of the first addresses, in a reset operation; and a cell array suitable for replacing one or more normal cells with one or more redundancy cells based on the second addresses in an access operation.

Abstract: In various embodiments, a circuit arrangement may be provided including a data cell. The circuit arrangement may further include a first transistor and a second transistor. The first controlled electrode of the first transistor and the first controlled electrode of the second transistor may be coupled to the first electrode of the data cell. The second controlled electrode of the first transistor may be configured to electrically connect to a first reference voltage such that the first electrode of the data cell is electrically connected to the first reference voltage when the first transistor is activated. The second controlled electrode of the second transistor may be configured to electrically connect to a second reference voltage, such that the first electrode of the data cell is electrically connected to the second reference voltage when the second transistor is activated.

Abstract: The semiconductor device includes a comparator and a data output unit. The comparator compares a phase of a first pulse signal generated in a first memory region with a phase of a second pulse signal generated in a second memory region and responsively generates a detection signal. The data output unit outputs first data received from the first memory region as output data in synchronization with a first output strobe signal generated by defining a pulse width of a first strobe signal in response to the detection signal and outputs second data received from the second memory region as the output data in synchronization with a second output strobe signal generated by defining a pulse width of a second strobe signal in response to the detection signal.

Abstract: A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

Abstract: A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also include a sense amplifier configured to sense and amplify the data stored in the data storage region and output output data. Further, the semiconductor memory apparatus may also include an enable signal generation block configured to generate a write driver enable signal and a sense amplifier enable signal according to a comparison result of the input data and the output data.

Abstract: A resistive memory device includes a plurality of memory cells, each of which is configured to store a normal data, a first reference data corresponding to a first resistance state and a second reference data corresponding to a second resistance state, a data copy unit configured to temporarily store the normal data read from a selected memory cell and generate a copied cell current based on the stored normal data, a mirroring block configured to temporarily store the first and second reference data read from the selected memory cell, and to generate a first reference current and a second reference current based on the stored first and second reference data, respectively, and a sensing unit configured to sense the stored normal data based on the copied cell current and the first reference current and the second reference current.

Abstract: An internal voltage generation circuit includes: a selection unit configured to select one of first and second reference voltages as a selection reference voltage in response to a self refresh signal and a power-down mode signal and output the selection reference voltage; a driving signal generation unit configured to compare the selection reference voltage with a negative word line voltage applied to an unselected word line and generate a driving signal; and a driving unit configured to change the negative word line voltage in response to the driving signal.

Abstract: Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells. The staircase voltage generator generates a staircase voltage having a staircase waveform that varies in at least two steps. The decode and level shift circuit selects one of said plurality of bit lines and applies the staircase voltage as a program voltage to the selected bit line.

Abstract: A semiconductor device includes a data output circuit suitable for transferring an output data to an external data line during a data output operation, and a controller suitable for generating control signals for controlling the data output circuit during the data output operation, wherein the data output circuit senses a variation and transfers the output data to the external data line based on the sensing result.

Abstract: FORMING reversible resistivity-switching elements is described herein. The FORMING voltage may be halted if the current through the memory cell reaches some reference current. The reference current may depend on how many groups of memory cells have been FORMED. This can help to increase the accuracy of determining when to halt the FORMING voltage. After the FORMING voltage is applied, a RESET voltage may be applied to those memory cells that have a resistance that is lower than a reference resistance to raise the resistance of those memory cells. By raising the resistance, the leakage current of these memory cells when other groups are programmed may be less. This, in turn, helps to prevent FORMING of the other groups from slowing down. A reason why this helps to prevent the slowdown is that the FORMING voltage may be kept near a desired level.

Abstract: A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.

Abstract: Methods and apparatuses for reduction of Read Disturb errors in a memory system utilizing modified or extra memory cells.

Abstract: A method includes determining a plurality of first current values of a first current to be sunk by a tracking cell of a tracking circuit in response to a plurality of first voltage values of a first voltage applied to the tracking cell. Each first current value of the plurality of first current values thereby corresponds to a first voltage value of the plurality of first voltage values. A second current value of a second current is determined. The second current value corresponds to a second voltage value of a second voltage of a memory cell of a plurality of memory cells. A third voltage value is selected based on the second current value, a first current value of the plurality of first current values, and a first voltage value corresponding to the first current value.

Abstract: A nonvolatile memory apparatus includes a read/write control unit and a voltage generation unit and the memory cell. The read/write control circuit is configured to supply a bias voltage in response to a read control signal, a write control signal and data. The voltage generation unit is configured to compare a level of the bias voltage with a voltage level of a sensing node and drive the sensing node at voltage having a constant level based on a result of the comparison. The memory cell coupled with the sensing node and configured to receive the voltage having the constant level.