Including Reference Or Bias Voltage Generator Patents (Class 365/189.09)
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Patent number: 10192621Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.Type: GrantFiled: March 8, 2018Date of Patent: January 29, 2019Assignee: Renesas Electronics CorporationInventors: Ken Matsubara, Takashi Iwase, Satoru Nakanishi
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Patent number: 10192594Abstract: A semiconductor device includes a voltage hold circuit that raises a second boosted voltage with rise of an output voltage of a booster circuit that generates a first boosted voltage and then maintains the second boosted voltage at a point when the output voltage reaches a hold voltage level after that, and a first switch that short-circuits a first output terminal through which the first boosted voltage is output and a second output terminal through which the second boosted voltage is output until the output voltage reaches the hold voltage level.Type: GrantFiled: February 17, 2017Date of Patent: January 29, 2019Assignee: Renesas Electronics CorporationInventors: Masao Yamashiro, Tatsuya Bando, Kunitoshi Kamada, Hiroshi Sato
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Patent number: 10175906Abstract: In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.Type: GrantFiled: July 31, 2014Date of Patent: January 8, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Naveen Muralimanohar, Erik Ordentlich, Cong Xu
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Patent number: 10153032Abstract: The present disclosure provides a pump system of a DRAM and a method for operating the same. The pump system includes a pump device and a spare pump assembly. The pump device provides a current sufficient to allow a bank of the DRAM to operate at a normal refresh rate without other spare pump devices in response to a normal instruction which indicates that the bank is instructed to operate at the normal refresh rate. The spare pump assembly includes a first spare pump device configured to provide, in combination with the pump device, a current sufficient to allow the bank to operate at a first refresh rate greater than the normal refresh rate in response to a first instruction which indicates that the bank is instructed to operate at the first refresh rate.Type: GrantFiled: June 12, 2017Date of Patent: December 11, 2018Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Ting-Shuo Hsu
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Patent number: 10147492Abstract: A non-differential sense amplifier circuit for reading out information in Non-Volatile Memories (NVMs) is disclosed. The circuit comprises a half latch, a PMOSFET device, a switch device and a reset transistor. The PMOSFET device has a source electrode connected to a digital voltage rail, a drain electrode connected to an output node of the half latch and a gate electrode connected to a bitline path coupled with a selected NVM cell. After the bitline path is pre-charged and the reset transistor is turned off, applying a read voltage to a word line related to the selected NVM cell causes a voltage at the gate electrode of the PMOSFET device to drop differently according to an electrical conductance state of the selected NVM cell. The disclosed circuitries can achieve extra low power consumption and high sensing speed compared to those in the conventional sensing scheme.Type: GrantFiled: November 27, 2017Date of Patent: December 4, 2018Assignee: FLASHSILICON INCORPORATIONInventor: Lee Wang
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Patent number: 10140047Abstract: The data storage system includes a memory, a hard disk, and a processing unit. A first logical address and a second logical address in a first logical block of the memory correspond to a piece of duplicated data, and the duplicated data is stored in two physical pages in the hard disk. When executing a de-duplication command, the processing unit transfers the duplicated data to a physical page mapped to a third logical address in a second logical block of the memory; the physical page has a third physical address, and the processing unit updates a first mapping relationship to make it provide a mapping relationship between the first logical address and the third logical address and a mapping relationship between the second logical address and the third logical address, and stores the mapping relationship between the third logical address and the third physical address in the memory.Type: GrantFiled: September 6, 2016Date of Patent: November 27, 2018Assignee: ACCELSTOR, INC.Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
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Patent number: 10110121Abstract: A charge pump includes a first unidirectional conducting device, a flying capacitor, a second unidirectional conducting device, an output capacitor, a first switch, and a second switch. The first unidirectional conducting device unidirectionally couples a supply voltage to an internal node. The flying capacitor is coupled between the internal node and a clock signal. The second unidirectional conducting device unidirectionally couples the internal node to an output node. The output capacitor is coupled between the output node and a ground. The first switch couples a discharge node to the ground according to a discharge signal. The second switch couples the output node to the discharge node according to the voltage of the internal node.Type: GrantFiled: October 5, 2017Date of Patent: October 23, 2018Assignee: FORTEMEDIA, INC.Inventors: Ion Opris, Abu Hena M Kamal, Lee Tay Chew, Shomo Chen
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Patent number: 10084311Abstract: A voltage generator includes a first voltage generation unit and a second voltage generation unit suitable for generating a second power supply voltage using a first power supply voltage, and being selectively driven, and a control signal generation unit suitable for activating the first voltage generation unit until the second power supply voltage reaches a specific level and activating the second voltage generation unit after the second power supply voltage reaches the specific level. The first voltage generation unit has less driving ability than the second voltage generation unit.Type: GrantFiled: September 10, 2015Date of Patent: September 25, 2018Assignee: SK Hynix Inc.Inventor: Young-Sub Yuk
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Patent number: 10073623Abstract: A memory system, may include: a memory device including a plurality of memory blocks each including a plurality of stacked word lines; and a controller suitable for dividing the plurality of word lines into two or more word line groups according to heights thereof, programming data of a relatively high access frequency into a word line group having word lines of relatively low physical heights and data of a relatively low access frequency into a word line group having word lines of relatively high physical heights among the word line groups included in each of the memory blocks.Type: GrantFiled: June 29, 2017Date of Patent: September 11, 2018Assignee: SK Hynix Inc.Inventor: Byoung-Sung You
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Patent number: 10056121Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.Type: GrantFiled: March 6, 2017Date of Patent: August 21, 2018Assignees: ARM Limited, The Regents of the University of MichiganInventors: Mahmood Khayatzadeh, Massimo Bruno Alioto, David Theodore Blaauw, Dennis Michael Chen Sylvester, Fakhruddin Ali Bohra
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Patent number: 10050044Abstract: The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.Type: GrantFiled: February 2, 2017Date of Patent: August 14, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Ping Huang, Chun-Hsien Huang, Yu-Tse Kuo, Ching-Cheng Lung
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Patent number: 10037802Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.Type: GrantFiled: September 15, 2016Date of Patent: July 31, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack Morrish
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Patent number: 10026489Abstract: The present technique relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device having improved reliability includes an address decoder applying a program voltage to a selected word line coupled to selected memory cells, among the plurality of memory cells, and a read and write circuit applying a program permission voltage or a program inhibition voltage to bit lines coupled to the selected memory cells, and a control logic controlling the read and write circuit to sequentially apply the program permission voltage and the program inhibition voltage to the bit lines coupled to the selected memory cells when the program voltage is applied.Type: GrantFiled: August 16, 2016Date of Patent: July 17, 2018Assignee: SK hynix Inc.Inventors: Hee Youl Lee, Hye Eun Heo
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Patent number: 10018680Abstract: A semiconductor device, a battery monitoring system, and a method for activating the semiconductor device that may reduce current consumption in standby state. An integrated circuit (IC) of the semiconductor device includes an activation circuit that uses a ground of the IC as ground and a power source voltage of the IC as its power source, and a driving circuit that uses the power source voltage as ground and a boosted voltage output from a boosting circuit as its power source. In the IC, only the activation circuit enters an operation state in a standby state, and when recovered from the standby state, causes the activation circuit to make inner circuits of the IC enter the operation state based on an activation signal. When all the inner circuits enter the operation state, the driving circuit outputs the activation signal to the activation circuit of an upper IC.Type: GrantFiled: August 12, 2015Date of Patent: July 10, 2018Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Hidekazu Kikuchi
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Patent number: 10008259Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses are described. A memory includes an array of cells for storing data and a sense amplifier for controlling access to the array. The cells receive word line inputs for data access driven by a first voltage supply. The sense amplifier includes first precharge logic, which receives a first precharge input driven by the first power supply used by the array. Therefore, the first precharge input has similar timing characteristics as the word line input used in the array. The sense amplifier includes second precharge logic, which receives a second precharge input driven by a second power supply not used by the array and provides precharged values on bit lines driven by the second power supply.Type: GrantFiled: December 7, 2016Date of Patent: June 26, 2018Assignee: Advanced Micro Devices, Inc.Inventor: Ryan Thomas Freese
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Patent number: 10002657Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory cell configured to operate in multiple retention states including a static retention state and a dynamic retention state. The integrated circuit may include a controller configured to selectively apply different voltage levels to the memory cell based on the retention state of the memory cell.Type: GrantFiled: March 25, 2016Date of Patent: June 19, 2018Assignee: The Regents of the University of MichiganInventors: Byoungchan Oh, Sandunmalee Abeyratne, Ronald G. Dreslinski, Jr., Trevor Mudge
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Patent number: 9997228Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.Type: GrantFiled: October 7, 2016Date of Patent: June 12, 2018Assignee: SK hynix Inc.Inventors: Jae Seung Lee, Chang Hyun Kim, Yo Sep Lee
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Patent number: 9993175Abstract: A pulsed ultra-wideband sensor comprises a control unit designed for forming a time delay of a synchronizing pulse, a probing signal forming path, a transmitting antenna, a receiving antenna, a path of a probing signal transmitter, with an output of said path being connected to the transmitting antenna, a path of a return signal receiver, with an input of the path being connected to the receiving antenna, and a first electronic switch. The input of the first electronic switch is connected to the output of the path for forming a probing signal, and its outputs—to the input of the path of the probing signal transmitter and to the path of a return signal receiver. The outputs of the channels for processing a return signal, which are parts of the path of the return signal receiver, are connected to the path for calculating a respiratory rate and a heart rate.Type: GrantFiled: July 17, 2015Date of Patent: June 12, 2018Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Teh Ho Tao, Igor Yakovlevich Immoreev, Maksim Vladimirovich Fesenko
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Patent number: 9978435Abstract: A memory device includes a memory array including a plurality of memory cells coupled to a plurality of bitlines and a plurality of wordlines and a plurality of sense amplifier circuits coupled to the plurality of bitlines. Each sense amplifier circuit includes a sense amplifier configured to sense and amplify a voltage difference between two of the bitlines coupled thereto. The memory device further includes an address decoder to receive and decode addresses of memory cells to enable corresponding bitlines and wordlines, a refresh controller to control data refreshing of the memory cells, and a mode controller to control the memory device to operate in different operating modes including a deep power down (DPD) mode. The mode controller controls data of a group of the memory cells, sensed by corresponding ones of the sense amplifier circuits, to be latched in the corresponding sense amplifier circuits when entering the DPD mode.Type: GrantFiled: January 25, 2017Date of Patent: May 22, 2018Assignee: Winbond Electronics CorporationInventor: San-Ha Park
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Patent number: 9977480Abstract: Selective coupling of power rails to memory domain(s) in processor-based system, such as to reduce or avoid the need to provide intentional decoupling capacitance in logic domain(s) is disclosed. To avoid or reduce providing additional intentional decoupling capacitance in logic domain to mitigate voltage droops on logic power rail, power rail selection circuit is provided. The power rail selection circuit is configured to couple memory domain to a logic power rail when the logic power rail can satisfy a minimum operating voltage of memory arrays. The additional intrinsic decoupling capacitance of the memory arrays is coupled to the logic power rail. However, if the operating voltage of the logic power rail is scaled down below the minimum operating voltage of the memory arrays when the logic domain does not need higher operation functionality, the power rail selection circuit is configured to couple the memory domain to separate memory power rail.Type: GrantFiled: March 31, 2016Date of Patent: May 22, 2018Assignee: QUALCOMM IncorporatedInventors: Yeshwant Nagaraj Kolla, Neel Shashank Natekar
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Patent number: 9978441Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.Type: GrantFiled: February 28, 2017Date of Patent: May 22, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Chika Tanaka, Keiji Ikeda, Toshinori Numata, Tsutomu Tezuka
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Patent number: 9934864Abstract: A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.Type: GrantFiled: February 2, 2017Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Patent number: 9928898Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.Type: GrantFiled: March 30, 2016Date of Patent: March 27, 2018Assignee: QUALCOMM IncorporatedInventors: Rahul Sahu, Sharad Kumar Gupta
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Patent number: 9928917Abstract: A memory device includes a memory cell, a bit line connected to the memory cell, a control voltage generator configured to generate a proportional to absolute temperature (PTAT) current and generate an analog control voltage inversely proportional to the PTAT current, and a load current control circuit configured to control a first load current supplied to the bit line based on the analog control voltage.Type: GrantFiled: February 23, 2017Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Jin Shin, Ho Young Shin
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Patent number: 9928918Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.Type: GrantFiled: January 9, 2017Date of Patent: March 27, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: Jin-Ki Kim, Peter B. Gillingham
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Patent number: 9922695Abstract: An apparatus comprises: a source array of memory cells with associated source sense amplifiers; a destination array of memory cells with associated destination sense amplifiers; and logic to activate a source word-line (WL) to select a row of memory cells within the source array such that data in the selected row of memory cells is latched by the associated source sense amplifiers, wherein the logic to activate a destination WL to select a row of memory cells within the destination array such that data in the selected row of memory cells is latched by the associated destination sense amplifiers, and wherein the source and destination arrays of memory cells are within a same bank of a memory.Type: GrantFiled: March 25, 2015Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Shigeki Tomishima, Shih-Lien L. Lu
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Patent number: 9917584Abstract: A bootstrap circuit integrated to a voltage converter integrated circuit (IC) and a voltage converter IC for a switch mode voltage regulator. The bootstrap circuit is used to provide a bootstrap voltage signal for driving a high side switch of the voltage converter IC. The bootstrap circuit has a pre-charger and a bootstrap capacitor. The pre-charger provides a first bootstrap signal to pre-charge a control terminal of the high side switch, and the bootstrap capacitor provides a second bootstrap signal to enhance the charge of the control terminal of the high side switch.Type: GrantFiled: September 21, 2016Date of Patent: March 13, 2018Assignee: Chengdu Monolithic Power Systems Co., Ltd.Inventors: Junyong Gong, Jian Jiang, Yike Li, Changjiang Chen
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Patent number: 9912353Abstract: Systems and methods are provided for generating a soft information metric corresponding to a bit stored in a memory. The systems and methods include comparing a symbol value associated with the stored bit to a plurality of decision thresholds to obtain a plurality of binary values. One of the plurality of binary values is selected to obtain a reference value. Further, a frequency metric is computed, which corresponds to the number of times each of the plurality of binary values equals a predefined value. The soft information metric is then determined based on the frequency metric and the reference value.Type: GrantFiled: March 10, 2016Date of Patent: March 6, 2018Assignee: Marvell International Ltd.Inventor: Seo-How Low
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Patent number: 9899089Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: GrantFiled: September 24, 2013Date of Patent: February 20, 2018Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Patent number: 9899091Abstract: There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.Type: GrantFiled: June 22, 2017Date of Patent: February 20, 2018Assignee: SK hynix Inc.Inventors: Yeong Joon Son, Jin Su Park
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Patent number: 9891855Abstract: A memory device is provided which is capable of adjusting an operation voltage, and an application processor is provided for controlling the memory device. The memory device may include: a receiving terminal for receiving a voltage control signal from an external source, the voltage control signal being for adjusting an operation voltage level according to an operation speed of the memory device; and a voltage adjustment unit for adjusting a level of an operation voltage of the memory device in response to the voltage control signal. The level of the operation voltage is adjusted before a memory operation is performed at the operation speed corresponding to the adjusted operation voltage.Type: GrantFiled: February 21, 2017Date of Patent: February 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hui-Kap Yang, Myung-Kyoon Yim, Soo-Hwan Kim
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Patent number: 9881671Abstract: A method is for operating a resistive memory system including a resistive memory device implemented as multi-level memory cells. The method includes setting levels of reference voltages used to determine resistance states of the multi-level memory cells, and reading data of the multi-level memory cells based on the reference voltages. A difference between the reference voltages used to determine a relatively high resistance state is greater than a difference between the reference voltages used to determine a relatively low resistance state.Type: GrantFiled: February 16, 2016Date of Patent: January 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Chu Oh, Young-Geon Yoo, Jun Jin Kong, Hong-Rak Son, Han-Shin Shin
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Patent number: 9881661Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.Type: GrantFiled: June 3, 2016Date of Patent: January 30, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Xinwei Guo, Daniele Vimercati
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Patent number: 9870821Abstract: An electronic device including a semiconductor memory is disclosed. The semiconductor memory includes a read path including a unit storage cell; a reference path including a unit reference cell; read circuit suitable for comparing a read current flowing on the read path with a reference current flowing on the reference path in response to a read voltage and a reference voltage, and sensing data stored in the unit storage cell based on the comparison result; a first replica path suitable for modeling the read path; and a reference voltage generation unit suitable for generating the reference voltage corresponding to a first replica current flowing on the first replica path in response to the read voltage.Type: GrantFiled: December 31, 2014Date of Patent: January 16, 2018Assignee: SK hynix Inc.Inventor: Hyuck-Sang Yim
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Patent number: 9865333Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.Type: GrantFiled: April 19, 2016Date of Patent: January 9, 2018Assignee: STMicroelectronics International N.V.Inventors: Kedar Janardan Dhori, Ashish Kumar, Hitesh Chawla, Praveen Kumar Verma
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Patent number: 9858988Abstract: A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.Type: GrantFiled: July 8, 2016Date of Patent: January 2, 2018Assignee: QUALCOMM IncorporatedInventors: Sonia Ghosh, Changho Jung
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Patent number: 9858970Abstract: A power supply circuit includes a first transistor and a second transistor electrically coupled between a power supply terminal and an output terminal. When a first current path, in which output terminal through the first transistor, is formed, a voltage level of the output terminal may be controlled to be greater than or equal to a predetermined level. When a second current path, in which a current flows from the power supply terminal to the output terminal through the second transistor, is formed, the voltage level of the output terminal may be controlled to be less than or equal to the predetermined level.Type: GrantFiled: July 23, 2015Date of Patent: January 2, 2018Assignee: SK Hynix Inc.Inventor: Bon Kwang Koo
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Patent number: 9859207Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.Type: GrantFiled: August 24, 2016Date of Patent: January 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kwang-Soo Kim
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Patent number: 9847716Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first output, a second charge pump circuit configured to provide a second output, a plurality of coupling circuits configured to voltage couple and current couple the first output and the second output to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first output and the second output based on the regulated voltage.Type: GrantFiled: July 3, 2017Date of Patent: December 19, 2017Assignee: Micron Technology, Inc.Inventors: Xiaojiang Guo, Qiang Tang
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Patent number: 9830960Abstract: A memory device may include a data output circuit configured to multiplex a plurality of data signals read from a memory cell array, wherein the data output circuit includes a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage, and a data output driver configured to multiplex and output the plurality of data signals synchronized with the boosted clock signals.Type: GrantFiled: October 17, 2016Date of Patent: November 28, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-kyo Lee, Won-young Lee, Bo-bae Shin, Jung-hwan Choi, Yong-cheol Bae, Seok-hun Hyun, Min-su Ahn
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Patent number: 9823719Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: May 31, 2013Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 9812193Abstract: A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a lower bound for a given bin and (2) performing a second read on the group of solid state storage cells at a second threshold that corresponds to an upper bound for the given bin. A minimum is determined using the bit flip counts corresponding to the plurality of bins and the minimum is used to estimate an optimal threshold.Type: GrantFiled: September 9, 2014Date of Patent: November 7, 2017Assignee: SK Hynix Inc.Inventors: Christopher S. Tsang, Frederick K. H. Lee, Xiangyu Tang, Zheng Wu, Jason Bellorado
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Patent number: 9805791Abstract: A resistive memory structure comprises at least one resistive memory element configured to store one or more bits of data and a circuit electrically connected to the resistive memory element for use in performing at least one of a read or write operation on the at least one resistive memory element. The circuit includes a resistor electrically connected in series to the resistive memory element thereby forming a voltage divider and electrical node therebetween, and an interpretation circuit electrically connected to the electrical node formed between the resistive memory element and the resistor. The interpretation circuit is configured to interpret a voltage at the electrical node and to determine a resistive state of the resistive memory element based on the voltage at the electrical node.Type: GrantFiled: December 17, 2013Date of Patent: October 31, 2017Assignee: The Regents of the University of MichiganInventors: Yalcin Yilmaz, Pinaki Mazumder
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Patent number: 9786357Abstract: In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage distribution circuit may connect a word line driver circuit to a bit-cell voltage circuit such that an operating voltage is received at a bit-cell circuit before a word line signal form the word line driver circuit is received at the bit-cell circuit, where the operating voltage is provided by the bit-cell voltage circuit. The method may further include the bit-cell circuit providing the operating voltage along a bit line based on a data stored at the bit-cell circuit and based on the word line signal. In some embodiments, a static noise margin of one or more portions of the bit-cell circuit may be improved. Additionally, in some cases, a wakeup time of the bit-cell circuit may be ignored, resulting in a faster read operation.Type: GrantFiled: February 17, 2016Date of Patent: October 10, 2017Assignee: Apple Inc.Inventors: Mohamed H. Abu-Rahma, Yildiz Sinangil
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Patent number: 9767907Abstract: A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.Type: GrantFiled: March 28, 2016Date of Patent: September 19, 2017Assignee: STMICROELECTRONICS S.R.L.Inventors: Salvatore Polizzi, Giovanni Campardo
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Patent number: 9754645Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.Type: GrantFiled: October 27, 2015Date of Patent: September 5, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Anirudh Amarnath, Tai-Yuan Tseng
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Patent number: 9747993Abstract: Technologies are generally described for a memory system that may be a solid-state drive (SDD). The memory system may include memory blocks, where each memory block may have multiple memory pages, and each memory page may have multiple memory cells. The memory cells may have multiple programmed states. In various examples, a method to control the memory system may include determining one or more memory pages to be analyzed, identifying read threshold voltages of each memory cell associated with the memory pages to be analyzed, performing statistical analysis on the identified read threshold voltages, and determining a distribution of the read threshold voltages based at least in part on the statistical analysis.Type: GrantFiled: August 13, 2013Date of Patent: August 29, 2017Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Hyoung-Gon Lee
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Patent number: 9747966Abstract: According to one embodiment, a semiconductor memory device includes a memory cell; a reference signal generation circuit; a sense amplifier; a first transistor configured to electrically couple the memory cell and a first input terminal of the sense amplifier; a second transistor configured to electrically couple the reference signal generation circuit and a second input terminal of the sense amplifier; a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor; a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor; and a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor.Type: GrantFiled: March 9, 2016Date of Patent: August 29, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Katsuyuki Fujita
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Patent number: 9727416Abstract: An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data.Type: GrantFiled: July 1, 2015Date of Patent: August 8, 2017Assignee: XILINX, INC.Inventor: Christopher H. Dick
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Patent number: 9722489Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first output, a second charge pump circuit configured to provide a second output, a plurality of coupling circuits configured to voltage couple and current couple the first output and the second output to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first output and the second output based on the regulated voltage.Type: GrantFiled: May 2, 2016Date of Patent: August 1, 2017Assignee: Micron Technology, Inc.Inventors: Xiaojiang Guo, Qiang Tang