Data Transfer Circuit Patents (Class 365/189.17)
  • Patent number: 9965415
    Abstract: Provided are a memory device and a memory bank comprising a split local data bus, and a segmented global data bus coupled to local data bus. Provided also is a method comprising, receiving a signal from a split local data bus, and transmitting the signal to a segmented global data bus coupled to local data bus. Provided also is a computational device that includes the memory device and the memory bank, and optionally one or more of a display, a network interface, and a battery.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Wei Wu, Shigeki Tomishima, Shih-Lien L. Lu
  • Patent number: 9959923
    Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: May 1, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Glen E. Hush
  • Patent number: 9727465
    Abstract: A method to monitor the behavior of a working set cache of a full data set at run time and determine whether it provides a performance benefit is disclosed. An effectiveness metric of the working set cache is tracked over a period of time by efficiently computing the amount of physical memory consumption the cache saves and comparing this to a straightforward measure of its overhead. If the effectiveness metric is determined to be on an ineffective side of a selected threshold amount, the working set cache is disabled. The working set cache can be re-enabled in response to a predetermined event.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: August 8, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: David J. Hiniker-Roosa
  • Patent number: 9588543
    Abstract: A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: March 7, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tsung-Huang Chen, Li-Chun Tu, Wen-Chi Chao
  • Patent number: 9472278
    Abstract: A voltage generator and an oscillation device, and an operation method thereof are disclosed. The oscillation device includes a non-volatile memory, the voltage generator and a voltage-controlled oscillation (VCO) circuit. The voltage generator uses the non-volatile resistance provided by a non-volatile memory to generate a bias voltage. The VCO circuit is coupled to the voltage generator so as to generate a corresponding oscillation frequency based on the bias voltage.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 18, 2016
    Assignee: Nuvoton Technology Corporation
    Inventor: Cheng-Chih Wang
  • Patent number: 9424902
    Abstract: A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 23, 2016
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chung-Ching Chen, Chen-Nan Lin, Yung Chang
  • Patent number: 9355686
    Abstract: A semiconductor chip comprises a word line configured to be driven by a word line driver. The semiconductor chip also comprises a plurality of bit lines. Each bit line of the plurality of bit lines is configured to transmit a signal to a respective bit line amplifier. The semiconductor device further comprises a plurality of memory cells. At least one memory cell of the plurality of memory cells is at an intersection of the word line and a bit line of the plurality of bit lines. The at least one memory cell of the plurality of memory cells is a type selected from at least two memory cell types based on a distance of the intersection from an end of the word line.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: May 31, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng Hung Lee, XiuLi Yang, Liangbo Zhuang
  • Patent number: 9147450
    Abstract: A semiconductor memory apparatus includes a first data storage region configured to be supplied with a driving voltage via a first voltage line, a second data storage region configured to be supplied with a driving voltage via a second voltage line and a switch configured to one of electrically couple the first voltage line with the second voltage line and decouple the first voltage line from the second voltage line in response to a switching control signal.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: September 29, 2015
    Assignee: SK Hynix Inc.
    Inventor: Kyeong Pil Kang
  • Patent number: 9111603
    Abstract: An integrated circuit may include a memory controller that interfaces with memory via one or more ports. A given port may be coupled to a comparator that receives data signals from the memory and a reference voltage signal and produces a corresponding output signal that identifies whether the data signals are logic one signals or logic zero signals. The memory controller may include detection circuitry coupled to the port that produces a target reference voltage signal for calibration of the reference voltage signal. The memory controller may include circuitry that produces the reference voltage signal based on control signals received from control circuitry. The control circuitry may generate the control signals to calibrate the reference voltage signal based on the target reference voltage.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 18, 2015
    Assignee: Altera Corporation
    Inventors: Xiaobao Wang, Chiakang Sung, Joseph Huang
  • Patent number: 9042160
    Abstract: A method includes, in a data storage device that includes a non-volatile memory and a resistive random access memory (ReRAM) on the same die, receiving data from a memory controller via a bus. The method also includes routing the data to data latches of the non-volatile memory via a first path and to the ReRAM via a second path distinct from the first path.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 26, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Sergey Anatolievich Gorobets, Aaron Keith Olbrich, Manuel Antonio D'Abreu, Xinde Hu
  • Patent number: 9036433
    Abstract: A data transfer circuit includes a plurality of first lines, a second line suitable for receiving data from a first line selected among the first lines, a third line suitable for transferring data to the first line selected among the first lines, a plurality of driving units, each suitable for driving the second line based on the data from the corresponding first line in a first operation, and a plurality of connection units, each suitable for coupling the third line to the corresponding first line when the corresponding first line is selected in a second operation.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sang-Oh Lim
  • Patent number: 9030859
    Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: May 12, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Raul-Adrian Cernea
  • Patent number: 9030894
    Abstract: A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: May 12, 2015
    Assignee: MoSys, Inc.
    Inventors: Richard S. Roy, Dipak Kumar Sikdar
  • Patent number: 9026725
    Abstract: Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Alexey Kostinsky, Zvika Greenfield, Christopher P. Mozak, Pavel Konev, Olga Fomenko
  • Patent number: 9019785
    Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Steven M. Bodily
  • Publication number: 20150109869
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Masayasu KOMYO, Yoichi Ilzuka
  • Patent number: 9013937
    Abstract: A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 9007865
    Abstract: According to some embodiments, an electronic circuit comprises a digital output which is held to a logic one after the power supply was removed, for a time duration in a narrow range. The electronic circuit comprises a first array of elements comprising capacitors and discharging devices (diodes or transistors). A time constant detector detects which elements has the discharging time closest to the target. A second array of elements also comprises capacitors and discharging devices, with discharging durations proportional to the discharging durations of the first array. A decoder charges the appropriate element from the second array. After the power is removed, this charged element starts to discharge. During the discharge duration, a comparator outputs a logic one, and a logic zero after the discharge is completed.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 14, 2015
    Inventor: Ion E. Opris
  • Publication number: 20150085589
    Abstract: Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Inventors: Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang
  • Patent number: 8982645
    Abstract: A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a first data line and is turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line. A second amplifier is coupled to the first data line and amplifies, when activated, the first data signal, and is further coupled to the first signal line and activated in response to a first activation signal that is transferred through a first signal line. A second transistor is coupled to the first signal line and is turned ON in response to the first selection signal to the first signal line.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 17, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8982649
    Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: March 17, 2015
    Assignee: GSI Technology, Inc.
    Inventors: Robert Haig, Patrick Chuang, Chih Tseng, Mu-Hsiang Huang
  • Patent number: 8982639
    Abstract: A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Young Kim, Myung-Hoon Choi
  • Patent number: 8977816
    Abstract: A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 10, 2015
    Assignee: OCZ Storage Solutions Inc.
    Inventor: Soo Gil Jeong
  • Patent number: 8971131
    Abstract: A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bing Wang
  • Patent number: 8971108
    Abstract: A semiconductor memory device includes a first semiconductor chip including a first pad group configured to input/output first data and a second pad group configured to input/output second data; and a second semiconductor chip in a stack with the first semiconductor chip and configured to be electrically connected to the first semiconductor chip by at least one chip through via, wherein the second semiconductor chip includes a first unit bank group including at least one first upper bank group and at least one first lower bank group, a second unit bank group including at least one second upper bank group and at least one second lower bank group, and a data path selector configured to electrically connect one among the first and second upper bank groups and the first and second lower bank groups with the chip through via.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: March 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Heat-Bit Park
  • Patent number: 8971139
    Abstract: A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 3, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20150055398
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.
    Type: Application
    Filed: November 10, 2014
    Publication date: February 26, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Masayasu KOMYO, Yoichi IIZUKA
  • Patent number: 8964483
    Abstract: A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 24, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Kazuhiko Kajigaya, Kazuo Ono, Tomonori Sekiguchi
  • Patent number: 8964470
    Abstract: Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two separate sourcelines for the paired flash Strings are also proposed for easy adding ability for the NVSRAM circuit to detect the marginally erased Vt0 and marginally programmed Vt1 of the paired flash cell. By increasing an resistance added to common SRAM power line, the pull-down current through flash Strings to grounding source line can be made much larger than the pull-up current to improve SFwrite program operation. Simple method by increasing flash cell channel length to effectively enhance coupling area is applied to secure SRAM-to-Flash store operation under self-boost-program-inhibit scheme. 1S2F architecture also provide flexibility for alternate erasing and programming during both a recall and store operation.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Aplus Flash Technology, Inc.
    Inventor: Peter Wung Lee
  • Patent number: 8958227
    Abstract: Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: February 17, 2015
    Assignee: CrossFire Technologies, Inc.
    Inventors: Kevin Atkinson, Clifford H. Boler
  • Patent number: 8958255
    Abstract: A semiconductor storage apparatus according to the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of pairs of bit lines, a plurality of sense amplifiers, a pair of common data lines, a data-to-be-written output circuit configured to, in writing data, set voltages of the common data lines forming the pair, a column selection signal output unit configured to output a plurality of column selection signals, and a plurality of column selection gates, in which in writing the data, the column selection signal output unit selectively turns on one of the column selection gates by setting each of voltages of the column selection signals to one of a level of a higher-potential power supply voltage and a level of a lower-potential power supply voltage, before activating the sense amplifiers.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Takahashi, Masahiro Yoshida
  • Patent number: 8953390
    Abstract: According to one embodiment, a semiconductor memory device includes n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m×n data latch circuits connected to the buses, with m (m being a natural number of 2 or more) data latch circuits being connected per one of the buses; and a selection circuit configured to simultaneously perform data transfer from/to the data retention circuits for a plurality of the data latch circuits in units of a group including the plurality of the data latch circuits, the data latch circuits being divided into the groups so that not all the data latch circuits connected to the same bus are included in the same group.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatsugu Ogawa, Teruo Takagiwa
  • Patent number: 8953391
    Abstract: A semiconductor apparatus includes an input buffer configured to buffer and output data inputted from a data input/output pad; a data input control unit configured to transfer data outputted from the input buffer; a data output control unit configured to transfer inputted data to an output buffer; the output buffer configured to buffer data outputted from the data output control unit, and output the buffered data to the data input/output pad; a test data input/output unit configured to latch test inputted data inputted and output test latch data or latch an output of the input buffer and output the test latch data; and a test loop control unit configured to transfer data or the test latch data to the data output control unit.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: February 10, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young Jun Yoon
  • Patent number: 8947954
    Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 3, 2015
    Assignee: Mentor Graphics Corporation
    Inventor: Peer Schmitt
  • Patent number: 8947956
    Abstract: A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 3, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jeong-Tae Hwang
  • Patent number: 8947929
    Abstract: The present disclosure describes techniques for flash-based soft information generation. In some aspects a flash-memory device includes a soft information generator configured to determine soft information for a data value stored by a flash-memory cell. The soft information includes fewer bits than a number of data bits read from the flash-memory cell from which the soft information is generated. When the flash-memory device transfers the soft information to a memory controller, fewer bits per data value are transferred. By so doing, an efficiency of a data link between the flash memory device and the memory controller may be improved.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 3, 2015
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Patent number: 8947952
    Abstract: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Chulmin Jung
  • Patent number: 8947942
    Abstract: A semiconductor memory chip includes a first pad unit configured to receive a first data and a first strobe signal, and a first selection transfer unit configured to transfer the first data and the first strobe signal to a first write path circuit in a first mode, and transfer the first data and the first strobe signal to a second write path circuit in a swap mode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Bok Rim Ko, Kwang Soon Kim
  • Publication number: 20150016201
    Abstract: A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.
    Type: Application
    Filed: November 26, 2013
    Publication date: January 15, 2015
    Applicant: SK hynix Inc.
    Inventors: Hye-Young LEE, Kie-Bong KU, Choung-Ki SONG, Sung-Hwa OK, Se-Jin YOO
  • Publication number: 20150003175
    Abstract: Memory devices, controllers, and electronic devices comprising memory devices are described. In one embodiment, a memory device comprises a volatile memory, a nonvolatile memory, and a controller comprising a memory buffer, and logic to transfer data between the nonvolatile memory and the volatile memory via the memory buffer in response to requests from an application, wherein data in the memory buffer is accessible to the application. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventor: Raj K. Ramanujan
  • Patent number: 8923062
    Abstract: A next read threshold is determined by determining a first number of solid state storage cells having a stored voltage which falls into a first voltage range and determining a second number of solid state storage cells having a stored voltage which falls into a second voltage range. A gradient is determine by taking a difference between the first number of solid state storage cells and the second number of solid state storage cells. The next read threshold is determined based at least in part on the gradient.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: December 30, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Arunkumar Subramanian, Lingqi Zeng, Xiangyu Tang, Ameen Aslam
  • Patent number: 8923079
    Abstract: A semiconductor apparatus having a data bit inversion function and, the semiconductor apparatus including a first semiconductor chip and a second semiconductor chip electrically coupled to the first semiconductor chip, wherein the first semiconductor chip may be configured to receive data and a data bit inversion flag, and transfer the data to the second semiconductor chip, and the second semiconductor chip may be configured to invert and store the data, which is transferred from the first semiconductor chip, according to to the data bit inversion flag.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Heat Bit Park, Jong Chern Lee
  • Publication number: 20140369142
    Abstract: A data transfer device 2 has a first bank 31 which has a first bank first memory 311 and a first bank second memory 312, a second bank 32 which has a second bank first memory 321 and a second bank second memory 322, and a control circuit. Write and read operations of both the first bank 31 and second bank 32 are performed in the reference period, and alternately changes to the write state and to the read state in the phase opposite to each other. The control circuit 70 controls the first bank 31 and the second bank 32 so that input data groups are stored sequentially in the first bank 31 and in the second bank 32 and the stored data groups are read sequentially.
    Type: Application
    Filed: June 9, 2014
    Publication date: December 18, 2014
    Inventor: Yoshihiro Kitahara
  • Patent number: 8908449
    Abstract: A master stage (502) of a master-slave flip-flop (500) includes an input terminal (504) for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals, a transmission gate (522) coupled to the input terminal and having an output terminal, a storage element (520) coupled to the output terminal of the transmission gate, and a two-input logic gate (525) having a first input terminal (541) coupled to the storage element, a parallel input terminal (542) coupled to the input terminal of the master stage, and an output terminal (543) that provides an output terminal of the master stage. A slave stage (503) has terminals for receiving second clock signals, wherein first clock signals are delayed relative to second clock signals.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ravindraraj Ramaraju
  • Publication number: 20140355364
    Abstract: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.
    Type: Application
    Filed: October 9, 2013
    Publication date: December 4, 2014
    Applicant: Sk hynix Inc.
    Inventors: Heat-Bit PARK, Kang-Seol LEE
  • Publication number: 20140355363
    Abstract: A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area, a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block, and a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel.
    Type: Application
    Filed: October 1, 2013
    Publication date: December 4, 2014
    Applicant: SK hynix Inc.
    Inventor: Sang-Jin BYEON
  • Patent number: 8902673
    Abstract: A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array, and outputting test result data through one or more test pads. The first data is received from an external device through the one or more test pads, which correspond to one or more of the plurality of data pads. The test result data is based on the rewritten data in the memory cell array.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Beom Kim, Hyun-Soon Jang
  • Patent number: 8902671
    Abstract: A method for programming data is provided for a memory storage device having a rewritable non-volatile memory module and a buffer memory. The method includes receiving a plurality of data including a first-type data and at least one second-type data, and a size of the first-type data is smaller than a data size threshold. The method includes temporarily storing the plurality of data into the buffer memory, and programming the first-type data and at least one part of the at least one second-type data stored in the buffer memory into a physical program unit set if it is determined that the plurality of data are complied with a predetermined condition. The method includes obtaining writing statuses of the first-type data and the at least one part of the at least one second-type data at the same time.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: December 2, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Hong-Lipp Ko, Kuo-Lung Lee, Teng-Chun Hsu
  • Patent number: 8902681
    Abstract: Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Benjamin A. Fox, William P. Hovis, Thomas W. Liang, Paul W. Rudrud
  • Patent number: 8902680
    Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Tadashi Yamamoto