Abstract: In a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. Each of the enable outputs of the switch is connected to an enable input of one of the non-volatile storage units. The switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. In addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. The switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.

Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

Abstract: When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded. A delay adjustment circuit adjusts a delay amount of write data to a memory device. A control circuit sets a delay amount of the delay adjustment circuit. A storage unit stores a delay amount. The control circuit corrects the delay amount stored in the storage unit based on a writing result of write data obtained when the delay amount stored in the storage unit or an amount based on that delay amount is set on the delay adjustment circuit.

Abstract: Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a device that includes an interface for communication with a host. The device includes components that can operate during at least one of read link training and duty cycle distortion compensation operation.

Abstract: A memory device that includes an interface that receives a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal; a strobe buffer that receives the strobe signal from the interface; a phase detection unit that detects a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer; a phase adjust unit that adjusts a phase of the strobe signal output from the strobe buffer based on the phase difference; and a sampling unit that samples the data signal output from the interface based on the strobe signal output from the phase adjust unit.

Abstract: An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

Abstract: A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

Abstract: Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: A semiconductor device includes a plurality of chips, at least one line, and a controller. Each of the chips includes a chip input/output (I/O) pad, a transceiver configured to perform a transmission operation in response to a transmission enable signal or perform a reception operation in response to a reception enable signal, and a switch configured to couple the chip input/output (I/O) pad to the transceiver in response to a switch enable signal. The at least one line is configured to couple the chip input/output (I/O) pads contained in the plurality of chips. The controller generates the transmission enable signal, the reception enable signal, and the switch enable signal in response to a command signal and a chip identifier (ID) signal.

Abstract: An integrated circuit (IC) includes a first device and a second device. A latency measurement circuit is configured to determine a first latency of the first device; and determine a second latency of the second device based on the first latency.

Abstract: Methods and devices for gating an internal data strobe from an input buffer of a memory device. The gating function occurs after a write operation ceases but before an external controller stops driving an external data strobe that is used to generate the internal data strobe. The methods and devices use local counters to count how many pulses have occurred on the data strobe during a write operation. When the local counters indicate that an expected number of cycles for the write operation have elapsed, the local counters indicate that the write operation has completed. This indication causes gating circuitry to cut off the internal data strobe from writing circuitry.

Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y?1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read.

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a bus master, a bus slave and a clock gating circuit. The bus master outputs an access request. The bus slave transmits a response to the access request to the bus master. The clock gating circuit shuts off clocks supplied to the bus slave. The bus slave includes a control circuit which outputs first and second signals in response to the access request; a first circuit which outputs a third signal in response to a clock supplied from the clock gating circuit, when the first signal is asserted; and a second circuit which receives the third signal output from the first circuit and the second signal, and outputs a fourth signal as the response to the bus master, when the second signal is asserted.

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

Abstract: A memory device implements a memory read training method using a dedicated read command to retrieve training data from a register for performing memory read training while the memory device remains operating in the normal operation mode. Subsequent to the memory read training, the memory device may then receive the normal read command to read data from the memory cell array or the normal write command to write data to the memory cell array. In this manner, memory read training is performed simply by issuing read commands and carrying out read operations without requiring the memory device to enter and exit special memory read training mode for performing calibration.

Abstract: An error detection circuit may include a selection unit that sequentially selects a primary data group and a secondary data group according to a first control signal and generates an output signal; a first operation unit that performs an error detection operation on the output signal and outputs a preliminary error operation signal; a storage unit that latches the preliminary error operation signal and output a latched signal according to a second control signal; a second operation unit that performs an error detection operation on a previous preliminary error operation signal outputted from the storage unit and a current preliminary error operation signal outputted from the first operation unit and generates an internal error operation signal; and a comparison unit that compares the internal error operation signal with an external error operation signal and outputs a result of the comparison as an error detection signal.

Abstract: In a method of operating a semiconductor memory device including a memory cell array and a control logic circuit configured to control access to the memory cell array, data synchronized with a differential data clock signal is received from an external memory controller, the data is stored in the memory cell array based on a frequency-divided data clock signal from which the differential data clock signal is divided, data is read from the memory cell array in response to a read command and a target address from the memory controller, and the read data is transmitted to the memory controller with one of a single strobe signal and a differential strobe signal according to a strobe mode of the semiconductor memory device.

Abstract: A clean data strobe signal generating circuit in a read interface device includes receivers configured to output first and second single ended data strobe signals. In the circuit, a gate signal generating unit is configured to generate a data strobe gate signal synchronized with the first single ended data strobe signal using the first and second single ended data strobe signals and a memory gate signal of which the pulse width varies in accordance with a burst length after termination of a read latency. The gating unit is configured to generate a clean data strobe signal using the first single ended data strobe signal and the data strobe gate signal.

Abstract: A semiconductor system includes a controller operatively coupled to a semiconductor device, the controller being suitable in a training mode for receiving an external signal and a first data signal from an external device and for transmitting the received external signal and the first data signal to the semiconductor device; and the semiconductor device being suitable in the training mode for determining a level of a reference voltage in response to the first data signal, and for transmitting a second data signal to the controller by buffering the external signal based on the reference voltage without performing a termination operation during an output period of the second data signal, wherein the controller controls an enable timing of the external signal by receiving the second data signal.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The bit lag control element has delay lock control and a gray encoder.

Abstract: According to certain general aspects, the present embodiments relate to methods and apparatuses for performing read and write data path training in HBMs. In accordance with some aspects, embodiments configure HBM mode registers for read and write data path training using an IEEE 1500 interface is simpler than the traditional scenario. In accordance with other aspects, the logic for performing read and write data path training is independent from normal memory access functionality in the host, capable of independently interacting with a PHY core for performing read and write data path training.

Abstract: A data storage device includes a memory device suitable for storing and outputting data in synchronization with a strobe signal; and a controller suitable for delaying the strobe signal based on each of different test delay values, testing capture of the data by using a delayed strobe signal, and determining a delay value of the strobe signal based on a test result.

Abstract: An integrated circuit including semiconductor devices may be provided. The semiconductor device may be configured to compare phases of strobe signals which are generated according to internal delay times of the semiconductor devices and configured to control points of time that an internal command is inputted to the internal circuits of the semiconductor devices according to a comparison result of the phases of the strobe signals.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output commands and addresses. The first semiconductor device may be configured to output a strobe signal toggled and data after an initialization operation. The second semiconductor device may be configured to start the initialization operation if the commands have a first combination and stores internal data having a predetermined level during a set period of the initialization operation if the commands have a second combination.

Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.

Abstract: An address generation device of a memory system includes an address generator and a synchronizer. The address generator may receive a clock and sequentially generate a first address and a second address after the first address. The synchronizer may synchronize the first address in response to the clock at a preset time point before the second address is generated by the address generator, and output the synchronized address as an output address.

Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: A semiconductor device includes a memory array including a plurality of memory blocks, wherein the memory blocks are grouped into sub-block groups, and the sub-block groups are grouped into main block groups; an operation circuit suitable for performing a read operation and a test read operation on memory cells included in the memory block; and a read counter suitable for counting a first number of read operations for each word line in the respective main block groups and a second number of read operations for the respective sub-block groups.

Abstract: A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.

Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.

Abstract: An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

Abstract: A system and method providing timing alignment of a data mask (DM) signal with respect to a data strobe (DQS) signal for memory devices not designed for adjusting such alignment is provided. Alignment between data signals (DQ) and a DQS signal is first achieved during a first write training procedure where a data delay value is optimized for one of the DQS or DQ signals. Subsequently, using the optimum delay value from the first write training procedure, a second write training procedure is initiated. In the second write training procedure, timing alignment between the DM signal and the DQ signals is achieved by determining an optimal delay value of the DM signal relative to the DQS signal.

Abstract: A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

Abstract: A semiconductor memory device includes: an enable signal generation portion suitable for generating a data output enable signal activated at a predetermined first moment corresponding to column address strobe (CAS) latency based on a read command, a strobe signal generation portion suitable for generating a data strobe signal which has a preamble section until the data output enable signal is activated from a predetermined second moment ahead of the first moment based on the read command and toggles based on a source clock during an activated section of the data output enable signal, and a data output portion suitable for outputting internal data in synchronization with the data strobe signal during the activated section of the data output enable signal.

Abstract: A printhead including a fluid ejector chip having an electrical interface. The electrical interface includes one or more inputs for receiving respective primitive address data and heater address data corresponding to each of one or more address cycles, at least one of the one or more inputs being switchable to a deactivated state, and one or more shift registers, a total number of shift registers being adjustable so that each of the one or more shift registers corresponds to a respective one of the one or more inputs that is not in a deactivated state, the one or more shift registers receiving the respective primitive address data and heater address data from the one or more inputs that are not in a deactivated state to allow for selective application of electrical signals to the heating elements so that fluid is ejected from the fluid ejector chip in accordance with image data.

Abstract: Techniques are disclosed relating to a cache configured to store state information for texture mapping. In one embodiment, a texture state cache includes a plurality of entries configured to store state information relating to one or more stored textures. In this embodiment, the texture state cache also includes texture processing circuitry configured to retrieve state information for one of the stored textures from one of the entries in the texture state cache and determine pixel attributes based on the texture and the retrieved state information. The state information may include texture state information and sampler state information, in some embodiments. The texture state cache may allow for reduced rending times and power consumption, in some embodiments.

Abstract: A peripheral interface circuit at host side and an electronic system using the same is disclosed. The peripheral interface circuit has a bus clock signal generator and a data register. The bus clock signal generator outputs a bus clock signal based on a host clock signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data. The data register receives the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. The bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal.

Abstract: Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to adjust a level of a first strobe signal to a predetermined level during a first time period. The semiconductor device may be configured to adjust a swing width of the first strobe signal during a second time period.

Abstract: An embedded multimedia card (eMMC) is provided. The eMMC includes a clock channel receiving a clock output from a host, data channels receiving data signals from the host, and a command channel receiving a SWITCH command including delay offset values from the host so as to adjust a delay of at least one of the data signals, which are received, in response to the delay offset values.

Abstract: A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Abstract: A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.