Testing Patents (Class 365/201)
  • Patent number: 11605443
    Abstract: The present disclosure provides a test method and a test apparatus for a semiconductor device. The test method includes: forming a plurality of test values based on a first retention time range and a first step size, and sequentially testing a plurality of memory cells in the semiconductor device based on the plurality of test values in ascending order; determining, during tests corresponding to each test value, a memory cell whose retention time is less than the test value, and recording a position and corresponding test value of the memory cell whose retention time is less than the test value, to form first test data; a similar method is applied to form second test data; and determining, based on the first test data and the second test data, positions and corresponding test values of memory cells whose retention times fail to pass the tests.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: March 14, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yu-Ting Cheng
  • Patent number: 11604607
    Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Xinghui Duan, Eric Kwok Fung Yuen, Zhi Ping Yu, Guanzhong Wang
  • Patent number: 11604693
    Abstract: A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: March 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yesin Ryu, Sunggi Ahn, Jaeyoun Youn
  • Patent number: 11605416
    Abstract: Methods, systems, and devices for reducing duty cycle degradation for a signal path are described. In some examples, a memory system may alternate a polarity of a signal line or signal path that includes a set of transistors during successive active periods of the memory system. In some cases, the memory device may include an inversion control component configured to operate the signal using either a first polarity or a second polarity. The inversion control component may receive an indication when the memory system enters an active period, and may accordingly alternate or the polarity of the signal path during successive active periods. In some examples, the signal path may be coupled with one or more output components which may uninvert signals from the signal path when the inversion control component has inverted the polarity of the signal path.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Roman A. Royer
  • Patent number: 11600353
    Abstract: A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: March 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung Hyuk Lee
  • Patent number: 11594275
    Abstract: The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 28, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xing Liu, Xiaodong Luo
  • Patent number: 11594298
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Randall J. Rooney
  • Patent number: 11587636
    Abstract: The disclosure relates to a system and method for maintaining stability during a scan shift operation on multiple embedded memories in an integrated circuit. Examples disclosed herein include an integrated circuit comprising a plurality of memory modules and a built-in self-test controller, wherein the BIST controller and memory modules are arranged and configured to reduce toggling of cells in the memory modules during a scan shift operation.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: February 21, 2023
    Assignee: NXP USA, Inc.
    Inventors: Wenbin Yang, Weiwei Sang
  • Patent number: 11587635
    Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Nevil N. Gajera, Mingdong Cui, Fabio Pellizzer
  • Patent number: 11574676
    Abstract: A memory device is disclosed. The memory device includes at least one reference cell and multiple sense amplifiers. The at least one reference cell having a first terminal coupled to a ground. Each of the sense amplifiers has a first terminal and a second terminal. The first terminal is coupled to one of multiple first data lines, and the second terminal is coupled to a second terminal of the at least one reference cell.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiroki Noguchi, Ku-Feng Lin
  • Patent number: 11575365
    Abstract: An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: February 7, 2023
    Assignee: SK hynix Inc.
    Inventor: Ho Don Jung
  • Patent number: 11568938
    Abstract: A data storage device includes one or more memory devices that each includes one or more superblocks and a controller coupled to the one or more memory devices. Each superblock includes a plurality of wordlines. The controller is configured to write data to a first wordline of the plurality of wordlines, write data to a second wordline of the plurality of wordlines, perform a read verify operation on the first wordline, and perform a read verify operation on the second wordline. At least one of the first wordline and the second wordline does not include an XOR parity element and one or more wordlines of the plurality of wordlines includes the XOR parity element.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 31, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Liam Parker, Yuval Shohet, Michelle Martin
  • Patent number: 11557333
    Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 17, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Chong J. Zhao, James A. McCall, Shigeki Tomishima, George Vergis, Kuljit S. Bains
  • Patent number: 11556616
    Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 17, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Minghai Qin, Pi-Feng Chiu, Wen Ma, Won Ho Choi
  • Patent number: 11557360
    Abstract: The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 17, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yan-De Lin, Jui-Hsiu Jao
  • Patent number: 11545200
    Abstract: A data control circuit includes a first latch circuit, a self-block circuit, a second latch circuit, a third latch circuit, a first data timing-labeled signal generating circuit, and a second data timing-labeled signal generating circuit. The first latch circuit is arranged to receive a data window signal. The self-block circuit is coupled to the first latch circuit, and is arranged to generate a protection signal. The second latch circuit is coupled to the self-block circuit, and is arranged to output a first data timing-labeled signal. The third latch circuit is coupled to the second latch circuit, and is arranged to generate a second data timing-labeled signal. The first data timing-labeled signal generating circuit is arranged to generate a third data timing-labeled signal. The second data timing-labeled signal generating circuit is arranged to generate a fourth data timing-labeled signal.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: January 3, 2023
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 11538548
    Abstract: A memory may include a first repair analysis circuit suitable for storing an input fail address when the input fail address is different from a fail address which is already stored in the first repair analysis circuit, and outputting the input fail address as a first transfer fail address when a storage capacity of the first repair analysis circuit is full; and a second repair analysis circuit suitable for storing the first transfer fail address when the first transfer fail address is different from a fail address which is already stored in the second repair analysis circuit.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: December 27, 2022
    Assignee: SK hynix Inc.
    Inventor: Hosung Cho
  • Patent number: 11531320
    Abstract: A numerical controller that collects data from an industrial machine and writes data into a storage medium includes: an interval setting unit that sets a time interval between cycles in which one cycle involves collection of operation information indicating an operating state of the industrial machine and writing of the collected operation information to the storage medium; a reduced service life calculation unit that calculates a service life of the number of writes of the storage medium reduced by the writing on the basis of the set time interval as a reduced service life; a determining unit that determines whether the calculated reduced service life exceeds a prescribed threshold; and a signal output unit that outputs a signal indicating that the reduced service life exceeds the prescribed threshold when it is determined that the reduced service life exceeds the prescribed threshold.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: December 20, 2022
    Assignee: FANUC CORPORATION
    Inventor: Shinichi Ozeki
  • Patent number: 11527297
    Abstract: Disclosed herein is a semiconductor device including a non-volatile memory unit. The non-volatile memory unit has a subject current path disposed in a semiconductor integrated circuit and a fuse element inserted in series on the subject current path, and changes output data according to a voltage between both ends of the fuse element when supply of a subject current to the subject current path is intended. A current supply part that switches the subject current between a plurality of stages is disposed in the non-volatile memory unit.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: December 13, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Shun Fukushima
  • Patent number: 11526278
    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 13, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Guanhao Shen, Ravindra N. Bhargava, James Raymond Magro, Kedarnath Balakrishnan, Kevin M. Brandl
  • Patent number: 11526453
    Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a read state circuit configured to control the schedule/timing associated with parallel pipelines, and (2) a timing control circuit configured to coordinate output of data from the parallel pipelines.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, Navya Sri Sreeram, Ryo Fujimaki
  • Patent number: 11528126
    Abstract: This document includes techniques, apparatuses, and systems related to an interface for revision-limited memory, which can improve various computing aspects and performance. In aspects, confidentiality, integrity, and availability may be ensured while increasing the performance of revision-limited memory. In this example, the techniques also enable the digital computing device to interact with information related to the revision-limited memory.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 13, 2022
    Assignee: Google LLC
    Inventors: Eunchan Kim, Michael Stefano Fritz Schaffner, Timothy Jay Chen, Christopher Gori, Ziv Hershman, Miguel Angel Osorio
  • Patent number: 11520528
    Abstract: A semiconductor memory device includes a test pattern data storage configured to store test write pattern data in response to a register write command and a register address and output test read pattern data in response to a test read command and a test pattern data selection signal during a test operation, a memory cell array including a plurality of memory cells and configured to generate read data, a read path unit configured to generate n read data, by serializing the read data, and a test read data generation unit configured to generate n test read data, by comparing the test read pattern data with each of the n read data, generated at a first data rate, and generate the n test read data, at a second data rate lower than the first data rate, during the test operation.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: December 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongjun Jin, Yongjae Lee, Seunghan Kim, Hyoungjoo Kim
  • Patent number: 11508453
    Abstract: Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jason M. Johnson
  • Patent number: 11508804
    Abstract: The present disclosure discloses an organic light emitting display device. The organic light emitting display device includes a substrate, an initializing voltage input line, a first electrode line, a thin film transistor, and an organic light emitting diode arranged on the substrate. The thin film transistor includes a first electrode, a second electrode and a control electrode, and the first electrode is coupled to the first electrode line, the initializing voltage input line is provided in the same layer and is made of the same material as one of the first electrode, the second electrode and the control electrode of the thin film transistor, and an extension direction of the initializing voltage input line is substantially the same as an extension direction of the first electrode line.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 22, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS, CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liman Peng, Qi Liu, Dianjie Hou, Xueguang Hao, Jin Yang, Zihua Li, Yan Wu, Guoping Zhang, Haifeng Xu, Lei Wang, Wenxiu Li, Jianqiang Wang, Fan Yang
  • Patent number: 11501823
    Abstract: A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangyun Kim, Younghun Seo, Hyejung Kwon, Myungkyu Lee, Sunghye Cho
  • Patent number: 11495287
    Abstract: A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a transpose cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The transpose cell is connected to the memory cell and receives the weight via the local bit line. The transpose cell includes an input bit line, an input bit line bar, an output bit line and an output bit line bar. Each of the input bit line and the input bit line bar transmits a multi-bit input value, and the transpose cell is controlled by the second word line to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value and the weight.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: November 8, 2022
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Yung-Ning Tu, Xin Si, Wei-Hsing Huang
  • Patent number: 11494265
    Abstract: In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: November 8, 2022
    Assignee: NVIDIA Corporation
    Inventor: Nirmal R. Saxena
  • Patent number: 11488679
    Abstract: Disclosed is a method for grading memory modules comprising: a testing step which applies at least one test procedure to test a memory, each test procedure is provided with a reliability test; and a grading step which grades the memory into corresponding grade level according to test results of said at least one test procedure, and each test result includes a reliability test result wherein the reliability test has the following steps in sequence: performing a data-writing operation on the memory, wherein the data-writing operation is an operation that writes data to the memory; stopping electric charging the memory; halting a predetermined time period; electric charging the memory; checking data integrity of the memory; and generating the reliability test result according to the data integrity.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: November 1, 2022
    Assignee: TEAM GROUP INC.
    Inventors: Hsi-Lin Kuo, Ming-Hsun Chung, Chin-Feng Chang
  • Patent number: 11486926
    Abstract: Examples described herein provide a wearout card and a method for using the wearout card. The wearout card generally includes a first set of connectors configured to connect the testing apparatus to a testing controller, and a second set of connectors configured to connect the testing apparatus to a device under test (DUT). The wearout card can also include a memory configured to store identifying information of the testing apparatus and a use counter indicating a number of times different DUTs have been connected to the second set of connectors.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 1, 2022
    Assignee: XILINX, INC.
    Inventor: Robert Andrew Daniels
  • Patent number: 11487561
    Abstract: According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analysis tool to provide post-processing debug, including searching forward and backward in capture time of the stored memory view to analyze the events of the simulation. The memory is constructed by capturing and storing each memory execution transaction, bus transaction, and register transaction during simulation. Changes in simulation platform hardware state may also be captured and stored in a hardware state database, including switches between process threads detected during the simulation that may update a simulator register. The captured events provide observability into the OS processes, the hardware, and the embedded software of the simulation platform.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: November 1, 2022
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Andrew Wilmot, Neeti Khullar Bhatnagar, Qizhang Chao, George Franklin Frazier
  • Patent number: 11487276
    Abstract: A method of salvaging an output is provided. The method includes defining a condition for terminating a run of a tool, checking whether the condition is likely to be met during a running of the tool, terminating the running in an event the condition is likely to be met, checking a validity of an incomplete output of the tool generated during the running and finalizing the incomplete output in an event the incomplete output is valid.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Oz Dov Hershkovitz
  • Patent number: 11481624
    Abstract: A NAND memory device that includes a plurality of blocks, each block comprises a plurality of wordlines and an associated agent, and each wordline comprises a plurality of cells and a plurality of voltage levels and an associated agent, and each voltage level comprises an agent. A method of programming the NAND memory device includes receiving, by an agent at a given rank in the plurality of ranks, parameters from a higher rank agent in the hierarchy of ranks and a state from the memory device; determining, by the agent, an action from the parameters and the state; passing the action as parameters to a lower rank agent in the hierarchy of ranks; and updating the agent based on a reward output by the agent, wherein the reward measures a difference between the target voltage levels of the cells and the actual voltage levels programmed to the cells.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Evgeny Blaichman, Amit Berman, Elisha Halperin, Dan Elbaz
  • Patent number: 11476169
    Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: October 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Sun Myung Choi
  • Patent number: 11475964
    Abstract: A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: October 18, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Haibo Li, Qiang Tang
  • Patent number: 11475975
    Abstract: The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block including memory cells, a peripheral circuit configured to program the memory cells in a set program state during a test operation and perform a test erase voltage application operation on the memory cells programmed in the set program state, and control logic configured to control the peripheral circuit to count abnormal memory cells of which a threshold voltage is less than a set threshold voltage among the memory cells.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: October 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong Wook Kim
  • Patent number: 11474890
    Abstract: The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of semiconductor memories, and a controller for controlling the memory device to perform a test program operation and a threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories during an operation. The controller sets operation performance parameters of each of the semiconductor memories based on monitoring information obtained as a result of the threshold voltage distribution monitoring operation.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: October 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong Wook Kim
  • Patent number: 11468966
    Abstract: The present disclosure provides an operation method related to a post package repair (PPR) function in a dynamic random access memory (DRAM) device. The method for operating a post package repair (PPR) function of a memory device is disclosed. The method includes providing a memory bank, which includes a memory array and a sense amplifier adjacent to the memory array, wherein the memory array comprises at least one defective row and at least one associated row, and the at least one associated row is electrically connected to the sense amplifier by a plurality of bit lines. The method also includes arranging a redundant row adjacent to the memory array, wherein the redundant row is electrically connected to the sense amplifier by the plurality of bit lines.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: October 11, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Nung Yen
  • Patent number: 11462290
    Abstract: The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: October 4, 2022
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Zhenan Lai, Junsheng Chen, Zhaoying Huang
  • Patent number: 11462287
    Abstract: The present disclosure provides a memory test method, a storage medium and a computer device. The memory test method comprises: obtaining a target test pattern that needs to be written into a plurality of chip interfaces, the plurality of chip interfaces being connected to a plurality of physical interfaces in a one-to-one correspondence; determining second information of the chip interfaces corresponding to first information of the physical interfaces, and using the first information and the second information as corresponding connection information; remapping the corresponding connection information to obtain mapped connection information; and determining, according to the target test pattern and the mapped connection information, an initial test pattern that needs to be written into the physical interfaces.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 4, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Guangteng Long, Hao He, Dan Lu, Bo Hu
  • Patent number: 11462285
    Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Sungmook Lim, In Gon Yang, Jae Hyeon Shin, Hyung Jin Choi
  • Patent number: 11462284
    Abstract: A system and method are provided for a analyzing a refresh rate of a device under test (DUT) such as a volatile memory device that includes a memory and an associated memory controller. The method includes acquiring refresh data based upon signals between the memory and the memory controller of the volatile memory device over a time period, determining the refresh rate of the volatile memory device for time windows of the time period based upon the acquired refresh data, and displaying the refresh rate of the volatile memory device, compared to a refresh threshold, on a graphical user interface (GUI), for each of the time windows over the time period.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 4, 2022
    Assignee: Keysight Technologies, Inc.
    Inventors: Michael Shaun Backsen, Frank D. Simon, Jennie Colleen Grosslight
  • Patent number: 11461050
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enforcing a decay policy for a data object. One of the methods includes receiving a request to store a data object in a storage device; obtaining a user policy identifying a lifetime of the data object; determining, using the lifetime of the data object, a voltage policy for a plurality of memory cells of the storage device, wherein: each of the plurality of memory cells will store one or more bits of the data object; the voltage policy identifies a voltage to provide each memory cell; and an expected time at which raw bit errors of the data object will cause the data object to decay is equal to a time point identified by the lifetime of the data object; and storing the data object in the storage device according to the determined voltage policy.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: October 4, 2022
    Assignee: VMware, Inc.
    Inventors: Amy Tai, Michael Wei
  • Patent number: 11443782
    Abstract: An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11442940
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Libo Wang, Di Wu, James S. Rehmeyer, Anthony D. Veches
  • Patent number: 11437114
    Abstract: A first set of 64 bytes of data and a second set of 64 bytes of data are received. A first set of eight error-correcting code (ECC) bytes for the first set of 64 bytes of data and a second set of eight ECC bytes for the second set of 64 bytes of data are calculated. The first set of 64 bytes of data, the second set of 64 bytes of data, the first set of eight ECC bytes, and the second set of eight ECC bytes are sent to one or more 5th generation double data rate (DDR5) synchronous dynamic random-access memory (SDRAM) modules through a DDR5 dual-channel in a single burst, wherein the DDR5 dual-channel comprises a first data channel and a second data channel, and wherein the first data channel and the second data channel are driven by a same clock signal.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: September 6, 2022
    Assignee: Meta Platforms, Inc.
    Inventors: Narsing Krishna Vijayrao, Christian Markus Petersen
  • Patent number: 11437097
    Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Corrado Villa, Ferdinando Bedeschi, Paolo Fantini
  • Patent number: 11437118
    Abstract: A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: September 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungik Jang, Kihyun Kim, Soojin Ann, Chungki Lee, Dongguk Han
  • Patent number: 11437111
    Abstract: Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. McNeil, Jr., Karl D. Schuh, Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Kishore K. Muchherla, Gil Golov, Todd A. Marquart, Jiangang Wu, Niccolo' Righetti, Ashutosh Malshe
  • Patent number: 11429769
    Abstract: Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 30, 2022
    Assignee: Xilinx, Inc.
    Inventors: Pradip Kar, Nithin Kumar Guggilla, Chaithanya Dudha, Satyaprakash Pareek