Abstract: A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.

Abstract: The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resistance element may have at least a first resistance value and a second resistance value higher than the first resistance value. The contact arrangement portion is formed to arrange a plurality of contacts on a plane. The contacts are connected to the first wirings or the second wirings. The probe can move along the plane to electrically contact with either of the contacts.

Abstract: Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control signal and transfer amplified data to the second data line, and a second transfer unit configured to electrically connect the first data line to the second data line in response to a second control signal.

Abstract: A circuit comprises a first read bit line, a second read bit line, and a sense amplifier. First and second read bit lines couple a plurality of memory cells and a reference cell of a memory array, respectively. The sense amplifier is configured to receive the first read bit line as a first input and the second read bit line as a second input. When a memory cell of the first plurality of memory cells is read, the memory cell is read activated, the first reference cell is configured to be off, the second reference cell is configured to be on, and the sense amplifier is configured to provide an output reflecting a data logic stored in the memory cell based on a voltage difference between a first voltage of the first read bit line and a second voltage of the second read bit line.

Abstract: A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.

Abstract: A semiconductor memory circuit includes a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecting unit for selecting the memory cells of the memory cell array aligned in the column direction; a plurality of main bit lines for outputting data of the memory cells; a data reading unit for reading data of one of the memory cells selected with the row selecting unit and the column selecting unit; a first multiplexer for connecting one of the main bit lines connected to the memory cell to the data reading unit; and a second multiplexer for connecting an adjacent main bit line situated adjacently outside the main bit line to a charging/discharging voltage source for setting at a specific voltage.

Abstract: A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output.

Abstract: In some embodiments a voltage regulator provides an operation voltage to a memory system and a transient voltage supply adjusts the operation voltage provided by the voltage regulator during transient events of the memory system. Additionally, the voltage supply may adjust the operation voltage provided to the memory system at a fixed time interval that corresponds to a worst case load transient event.

Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.

Abstract: Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.

Abstract: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

Abstract: Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus are presented. The circuits and methods are responsive to an idle condition on the bidirectional bus. The control signal is applied to and changes an electrical characteristic within the receiver to generate a voltage offset. The voltage offset prevents unintended voltage transitions in the power supply of circuits coupled to the bidirectional bus from generating a signal transition on an output signal connection of the receiver.

Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.

Abstract: A method of efficiently programming charge-trapping memory cells includes sense amplifiers being dynamically connected to cells to be programmed, by switching bit lines. The method increases a number of cells that can be programmed simultaneously, such that an optimal use of sense amplifier resources is obtained.

Abstract: Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A non-volatile semiconductor memory is disclosed comprising a memory device including a plurality of memory segments. A program command is issued to the memory device to program a memory segment, and a program time required to execute the program command is saved. An erase command is issued to the memory device to erase the memory segment, and an erase time required to execute the erase command is saved. A wear leveling algorithm is executed for the memory segment in response to the program time and the erase time.

Abstract: Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit may allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided.

Abstract: A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.

Abstract: A DC mode word-line coupling noise restriction circuit for multiple-port Random Access Memory cells. This circuit may comprise a Static Random Access Memory array. The SRAM array contains a plurality of columns and a plurality of rows with an SRAM cell formed at a cross-point of the columns and rows. Each SRAM cell has a first word-line conductor and a second word-line conductor. The first word-line conductor is connected to a first coupling noise restriction circuit. The first coupling noise restriction circuit comprises an inverter and a NMOSFET. The inverter has another NMOSFET and a PMOSFET.

Abstract: A semiconductor memory device adjusts a timing interval between the activation of first and second amplifiers in a sense amplifier circuit based on the distance between the sense amplifier circuit and corresponding power supply.

Abstract: A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling up a voltage of one of the second I/O pair to a full power voltage level.

Abstract: A device, computer system, and method are disclosed. In one embodiment, the device includes a memory buffer driver circuit that can drive signals on a memory channel at a given voltage level. The voltage at the voltage level is supplied to the memory buffer driver circuit from a rail of a power delivery network. The voltage level exhibits a repeatable fluctuation cycle at a resonant frequency of the power delivery network. The device also includes an on-die termination logic circuit that asserts a first termination resistance on the memory channel after the memory channel enters an idle state but before the voltage level reaches a peak of the repeatable fluctuation cycle. The on-die termination logic circuit then deasserts the first termination resistance on the memory channel at a later point in time.

Abstract: The disclosure provides a method for reducing an amount of simultaneous switching outputs (SSO) of a device. The method of reducing the amount of simultaneous switching outputs can include driving outputs of the device to a first set of values, scrambling a second set of values to reduce an amount of simultaneous switching outputs resulting from the switching of the first to the second set of values, and driving the outputs of the device to the scrambled second set of values. Further, the method can include descrambling the scrambled second set of values back to the second set of values.

Abstract: Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.

Abstract: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage.

Abstract: A storage device includes: a printed circuit board; a semiconductor memory package mounted on the printed circuit board via solder joints, the semiconductor memory package incorporating semiconductor memories; a sensor configured to measure a physical quantity relating to a state of the storage device; a database including a damage estimation model base to be used for estimating damage of the solder joints from the physical quantity measured by the sensor; a damage estimating module configured to calculate a damage estimation value of the solder joints from the physical quantity using the damage estimation model base; and a controller configured to control writing, reading, and erasure of electronic data to or from the semiconductor memories based on the damage estimation values calculated by the damage estimating module.

Abstract: Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source.

Abstract: A sense amplifier and method of implementing includes a reference current generation circuit, which is used for providing a reference current with a settable temperature coefficient for a main circuit of the sense amplifier; the main circuit is used for comparing the reference current with a storage cell current, and distinguishing between 0 and 1 Storage Cell. A method of implementing the sense amplifier that is as below: With an additional current reference circuit, generating and inputting the reference current with a positive/negative/zero temperature coefficient into the main circuit, by mixing a proportional absolute temperature current and a constant current according to different ratios; a storage cell selection tube in a mirror branch of a biased current of the main circuit, so as to constitute a source degeneration circuit, making the biased current change with the power supply voltage and realizing a gain compensation function.

Abstract: A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path is coupled to a first split path including a first load transistor and to a second split path including a second load transistor. The second path is coupled to a third split path including a third load transistor and to a fourth split path including a fourth load transistor.

Abstract: An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory.

Abstract: A word driver supplies a high level voltage to a word line when a memory cell is accessed and supplies low level voltage which is a negative voltage to the word line when the memory cell isn't accessed. A precharge circuit lowers a precharge voltage-supplying capacity to a bit line at least during a standby period when the memory cell is not accessed. A substrate voltage of an nMOS transistor with source or drain connected to the bit line is set to the low level voltage or lower of the word line. Therefore, when the word line and the bit line fails short and the voltage of the bit line changes to the low level voltage of the word line during the standby period, a substrate current can be prevented from flowing between the source of the nMOS transistor and a substrate or the drain and the substrate.

Abstract: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.

Abstract: A semiconductor device includes: a first level detecting circuit for detecting a voltage level at a control terminal after a prescribed time period from when a power supply voltage is supplied to a power supply terminal, a control unit for selecting in which operation mode among a plurality of operation modes the semiconductor device operates, based on a result of detection by the first level detecting circuit; and a regulator for generating an internal power supply voltage based on the power supply voltage supplied to the power supply terminal. The first level detecting circuit and the control unit receive the internal power supply voltage as an operating power supply voltage. In an operation mode, among the plurality of operation modes, where a power supply voltage having a level different from that of a power supply voltage in other operation modes is supplied to the power supply terminal, the control unit performs data processing by using the power supply voltage supplied to the power supply terminal.

Abstract: In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.

Abstract: A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a first sense circuit connected to the bit line and configured to amplify a signal read out from the memory cell; and a second sense circuit connected to the local bit lines and configured to amplify a signal amplified by the first sense circuit, wherein the first switch unit disconnects the local bit line from the bit line when the first sense circuit amplifies the signal, and connects the local bit line to the bit line when the second sense circuit amplifies the signal amplified by the first sense circuit.

Abstract: The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resistance element may have at least a first resistance value and a second resistance value higher than the first resistance value. The contact arrangement portion is formed to arrange a plurality of contacts on a plane. The contacts are connected to the first wirings or the second wirings. The probe can move along the plane to electrically contact with either of the contacts.

Abstract: Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.

Abstract: Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.

Abstract: In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits.

Abstract: A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Abstract: Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

Abstract: A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.

Abstract: Some embodiments include a first circuit to drive signals at first circuit output nodes, and a second circuit to generate output signals at second circuit output nodes. The second circuit includes a first transistor coupled between a supply node and a first node of the second circuit output nodes and a second transistor coupled between the supply node and a second node of the second circuit output nodes. Each of the first and second transistors includes a gate coupled to one of the first and second nodes. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry.

Abstract: A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory cell along the selected row and, for each column, using a respective local sense amplifier and a column sense amplifier to successively differentiate a voltage across the associated memory cell in said column to output a programmed content of the row.

Abstract: A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

Abstract: Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.

Abstract: A memory integrated circuit (IC) includes an input that receives data for programming a target cell to a state. The memory IC further includes a programming module that determines a programming value for programming the target cell to the state based on the state and states of C cells that are adjacent to the target cell. The target cell and the C cells each store K bits per cell, where C and K are integers greater than or equal to 1.