Abstract: A read-out circuit for or in a ROM memory, comprises an input, a comparator circuit, a threshold setting, and a control signal generator for driving the threshold setting generator. A read signal can be coupled into the input. The read signal, depending on the information contained in the read signal, comprises a high signal level relative to a reference potential or a low signal level relative to a reference potential. The comparator circuit compares the read signal with a settable threshold, the threshold setting circuit is designed for setting the threshold of the comparator circuit relative to the high and low signal levels, and the control signal generator generates a control signal similar to the read signal.

Abstract: Provided is a memory device that can detect a mismatch in a bit line sense amp, wherein the memory device includes a sense amp drive unit for selectively supplying a pull-up drive voltage or a pull-down drive voltage to a bit line sense amp in response to a sensing test signal provided from outside.

Abstract: Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

Abstract: A memory cell array includes a memory cell comprising a ferroelectric capacitor and a transistor arranged therein. A plate line applies a drive voltage to one end of the ferroelectric capacitor. A bit line reads data stored in the memory cell from the other end of the ferroelectric capacitor. A sense amplifier circuit detects and amplifies a signal read to the bit line from the ferroelectric capacitor. A bit line voltage control circuit performs control of changing a voltage of the bit line to which the signal is read, thereby pulling up a potential difference between the plate line and the bit line, prior to operation of the sense amplifier circuit for data read. The bit line voltage control circuit varies a range of variation of the voltage of the bit line depending on ambient temperature.

Abstract: A sensing amplifier for a memory cell comprises a selection stage that outputs one of a reference current and a memory cell current during a first period and the other of the reference current and the memory cell current during a second period. The first period and the second period are non-overlapping. An input stage generates a first current based on the one of the reference current and the memory cell current during the first period and generates a second current based on the other of the reference current and the memory cell current during the second period. A sensing stage senses a first value based on the first current and stores the first value during the first period, senses a second value based on the second current during the second period and compares the first value to the second value.

Abstract: A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and are disposed in the center region of the well, while non-sensitive element is disposed in the peripheral region close to the boundary in the well. Since sensitive element requiring precise control of threshold voltage is disposed in the center region having uniform impurity density, and non-sensitive element allowing for less precise control of threshold voltage is disposed in the peripheral region suffering from uneven impurity density, it is possible to effectively use the overall area of the well and to thereby suppress an increase in the layout area of chips.

Abstract: A semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying unit coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying unit in response to a control signal.

Abstract: A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the second bias different from the first bias. The method includes determining a data value stored in the memory cell based on a difference between the first and second responses and a predetermined reference.

Abstract: A memory device and method for improving speed at which data is read from non-volatile memory are provided, where the memory device including the non-volatile memory precharges all word lines with a predetermined precharge voltage during standby for a read operation, in which data is read from the non-volatile memory, and then, during the read operation, pulls up a voltage of only a word line selected by a row address to a read voltage and pulls down a voltage of remaining unselected word lines down to a ground voltage, such that data reading speed of the memory device is increased.

Abstract: A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

Abstract: A semiconductor device may include, but is not limited to, a first signal line, a second signal line, and a first shield line. The first signal line is supplied with a first signal. The first signal is smaller in amplitude than a potential difference between a power potential and a reference potential. The second signal line is disposed in a first side of the first signal line. The second signal line is supplied with a second signal. The second signal is smaller in amplitude than the potential difference. The first shield line is disposed in a second side of the first signal line. The second side is opposite to the first side. The first shield line reduces a coupling noise that is applied to the first shield line from the second side.

Abstract: An integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first and second input terminals; a signal line connected to the memory cells, the reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. A method of operating the integrated circuit includes closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first and second voltages using the voltage comparator, wherein the first voltage represents a memory state of a memory cell, and the second voltage is a reference voltage which represents a memory state of a reference cell, or vice versa.

Abstract: An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by a first voltage drop amount in response to a test mode signal; and a second voltage drop unit for transferring the bit line precharge voltage to a second output node after decreasing the bit line precharge voltage by a second voltage drop amount in response to the test mode signal, wherein the second voltage drop amount is greater than the first voltage drop amount.

Abstract: A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines. A design structure embodied in a machine readable medium used in a design process, includes such a circuit for accessing a memory cell.

Abstract: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.

Abstract: A semiconductor memory device includes a first memory cell array that comprises first memory cells arranged in a matrix of first rows and first columns; a second memory cell array that comprises second memory cells arranged in a matrix of second rows and second columns; a row decoder that is configured to select and activate one of the rows of the first and second cell arrays in response to a row address; a sense amplifier that may be disposed between the first memory cell array and the second memory cell array; a switch that is configured to selectively connect the sense amplifier to the first memory cell array and the second memory cell array; and a switch controller that is configured to control the switch to connect the sense amplifier to one of the first and second memory cell arrays based on the row address.

Abstract: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

Abstract: A sense amplifier comprises: a differential amplifier circuit configured to generate an amplified signal depending on a difference in voltage between bit lines; an output circuit receiving the amplified signal; and a load. The differential amplifier circuit comprises: a first output node supplying the amplified signal to the output circuit; and a second output node symmetrically placed with respect to the first output node and connected to the load. The output circuit comprises an output terminal for outputting an output signal generated based on the amplified signal.

Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

Abstract: A sense amplifier control circuit which can be used in a semiconductor device includes an enable signal generator for decoding a plurality of internal commands, to output a first enable signal and a second enable signal which are enabled in an active mode of a semiconductor device, a first driving control signal generator for generating a first driving control signal adapted to control a driving period of a pull-down source line of a sense amplifier included in the semiconductor device, a second driving control signal generator for comparing a voltage level of a pull-up source line of the sense amplifier with a predetermined internal voltage, and generating a second driving control signal which is enabled when the voltage level of the pull-up source line is higher than the internal voltage, to control the driving period of the pull-up source line, and a third driving control signal generator for generating a third driving control signal which is disabled in response to enabling of the second driving control s

Abstract: A semiconductor memory device comprises a sense amplifier circuit having a first and a second input terminal, the sense amplifier configured to compare current flowing in the first input terminal with current flowing in the second input terminal, and the sense amplifier configured to provide the result to external; a first gate circuit connected to the first input terminal, the first gate circuit configured to pass a cell current flowing in a memory cell to the first input terminal; a reference current source, the reference current source configured to feed a reference current to the second input terminal, the reference current serving as the reference for level sensing the cell current; a second gate circuit connected to the second input terminal, the second gate circuit including a replica circuit of the first gate circuit; a first current source configured to feed a first current to the first input terminal, the first current corresponding to the offset at the time of read from a first-state cell; and a se

Abstract: A non-volatile memory device may include at least one string, at least one bit line corresponding to the at least one string, and/or a sensing transistor. The at least one string may include a plurality of memory cell transistors connected in series. The sensing transistor may include a gate configured to sense a voltage of the corresponding bit line. A threshold voltage of the sensing transistor may be higher than a voltage obtained by subtracting a given voltage from a voltage applied to read the corresponding bit line connected to a memory cell transistor to be read of the plurality of memory cell transistors.

Abstract: A semiconductor memory device includes a shared transistor controlling coupling between a bit line pair in a memory cell array and a bit line pair in a sense amplifier. After a word line is activated and the sense amplifier amplifies the potential difference between the bit lines of the bit line pair in the sense amplifier, the shared transistor is tuned OFF and precharge/equalizing circuit is activated to precharge the bit lines in the sense amplifier to a potential which is half the internal power source potential.

Abstract: An integrated cell for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the sign of the difference invariable.

Abstract: A memory cell array includes memory cells disposed in a matrix. A plurality of word-lines are arranged in the memory cell array to select a memory cell in a row direction. A read bit-line pair is arranged in a direction perpendicular to the word-line to read data from the memory cell. In addition, a write bit-line is arranged in a direction perpendicular to the word-line to write data to the memory cell. The read bit-line pair includes a true and a complementary read bit-line. One of the true and complementary read bit-lines is connected to the memory cell connected to an even-numbered word-line. The other one is connected to the memory cell connected to an odd-numbered word-line.

Abstract: A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory device in the overdriving operation. The semiconductor memory device includes a bit line sense amplifier for performing an amplification operation using a normal driving voltage or an overdriving voltage to sense and amplify data applied to bit lines, a normal driving voltage compensator configured to drive a normal driving voltage terminal according to a voltage level of the normal driving voltage terminal and target normal driving voltage levels, and a discharge enable signal generator configured to generate a discharge enable signal by adjusting an activation period of the discharge enable signal according to the overdriving voltage.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs.

Abstract: A sense amplifier control unit include: a control unit that detects a variation in the level of an external voltage and outputs a delay time selection signal on the basis of the result of the detection. A variable delay unit delays an active signal by a delay time corresponding to the delay time selection signal and outputs the delayed signal. A driving signal generating unit outputs a driving signal according to the output of the variable delay unit. A sense amplifier driver drives a sense amplifier on the basis of the driving signal.

Abstract: A memory device and method for arranging signal and power lines includes a plurality of sub-memory cell arrays having a plurality of memory cells, a plurality of sense amplifiers to sense and amplify data from the plurality of memory cells, a plurality of power lines to provide power to the sense amplifiers, where at least one of the power lines is disposed over a first set of the sense amplifiers and the sub-memory cell arrays, and at least another one of the power lines is disposed over second set of the sense amplifiers and the sub-memory cell arrays.

Abstract: In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying a precharge signal to a gate of the transistor. The gate electrode of the plurality of sense amplifier portions is provided as one piece as a whole and extends in a direction parallel to a row direction in the memory cell array. A gate electrode portion which is a connected portion between the gate electrode in a k-th sense amplifier portion and the gate electrode in a (k+1)-th sense amplifier portion is ring-shaped, where k is an odd number.

Abstract: A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.

Abstract: A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter than the length of the global digit lines. As a result, the local digit lines have substantially less capacitance so that a voltage stored by a memory cell capacitor can be more easily transferred to the local digit line. The coupling circuits provide current amplification so that the voltage on the local digit lines can be more easily transferred to the global digit lines. A write back circuit is coupled to the local digit line to restore the voltage of the memory cell capacitor.

Abstract: To provide a current sensing circuit that detects a difference between a cell current and a reference current. The current sensing circuit includes: current mirror circuits of which the input terminal is connected with a reference current source; a differential amplifier of which the one input terminal is supplied with a potential of an electrical connection point between an output terminal of the current mirror circuit and a memory cell and of which the other input terminal is supplied with a reference potential; and an equalizing circuit that short-circuits the both input terminals of the differential amplifier in response to an equalizing signal. Thereby, the both input terminals can be kept at the same potential immediately before a sensing operation starts, and thus, even when the cell current is weak, a highly sensitive sensing operation can be performed at high speed.

Abstract: In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

Abstract: A semiconductor memory device may include a power line, an over driver, and/or an internal voltage driver. The power line may be connected to at least one sense amplifier. The at least one sense amplifier may be connected to a memory cell included in a memory block. The memory block may be included in one of a plurality of memory block units including one or more memory blocks. The over driver may be configured to apply an external voltage to the power line in a sensing period of the sense amplifier. The internal voltage driver may be configured to apply an internal voltage to the power line in an amplification period of the sense amplifier. The over driver may be configured to perform an over driving operation by each memory block unit.

Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.

Abstract: Disclosed are methods, systems and devices, including devices having a plurality of data cells. In some embodiments, each data cell includes a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain.

Abstract: A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a first MOSFET having a drain terminal connected with the first node, a second MOSFET having a drain terminal connected with the second node, a memory cell connected with a source terminal of the first MOSFET, and a reference cell. The semiconductor memory device further includes a connection control circuit that connects a source terminal of the second MOSFET with the reference cell at the time of a regular operation and connects the source terminal of the second MOSFET with a reference voltage terminal at the time of a test operation.

Abstract: A semiconductor memory device is capable of swiftly sensing data loaded on local I/O lines and transferring the sensed data to a global I/O line, thereby reducing an operating time of a sense amplifier by increasing the sensing and amplifying speed. The semiconductor memory device includes a sense amplifying unit, a precharging unit, a charge sharing unit, and a driving unit. The sense amplifying unit amplifies data applied to a first data line in response to an I/O strobe signal. The precharging unit precharges an output unit of the sense amplifying unit in response to a precharge signal. The charge sharing unit performs a charge sharing operation between the first data line and the output unit before a sense amplifying operation of the sense amplifying unit. The driving unit drives a second data line in response to an output signal of the sense amplifying unit.

Abstract: An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a programmable resistive memory element, the clamping device configured to clamp a fixed voltage, at a first node of the data leg, across the memory element, thereby establishing a fixed current sinking capability thereof; and a plurality of differential amplifiers, each of the differential amplifiers configured to compare a first voltage input, taken at a second node of the data leg, with a second voltage input; wherein the second voltage input for each differential amplifier comprises different reference voltages with respect to one another so as to enable each differential amplifier to detect a different resistance threshold, thereby determining a specific resistance state of the programmable resistive memory element.

Abstract: A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.

Abstract: A data amplifying circuit for a semiconductor integrated circuit including a controller configured to generate a control signal for adjusting an amplification step in response to a test signal, and a data amplifier configured to amplify an input signal one time or two or more times in response to the control signal and to output an output signal.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

Abstract: Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the applied plurality of different stimuli. An analysis component determines a logic state of each memory cell of the plurality of memory cells as a function of the sensed characteristic of each memory cell of the plurality of memory cells.

Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open.

Abstract: A circuit for supplying power to a sense amplifier in a semiconductor memory apparatus includes: a compensation controlling unit configured to generate a compensation control signal to determine power compensation, in response to a refresh signal. A power compensating unit supplies a compensation voltage input node, which is applied with a first voltage, with a second voltage in response to the compensation control signal. And, a power supply unit configured to supply the second voltage or a voltage at the compensation voltage input node to a sense-amp driver in response to a first power control signal or a second power control signal.